From patchwork Fri Oct 26 04:49:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC67414DE for ; Fri, 26 Oct 2018 04:55:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 947AD2C5B6 for ; Fri, 26 Oct 2018 04:55:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8784D2C5C7; Fri, 26 Oct 2018 04:55:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2DDC22C5B6 for ; Fri, 26 Oct 2018 04:55:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB3346E3EF; Fri, 26 Oct 2018 04:55:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 642EA6E3EE for ; Fri, 26 Oct 2018 04:55:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494109" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:38 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:37 -0700 Message-Id: <20181026044943.29334-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Similar to DSC DPCD registers, let us cache FEC_CAPABLE register to avoid using stale values. With this we can avoid aux reads everytime and instead read the cached values. v2: Avoid using memset and array for a single field. (Manasi,Jani) Suggested-by: Jani Nikula Cc: Jani Nikula Cc: Ville Syrjala Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5a638503e36a..16d1db7c9398 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4198,9 +4198,13 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) /* *Clear the cached register set to avoid using stale values * for the sinks that do not support DSC. + * Similarly, clear the cached FEC register. */ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /* Clear fec_capable to avoid using stale values */ + intel_dp->fec_capable = 0; + /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || intel_dp->edp_dpcd[0] >= DP_EDP_14) { @@ -4214,6 +4218,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) (int)sizeof(intel_dp->dsc_dpcd), intel_dp->dsc_dpcd); } + /* FEC is supported only on DP 1.4 */ + if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) { + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, + &intel_dp->fec_capable) < 0) + DRM_ERROR("Failed to read FEC DPCD register\n"); + } } static bool diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 16bbc3768e02..9a94c6544bf5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1119,6 +1119,7 @@ struct intel_dp { uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; + u8 fec_capable; /* source rates */ int num_source_rates; const int *source_rates; From patchwork Fri Oct 26 04:49:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656915 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 377EF14DE for ; Fri, 26 Oct 2018 04:55:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 274E12C5B6 for ; Fri, 26 Oct 2018 04:55:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1BF8B2C5C7; Fri, 26 Oct 2018 04:55:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CFBB92C5B6 for ; Fri, 26 Oct 2018 04:55:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 118456E3F1; Fri, 26 Oct 2018 04:55:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D987B6E3EE for ; Fri, 26 Oct 2018 04:55:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494114" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:38 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:38 -0700 Message-Id: <20181026044943.29334-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 2/7] drm/dp/fec: DRM helper for Forward Error Correction X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP DP 1.4 has Forward Error Correction Support(FEC). Add helper function to check if the sink device supports FEC. v2: Separate the helper and the code that uses the helper into two separate patches. (Manasi) v3: - Move the code to drm_dp_helper.c (Manasi) - change the return type, code style changes (Gaurav) - Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani) v4: - Avoid aux reads everytime, instead read cached values of dpcd register (jani) - Move helper to drm_dp_helper.h like other dsc helpers.(Anusha) v5: rebased. Change the helper parameter suitably. Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Signed-off-by: Anusha Srivatsa Reviewed-by: Manasi Navare --- include/drm/drm_dp_helper.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 2649529d0d8f..b08f50b852f5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1101,6 +1101,13 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) DP_DSC_SLICE_WIDTH_MULTIPLIER; } +/* Forward Error Correction Support on DP 1.4 */ +static inline bool +drm_dp_sink_supports_fec(const u8 fec_capable) +{ + return fec_capable & DP_FEC_CAPABLE; +} + /* * DisplayPort AUX channel */ From patchwork Fri Oct 26 04:49:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB9B114DE for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AE242C5B6 for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F2EA2C5C7; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CA042C5B6 for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B4656E3FC; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6AECF6E3EE for ; Fri, 26 Oct 2018 04:55:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494118" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:39 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:39 -0700 Message-Id: <20181026044943.29334-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 3/7] i915/dp/fec: Check for FEC Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Check if the sink supports FEC using the helper. v2: Mention External DP where ever FEC is mentioned in the code.Check return status of dpcd reads. (Gaurav) - Do regular mode check even if FEC is not supported. (manasi) v3: Do not perform any dpcd writes in the atomic check phase. (DK, Manasi) v4: Use debug level logging for scenario where sink does not support a feature. (DK) v5: Correct commit message. rebase. v6: pass single field instead of an array for helper function. (manasi) Cc: Gaurav K Singh Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: Anusha Srivatsa Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 16d1db7c9398..cfcef9e4b5d9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -680,7 +680,7 @@ intel_dp_mode_valid(struct drm_connector *connector, dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); - } else { + } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(max_link_clock, max_lanes, @@ -690,7 +690,8 @@ intel_dp_mode_valid(struct drm_connector *connector, intel_dp_dsc_get_slice_count(intel_dp, target_clock, mode->hdisplay); - } + } else + DRM_DEBUG_KMS("Sink device does not Support FEC\n"); } if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || @@ -2063,6 +2064,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp)) return false; + /* DSC not supported if external DP sink does not support FEC */ + if (!intel_dp_is_edp(intel_dp) && + !drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n"); + return false; + } + /* DSC not supported for DSC sink BPC < 8 */ if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) { DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); From patchwork Fri Oct 26 04:49:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656919 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D88D14BD for ; Fri, 26 Oct 2018 04:55:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BF852C5B6 for ; Fri, 26 Oct 2018 04:55:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2088E2C5C7; Fri, 26 Oct 2018 04:55:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CB03C2C5C4 for ; Fri, 26 Oct 2018 04:55:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 366E06E3F4; Fri, 26 Oct 2018 04:55:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0301C6E3F0 for ; Fri, 26 Oct 2018 04:55:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494121" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:39 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:40 -0700 Message-Id: <20181026044943.29334-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 4/7] i915/dp/fec: Add can_fec to the crtc state. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error correction on other scenarios too if needed. Suggested-by: Ville Syrjala Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index cfcef9e4b5d9..4776ce6f2174 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2045,6 +2045,23 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, return false; } +static bool intel_dp_can_fec(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + if (INTEL_GEN(dev_priv) < 11 || intel_dp_is_edp(intel_dp)) + return false; + + /* On Gen 11, FEC is Supported Only for DP SST modes. + * Let us start by enabling FEC for Compressed streams. + */ + if (pipe_config->dsc_params.compression_enable) + return true; + else + return false; + +} static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits) @@ -2129,6 +2146,11 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->dsc_params.compressed_bpp, pipe_config->dsc_params.slice_count); + /* For DP 1.4, Enable DSC if FEC can be configured */ + pipe_config->can_fec = intel_dp_can_fec(intel_dp, pipe_config); + if (!pipe_config->can_fec) + return false; + return true; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9a94c6544bf5..9dac242ead12 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -940,6 +940,9 @@ struct intel_crtc_state { u8 slice_count; } dsc_params; struct drm_dsc_config dp_dsc_cfg; + + /* Forward Error correction State */ + bool can_fec; }; struct intel_crtc { From patchwork Fri Oct 26 04:49:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8E0B14BD for ; Fri, 26 Oct 2018 04:55:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D89302C5B6 for ; Fri, 26 Oct 2018 04:55:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C9C872C6B3; Fri, 26 Oct 2018 04:55:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 752502C5B6 for ; Fri, 26 Oct 2018 04:55:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 134AE6E3F2; Fri, 26 Oct 2018 04:55:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6EF8B6E3F0 for ; Fri, 26 Oct 2018 04:55:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494126" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:40 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:41 -0700 Message-Id: <20181026044943.29334-6-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 5/7] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If the panel supports FEC, the driver has to set the FEC_READY bit in the dpcd register: FEC_CONFIGURATION. This has to happen before link training. v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready - change commit message. (Gaurav) v3: rebased. (r-b Manasi) v4: Use fec crtc state, before setting FEC_READY bit. (Anusha) Cc: Gaurav K Singh Cc: Jani Nikula Cc: Ville Syrjala Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_ddi.c | 1 + drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 1de0a3917d7f..efbada95dc4e 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2932,6 +2932,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_sink_set_decompression_state(intel_dp, crtc_state, DP_DECOMPRESSION_EN); + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); intel_dp_start_link_train(intel_dp); if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 4776ce6f2174..c446821c58b2 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3057,6 +3057,20 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, state == DP_DECOMPRESSION_EN ? "enable" : "disable"); } +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state) +{ + int ret; + + if (!crtc_state->can_fec) + return; + + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state); + if (ret < 0) + DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n"); +} + /* If the sink supports it, try to set the power state appropriately */ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9dac242ead12..a15ecdb4a706 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1796,6 +1796,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int state); +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + int state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder); From patchwork Fri Oct 26 04:49:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A80014BD for ; Fri, 26 Oct 2018 04:55:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 298802C5B6 for ; Fri, 26 Oct 2018 04:55:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1DDEF2C5C7; Fri, 26 Oct 2018 04:55:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B1B7B2C5B6 for ; Fri, 26 Oct 2018 04:55:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A02736E3F0; Fri, 26 Oct 2018 04:55:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2E5C6E3F0 for ; Fri, 26 Oct 2018 04:55:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494132" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:40 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:42 -0700 Message-Id: <20181026044943.29334-7-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 6/7] i915/dp/fec: Configure the Forward Error Correction bits. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If FEC is supported, the corresponding DP_TP_CTL register bits have to be configured. The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and wait till FEC_STATUS in DP_TP_CTL[28] is 1. Also add the warn message to make sure that the control register is already active while enabling FEC. v2: - Change commit message. Configure fec state after link training (Manasi, Gaurav) - Remove redundent checks (Manasi) - Remove the registers that get added automagically (Anusha) v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav) v4: rebased. v5: - Move the code to the proper spot, according to spec.(Ville) - Use fec state as a check too. Cc: Gaurav K Singh Cc: Jani Nikula Cc: Ville Syrjala Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ddi.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e85f53cb9cdd..8b1753939299 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9134,6 +9134,7 @@ enum skl_power_gate { #define _DP_TP_CTL_B 0x64140 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) #define DP_TP_CTL_ENABLE (1 << 31) +#define DP_TP_CTL_FEC_ENABLE (1 << 30) #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) @@ -9152,6 +9153,7 @@ enum skl_power_gate { #define _DP_TP_STATUS_A 0x64044 #define _DP_TP_STATUS_B 0x64144 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) #define DP_TP_STATUS_IDLE_DONE (1 << 25) #define DP_TP_STATUS_ACT_SENT (1 << 24) #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index efbada95dc4e..5badeaefb539 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2889,6 +2889,29 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } } +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + enum port port = intel_dig_port->base.port; + u32 val; + + /* FEC support exists for DP 1.4 only */ + if (!crtc_state->can_fec) + return; + + val = I915_READ(DP_TP_CTL(port)); + val |= DP_TP_CTL_FEC_ENABLE; + I915_WRITE(DP_TP_CTL(port), val); + + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port), + DP_TP_STATUS_FEC_ENABLE_LIVE, + DP_TP_STATUS_FEC_ENABLE_LIVE, + 1)) + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); +} + static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -2934,9 +2957,13 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, DP_DECOMPRESSION_EN); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); intel_dp_start_link_train(intel_dp); + if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); + /* Set FEC state after link training */ + intel_dp_enable_fec_state(intel_dp, crtc_state); + icl_enable_phy_clock_gating(dig_port); if (!is_mst) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a15ecdb4a706..405a44b3b3a8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1799,6 +1799,8 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int state); +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder); From patchwork Fri Oct 26 04:49:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656921 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDB2414DE for ; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC4622C5B6 for ; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE8BF2C5C7; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 783282C5B6 for ; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6A056E3FE; Fri, 26 Oct 2018 04:55:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8033A6E3F0 for ; Fri, 26 Oct 2018 04:55:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494135" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:41 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:43 -0700 Message-Id: <20181026044943.29334-8-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 7/7] drm/i915/fec: Disable FEC state. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Set the suitable bits in DP_TP_CTL to stop bit correction when DSC is disabled. v2: - rebased. - Add additional check for compression state. (Gaurav) v3: rebased. v4: - Move the code to the proper spot according to spec (Ville) - Use proper checks (manasi) Cc: Gaurav K Singh Cc: Jani Nikula Cc: Ville Syrjala Cc: Manasi Navare Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_ddi.c | 32 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 5badeaefb539..1e16c9aa0e65 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2912,6 +2912,31 @@ void intel_dp_enable_fec_state(struct intel_dp *intel_dp, DRM_ERROR("Timed out waiting for FEC Enable Status\n"); } +void intel_dp_disable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + enum port port = intel_dig_port->base.port; + u32 val; + u8 dsc_en_state; + + if (!crtc_state->can_fec) + return; + + if (!crtc_state->dsc_params.compression_enable) + return; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_DSC_ENABLE, &dsc_en_state); + + if (!dsc_en_state) { + val = I915_READ(DP_TP_CTL(port)); + val &= ~DP_TP_CTL_FEC_ENABLE; + I915_WRITE(DP_TP_CTL(port), val); + POSTING_READ(DP_TP_CTL(port)); + } +} + static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -3052,7 +3077,11 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, static void intel_disable_ddi_buf(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); + struct intel_dp *intel_dp = &dig_port->dp; + struct intel_crtc_state *crtc_state; enum port port = encoder->port; + bool wait = false; u32 val; @@ -3068,6 +3097,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder) val |= DP_TP_CTL_LINK_TRAIN_PAT1; I915_WRITE(DP_TP_CTL(port), val); + /* Disable FEC in DP Sink */ + intel_dp_disable_fec_state(intel_dp, crtc_state); + if (wait) intel_wait_ddi_buf_idle(dev_priv, port); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 405a44b3b3a8..a2f4562dabe2 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1801,6 +1801,8 @@ void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, int state); void intel_dp_enable_fec_state(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_dp_disable_fec_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); void intel_dp_encoder_reset(struct drm_encoder *encoder); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void intel_dp_encoder_destroy(struct drm_encoder *encoder);