From patchwork Sat Sep 19 15:28:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Rosato X-Patchwork-Id: 11787033 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1EF8D6CA for ; Sat, 19 Sep 2020 15:28:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03B1721741 for ; Sat, 19 Sep 2020 15:28:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="b6BjJfuL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726635AbgISP2x (ORCPT ); Sat, 19 Sep 2020 11:28:53 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:39920 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726590AbgISP2s (ORCPT ); Sat, 19 Sep 2020 11:28:48 -0400 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08JF2WE9189365; Sat, 19 Sep 2020 11:28:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=pp1; bh=Zlwp6w1I0aP10xjqqHZZM9lxlCxlhdIk2wX+FJwZSd0=; b=b6BjJfuLY5Gy3xmnfFV+a0+ZSB3DhZIQZmwi7FVfXtyqFxY7INFCegcy5WfQlSJxWwFP 0VSTcTB8VG47YrKjxm4yzXERedPaAjGG7WbBivLDNafzGM8gJgQgppRjtLHIEQ7zkCHN 0+ow9BYgQIb04SsFFS6tsxVqNgQF1oJswWCZA31SO5m8I88tLjrCMfL9k8Sh4osAmhYv M4zZtGnw2AWiuOwTKPk/TC/BkNbBod/zx49T1Xn52lj3MY79H8UP3V7OSroSdmyX7JXz 2kLshOBOZzM53yupsryAdWJF1qmWYwuM2Wbr5+ir23LT4KobKauSi8HNOzl3AneNtw46 TA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 33nkqdh0sm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 19 Sep 2020 11:28:47 -0400 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 08JF5YbG000606; Sat, 19 Sep 2020 11:28:47 -0400 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 33nkqdh0s9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 19 Sep 2020 11:28:47 -0400 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 08JFQYY6019127; Sat, 19 Sep 2020 15:28:46 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma02wdc.us.ibm.com with ESMTP id 33n9m8b6sa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 19 Sep 2020 15:28:46 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 08JFSdxn28705310 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 19 Sep 2020 15:28:39 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F6CDBE051; Sat, 19 Sep 2020 15:28:43 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA1D2BE04F; Sat, 19 Sep 2020 15:28:41 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.211.74.107]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 19 Sep 2020 15:28:41 +0000 (GMT) From: Matthew Rosato To: alex.williamson@redhat.com, cohuck@redhat.com, schnelle@linux.ibm.com Cc: pmorel@linux.ibm.com, borntraeger@de.ibm.com, hca@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, linux-s390@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] s390/pci: stash version in the zpci_dev Date: Sat, 19 Sep 2020 11:28:35 -0400 Message-Id: <1600529318-8996-2-git-send-email-mjrosato@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> References: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-19_05:2020-09-16,2020-09-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009190131 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In preparation for passing the info on to vfio-pci devices, stash the supported PCI version for the target device in the zpci_dev. Signed-off-by: Matthew Rosato Acked-by: Niklas Schnelle Acked-by: Christian Borntraeger Acked-by: Cornelia Huck --- arch/s390/include/asm/pci.h | 1 + arch/s390/pci/pci_clp.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index 99b92c3..882e233 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -179,6 +179,7 @@ struct zpci_dev { atomic64_t mapped_pages; atomic64_t unmapped_pages; + u8 version; enum pci_bus_speed max_bus_speed; struct dentry *debugfs_dev; diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c index 7e735f4..48bf316 100644 --- a/arch/s390/pci/pci_clp.c +++ b/arch/s390/pci/pci_clp.c @@ -102,6 +102,7 @@ static void clp_store_query_pci_fngrp(struct zpci_dev *zdev, zdev->msi_addr = response->msia; zdev->max_msi = response->noi; zdev->fmb_update = response->mui; + zdev->version = response->version; switch (response->version) { case 1: From patchwork Sat Sep 19 15:28:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Rosato X-Patchwork-Id: 11787031 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00D7E618 for ; Sat, 19 Sep 2020 15:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D47F021741 for ; Sat, 19 Sep 2020 15:28:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="owpktlq7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726613AbgISP2v (ORCPT ); Sat, 19 Sep 2020 11:28:51 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:3914 "EHLO mx0b-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726449AbgISP2u (ORCPT ); Sat, 19 Sep 2020 11:28:50 -0400 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08JF31Ro057420; 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Sat, 19 Sep 2020 15:28:43 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.211.74.107]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 19 Sep 2020 15:28:43 +0000 (GMT) From: Matthew Rosato To: alex.williamson@redhat.com, cohuck@redhat.com, schnelle@linux.ibm.com Cc: pmorel@linux.ibm.com, borntraeger@de.ibm.com, hca@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, linux-s390@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] s390/pci: track whether util_str is valid in the zpci_dev Date: Sat, 19 Sep 2020 11:28:36 -0400 Message-Id: <1600529318-8996-3-git-send-email-mjrosato@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> References: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-19_05:2020-09-16,2020-09-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 mlxlogscore=906 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009190131 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We'll need to keep track of whether or not the byte string in util_str is valid and thus needs to be passed to a vfio-pci passthrough device. Signed-off-by: Matthew Rosato Acked-by: Christian Borntraeger Acked-by: Niklas Schnelle --- arch/s390/include/asm/pci.h | 3 ++- arch/s390/pci/pci_clp.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index 882e233..32eb975 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -132,7 +132,8 @@ struct zpci_dev { u8 rid_available : 1; u8 has_hp_slot : 1; u8 is_physfn : 1; - u8 reserved : 5; + u8 util_avail : 1; + u8 reserved : 4; unsigned int devfn; /* DEVFN part of the RID*/ struct mutex lock; diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c index 48bf316..d011134 100644 --- a/arch/s390/pci/pci_clp.c +++ b/arch/s390/pci/pci_clp.c @@ -168,6 +168,7 @@ static int clp_store_query_pci_fn(struct zpci_dev *zdev, if (response->util_str_avail) { memcpy(zdev->util_str, response->util_str, sizeof(zdev->util_str)); + zdev->util_avail = 1; } zdev->mio_capable = response->mio_addr_avail; for (i = 0; i < PCI_STD_NUM_BARS; i++) { From patchwork Sat Sep 19 15:28:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Rosato X-Patchwork-Id: 11787035 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 554A9618 for ; Sat, 19 Sep 2020 15:29:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3649721741 for ; Sat, 19 Sep 2020 15:29:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="Lm2Kygss" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726626AbgISP2w (ORCPT ); Sat, 19 Sep 2020 11:28:52 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:48220 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726591AbgISP2v (ORCPT ); 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Sat, 19 Sep 2020 15:28:45 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 68E95BE053; Sat, 19 Sep 2020 15:28:44 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.211.74.107]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 19 Sep 2020 15:28:44 +0000 (GMT) From: Matthew Rosato To: alex.williamson@redhat.com, cohuck@redhat.com, schnelle@linux.ibm.com Cc: pmorel@linux.ibm.com, borntraeger@de.ibm.com, hca@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, linux-s390@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] vfio-pci/zdev: define the vfio_zdev header Date: Sat, 19 Sep 2020 11:28:37 -0400 Message-Id: <1600529318-8996-4-git-send-email-mjrosato@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> References: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-19_05:2020-09-16,2020-09-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009190126 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We define a new device region in vfio.h to be able to get the ZPCI CLP information by reading this region from userspace. We create a new file, vfio_zdev.h to define the structure of the new region defined in vfio.h Signed-off-by: Matthew Rosato --- include/uapi/linux/vfio.h | 5 ++ include/uapi/linux/vfio_zdev.h | 116 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 include/uapi/linux/vfio_zdev.h diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 9204705..65eb367 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -326,6 +326,11 @@ struct vfio_region_info_cap_type { * to do TLB invalidation on a GPU. */ #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) +/* + * IBM zPCI specific hardware feature information for a devcie. The contents + * of this region are mapped by struct vfio_region_zpci_info. + */ +#define VFIO_REGION_SUBTYPE_IBM_ZPCI_CLP (2) /* sub-types for VFIO_REGION_TYPE_GFX */ #define VFIO_REGION_SUBTYPE_GFX_EDID (1) diff --git a/include/uapi/linux/vfio_zdev.h b/include/uapi/linux/vfio_zdev.h new file mode 100644 index 0000000..c9e4891 --- /dev/null +++ b/include/uapi/linux/vfio_zdev.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Region definition for ZPCI devices + * + * Copyright IBM Corp. 2020 + * + * Author(s): Pierre Morel + * Matthew Rosato + */ + +#ifndef _VFIO_ZDEV_H_ +#define _VFIO_ZDEV_H_ + +#include + +/** + * struct vfio_region_zpci_info - ZPCI information + * + * This region provides zPCI specific hardware feature information for a + * device. + * + * The ZPCI information structure is presented as a chain of CLP features + * defined below. argsz provides the size of the entire region, and offset + * provides the location of the first CLP feature in the chain. + * + */ +struct vfio_region_zpci_info { + __u32 argsz; /* Size of entire payload */ + __u32 offset; /* Location of first entry */ +} __packed; + +/** + * struct vfio_region_zpci_info_hdr - ZPCI header information + * + * This structure is included at the top of each CLP feature to define what + * type of CLP feature is presented / the structure version. The next value + * defines the offset of the next CLP feature, and is an offset from the very + * beginning of the region (vfio_region_zpci_info). + * + * Each CLP feature must have it's own unique 'id'. + */ +struct vfio_region_zpci_info_hdr { + __u16 id; /* Identifies the CLP type */ + __u16 version; /* version of the CLP data */ + __u32 next; /* Offset of next entry */ +} __packed; + +/** + * struct vfio_region_zpci_info_qpci - Initial Query PCI information + * + * This region provides an initial set of data from the Query PCI Function + * CLP. + */ +#define VFIO_REGION_ZPCI_INFO_QPCI 1 + +struct vfio_region_zpci_info_qpci { + struct vfio_region_zpci_info_hdr hdr; + __u64 start_dma; /* Start of available DMA addresses */ + __u64 end_dma; /* End of available DMA addresses */ + __u16 pchid; /* Physical Channel ID */ + __u16 vfn; /* Virtual function number */ + __u16 fmb_length; /* Measurement Block Length (in bytes) */ + __u8 pft; /* PCI Function Type */ + __u8 gid; /* PCI function group ID */ +} __packed; + + +/** + * struct vfio_region_zpci_info_qpcifg - Initial Query PCI Function Group info + * + * This region provides an initial set of data from the Query PCI Function + * Group CLP. + */ +#define VFIO_REGION_ZPCI_INFO_QPCIFG 2 + +struct vfio_region_zpci_info_qpcifg { + struct vfio_region_zpci_info_hdr hdr; + __u64 dasm; /* DMA Address space mask */ + __u64 msi_addr; /* MSI address */ + __u64 flags; +#define VFIO_PCI_ZDEV_FLAGS_REFRESH 1 /* Use program-specified TLB refresh */ + __u16 mui; /* Measurement Block Update Interval */ + __u16 noi; /* Maximum number of MSIs */ + __u16 maxstbl; /* Maximum Store Block Length */ + __u8 version; /* Supported PCI Version */ +} __packed; + +/** + * struct vfio_region_zpci_info_util - Utility String + * + * This region provides the utility string for the associated device, which is + * a device identifier string. + */ +#define VFIO_REGION_ZPCI_INFO_UTIL 3 + +struct vfio_region_zpci_info_util { + struct vfio_region_zpci_info_hdr hdr; + __u32 size; + __u8 util_str[]; +} __packed; + +/** + * struct vfio_region_zpci_info_pfip - PCI Function Path + * + * This region provides the PCI function path string, which is an identifier + * that describes the internal hardware path of the device. + */ +#define VFIO_REGION_ZPCI_INFO_PFIP 4 + +struct vfio_region_zpci_info_pfip { +struct vfio_region_zpci_info_hdr hdr; + __u32 size; + __u8 pfip[]; +} __packed; + +#endif From patchwork Sat Sep 19 15:28:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Rosato X-Patchwork-Id: 11787037 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5254618 for ; Sat, 19 Sep 2020 15:29:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D09621D43 for ; Sat, 19 Sep 2020 15:29:05 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 19 Sep 2020 15:28:46 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BD59DBE054; Sat, 19 Sep 2020 15:28:46 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A9015BE04F; Sat, 19 Sep 2020 15:28:45 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.211.74.107]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 19 Sep 2020 15:28:45 +0000 (GMT) From: Matthew Rosato To: alex.williamson@redhat.com, cohuck@redhat.com, schnelle@linux.ibm.com Cc: pmorel@linux.ibm.com, borntraeger@de.ibm.com, hca@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, linux-s390@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] vfio-pci/zdev: use a device region to retrieve zPCI information Date: Sat, 19 Sep 2020 11:28:38 -0400 Message-Id: <1600529318-8996-5-git-send-email-mjrosato@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> References: <1600529318-8996-1-git-send-email-mjrosato@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-19_05:2020-09-16,2020-09-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009190126 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define a new configuration entry VFIO_PCI_ZDEV for VFIO/PCI. When this s390-only feature is configured we initialize a new device region, VFIO_REGION_SUBTYPE_IBM_ZPCI_CLP, to hold information provided by the underlying hardware. This patch is based on work previously done by Pierre Morel. Signed-off-by: Matthew Rosato --- drivers/vfio/pci/Kconfig | 13 ++ drivers/vfio/pci/Makefile | 1 + drivers/vfio/pci/vfio_pci.c | 8 ++ drivers/vfio/pci/vfio_pci_private.h | 10 ++ drivers/vfio/pci/vfio_pci_zdev.c | 242 ++++++++++++++++++++++++++++++++++++ 5 files changed, 274 insertions(+) create mode 100644 drivers/vfio/pci/vfio_pci_zdev.c diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index ac3c1dd..07b4a35 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -45,3 +45,16 @@ config VFIO_PCI_NVLINK2 depends on VFIO_PCI && PPC_POWERNV help VFIO PCI support for P9 Witherspoon machine with NVIDIA V100 GPUs + +config VFIO_PCI_ZDEV + bool "VFIO PCI ZPCI device CLP support" + depends on VFIO_PCI && S390 + default y + help + Enabling this options exposes a region containing hardware + configuration for zPCI devices. This enables userspace (e.g. QEMU) + to supply proper configuration values instead of hard-coded defaults + for zPCI devices passed through via VFIO on s390. + + Say Y here. + diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile index f027f8a..781e080 100644 --- a/drivers/vfio/pci/Makefile +++ b/drivers/vfio/pci/Makefile @@ -3,5 +3,6 @@ vfio-pci-y := vfio_pci.o vfio_pci_intrs.o vfio_pci_rdwr.o vfio_pci_config.o vfio-pci-$(CONFIG_VFIO_PCI_IGD) += vfio_pci_igd.o vfio-pci-$(CONFIG_VFIO_PCI_NVLINK2) += vfio_pci_nvlink2.o +vfio-pci-$(CONFIG_VFIO_PCI_ZDEV) += vfio_pci_zdev.o obj-$(CONFIG_VFIO_PCI) += vfio-pci.o diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index 1ab1f5c..cfb04d9 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -409,6 +409,14 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev) } } + if (IS_ENABLED(CONFIG_VFIO_PCI_ZDEV)) { + ret = vfio_pci_zdev_init(vdev); + if (ret && ret != -ENODEV) { + pci_warn(pdev, "Failed to setup zPCI CLP region\n"); + goto disable_exit; + } + } + vfio_pci_probe_mmaps(vdev); return 0; diff --git a/drivers/vfio/pci/vfio_pci_private.h b/drivers/vfio/pci/vfio_pci_private.h index 61ca8ab..729af20 100644 --- a/drivers/vfio/pci/vfio_pci_private.h +++ b/drivers/vfio/pci/vfio_pci_private.h @@ -213,4 +213,14 @@ static inline int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev) return -ENODEV; } #endif + +#ifdef CONFIG_VFIO_PCI_ZDEV +extern int vfio_pci_zdev_init(struct vfio_pci_device *vdev); +#else +static inline int vfio_pci_zdev_init(struct vfio_pci_device *vdev) +{ + return -ENODEV; +} +#endif + #endif /* VFIO_PCI_PRIVATE_H */ diff --git a/drivers/vfio/pci/vfio_pci_zdev.c b/drivers/vfio/pci/vfio_pci_zdev.c new file mode 100644 index 0000000..9c7d659 --- /dev/null +++ b/drivers/vfio/pci/vfio_pci_zdev.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * VFIO ZPCI devices support + * + * Copyright (C) IBM Corp. 2020. All rights reserved. + * Author(s): Pierre Morel + * Matthew Rosato + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include "vfio_pci_private.h" + +static size_t vfio_pci_zdev_rw(struct vfio_pci_device *vdev, + char __user *buf, size_t count, loff_t *ppos, + bool iswrite) +{ + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS; + struct vfio_region_zpci_info *region = vdev->region[i].data; + loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; + + if ((!vdev->pdev->bus) || (!to_zpci(vdev->pdev))) + return -ENODEV; + + if (pos >= vdev->region[i].size || iswrite) + return -EINVAL; + + count = min(count, (size_t)(vdev->region[i].size - pos)); + if (copy_to_user(buf, region + pos, count)) + return -EFAULT; + + return count; +} + +static void vfio_pci_zdev_release(struct vfio_pci_device *vdev, + struct vfio_pci_region *region) +{ + kfree(region->data); +} + +static const struct vfio_pci_regops vfio_pci_zdev_regops = { + .rw = vfio_pci_zdev_rw, + .release = vfio_pci_zdev_release, +}; + +static void vfio_pci_zdev_fill_hdr(struct vfio_region_zpci_info_hdr *hdr, + __u16 id, __u16 version, size_t offset, + size_t size) +{ + hdr->id = id; + hdr->version = version; + hdr->next = offset + size; +} + +/* + * Add the Query PCI Function information to the device region. + * + * zdev - the zPCI device to get information from + * region - start of the vfio device region + * offset - location within region to place the data + * + * On return, provide the offset of the end of this CLP feature. + */ +static size_t vfio_pci_zdev_add_qpci(struct zpci_dev *zdev, void *region, + size_t offset) +{ + struct vfio_region_zpci_info_qpci *clp; + + /* Jump to the CLP region via the offset */ + clp = (struct vfio_region_zpci_info_qpci *) (region + offset); + + /* Fill in the clp header */ + vfio_pci_zdev_fill_hdr(&clp->hdr, VFIO_REGION_ZPCI_INFO_QPCI, 1, + offset, sizeof(*clp)); + + /* Fill in the CLP feature info */ + clp->start_dma = zdev->start_dma; + clp->end_dma = zdev->end_dma; + clp->pchid = zdev->pchid; + clp->vfn = zdev->vfn; + clp->fmb_length = zdev->fmb_length; + clp->pft = zdev->pft; + clp->gid = zdev->pfgid; + + /* Return offset to the end of this CLP feature */ + return clp->hdr.next; +} + +/* + * Add the Query PCI Function Group information to the device region. + * + * zdev - the zPCI device to get information from + * region - start of the vfio device region + * offset - location within region to place the data + * + * On return, provide the offset of the end of this CLP feature. + */ +static size_t vfio_pci_zdev_add_qpcifg(struct zpci_dev *zdev, void *region, + size_t offset) +{ + struct vfio_region_zpci_info_qpcifg *clp; + + /* Jump to the CLP region via the offset */ + clp = (struct vfio_region_zpci_info_qpcifg *) (region + offset); + + /* Fill in the clp header */ + vfio_pci_zdev_fill_hdr(&clp->hdr, VFIO_REGION_ZPCI_INFO_QPCIFG, 1, + offset, sizeof(*clp)); + + /* Fill in the CLP feature info */ + clp->dasm = zdev->dma_mask; + clp->msi_addr = zdev->msi_addr; + clp->flags = VFIO_PCI_ZDEV_FLAGS_REFRESH; + clp->mui = zdev->fmb_update; + clp->noi = zdev->max_msi; + clp->maxstbl = ZPCI_MAX_WRITE_SIZE; + clp->version = zdev->version; + + /* Return offset to the end of this CLP feature */ + return clp->hdr.next; +} + +/* + * Add the device utility string to the device region. + * + * zdev - the zPCI device to get information from + * region - start of the vfio device region + * offset - location within region to place the data + * + * On return, provide the offset of the end of this CLP feature. + */ +static size_t vfio_pci_zdev_add_util(struct zpci_dev *zdev, void *region, + size_t offset) +{ + struct vfio_region_zpci_info_util *clp; + size_t size = CLP_UTIL_STR_LEN; + + /* Only add a utility string if one is available */ + if (!zdev->util_avail) + return offset; + + /* Jump to the CLP region via the offset */ + clp = (struct vfio_region_zpci_info_util *) (region + offset); + + /* Fill in the clp header */ + vfio_pci_zdev_fill_hdr(&clp->hdr, VFIO_REGION_ZPCI_INFO_UTIL, 1, + offset, sizeof(*clp) + size); + + /* Fill in the CLP feature info */ + clp->size = size; + memcpy(clp->util_str, zdev->util_str, size); + + /* Return offset to the end of this CLP feature */ + return clp->hdr.next; +} + +/* + * Add the function path string to the device region. + * + * zdev - the zPCI device to get information from + * region - start of the vfio device region + * offset - location within region to place the data + * + * On return, provide the offset of the end of this CLP feature. + */ +static size_t vfio_pci_zdev_add_pfip(struct zpci_dev *zdev, void *region, + size_t offset) +{ + struct vfio_region_zpci_info_pfip *clp; + size_t size = CLP_PFIP_NR_SEGMENTS; + + /* Jump to the CLP region via the offset */ + clp = (struct vfio_region_zpci_info_pfip *) (region + offset); + + /* Fill in the clp header */ + vfio_pci_zdev_fill_hdr(&clp->hdr, VFIO_REGION_ZPCI_INFO_PFIP, 1, + offset, sizeof(*clp) + size); + + /* Fill in the CLP feature info */ + clp->size = size; + memcpy(clp->pfip, zdev->pfip, size); + + /* Return offset to the end of this CLP feature */ + return clp->hdr.next; +} + +int vfio_pci_zdev_init(struct vfio_pci_device *vdev) +{ + struct vfio_region_zpci_info *region; + struct zpci_dev *zdev; + size_t clp_offset; + int size; + int ret; + + if (!vdev->pdev->bus) + return -ENODEV; + + zdev = to_zpci(vdev->pdev); + if (!zdev) + return -ENODEV; + + /* Calculate size needed for all supported CLP features */ + size = sizeof(*region) + + sizeof(struct vfio_region_zpci_info_qpci) + + sizeof(struct vfio_region_zpci_info_qpcifg) + + (sizeof(struct vfio_region_zpci_info_util) + CLP_UTIL_STR_LEN) + + (sizeof(struct vfio_region_zpci_info_pfip) + + CLP_PFIP_NR_SEGMENTS); + + region = kmalloc(size, GFP_KERNEL); + if (!region) + return -ENOMEM; + + /* Fill in header */ + region->argsz = size; + clp_offset = region->offset = sizeof(struct vfio_region_zpci_info); + + /* Fill the supported CLP features */ + clp_offset = vfio_pci_zdev_add_qpci(zdev, region, clp_offset); + clp_offset = vfio_pci_zdev_add_qpcifg(zdev, region, clp_offset); + clp_offset = vfio_pci_zdev_add_util(zdev, region, clp_offset); + clp_offset = vfio_pci_zdev_add_pfip(zdev, region, clp_offset); + + ret = vfio_pci_register_dev_region(vdev, + PCI_VENDOR_ID_IBM | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, + VFIO_REGION_SUBTYPE_IBM_ZPCI_CLP, &vfio_pci_zdev_regops, + size, VFIO_REGION_INFO_FLAG_READ, region); + if (ret) + kfree(region); + + return ret; +}