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Thu, 25 Oct 2018 16:22:02 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH v4 1/2] drm/exynos: decon: Make plane alpha configurable Date: Thu, 25 Oct 2018 18:21:52 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540484513-24274-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTUQDm7D52Hc1uU/CgZbjKUsosjA4lPTDoFhH1p9conXnTyk3ZTc0S lAWpM99gassXaqKZOd8zBW20zMdSw3JmKSvxkeW7ByU5r9a/78l3zuFQmKSLcKSuKm+wKqU8 WEqK8NoXP007yia7ZZ49Bg9kftJFoMSuNgGqzKwgkLGxCKA3899I1DCkF6K0jyk4Gv3QjaNk ywSGTKanQtSp/iJEOksfgXr1WhJlmpoFKLm+hUDlhkEhyp+uwdFgugGgzPQx8pAd8zjnMWB0 pfEkU7cwRDA5baeZjwlGAVNVGM00pDUJGKPeLGSSqksBM6tzPiW6IPIOYIOvhrOqnQf8REHG hzoyNGHzzdz+CiIGqJ01wIaCtBcsmIwjNUBESegSABdNapwncwC+KteskFkAX8R8JVcrUxOF GG88ArB//ongX2U06yVhTZH0HjgwOLPcsKc3wT+ppcAawuheApoK8nGrYUcz8M1C7lKBonB6 C3w+tIZfcIb9XfGYFdvQx+D0dJWQ1yeFcMwisGIxHQ6HZ2YwXj8Cy011Kxk7OG6sXsHrYXv6 veUrQPoOgOa5PoInKQC2lGlwPrUf6t6NC6yHwGg3WKHfycuHYVGxZVmGtC18N7nOKmNLMK32 PsbLYhh3V8KnXeFEdTW5Ojs6Ow/4CAM1Hdv559EC+FmrxlLAxuz/W3kAlAIHNoxTBLLcbiUb 4cHJFVyYMtDjcohCB5Z+Wfuica4e6H/7twKaAtI14pdPX8skhDyci1S0AkhhUntx00C3TCIO kEfeYlUhvqqwYJZrBU4ULnUQF+dUyiR0oPwGe51lQ1nVqiugbBxjwFlzz9qsiy4RvlEBih7b T5B0rflwsjF1xBVPfLA1Q6a99929w01sSI498977OBf/diqs5LzYc++Jztt15ivhLpZtP1yz xx74y/ySkp9d61dHhThleZ3rs5ny8TyozMuTZhTlem3zaLjU3KdUa8dHVEcNsT4bmZ40v1/D G9K7o933SXEuSL7LHVNx8r8p7gd2YQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsVy+t/xu7qr3l6MNvhwzMri1rpzrBa9504y WWycsZ7V4vjupYwWV76+Z7PY+WAXu8Wk+xNYLF7cu8hi0f/4NbPF+fMb2C3ONr1ht9j0+Bqr xeVdc9gsZpzfx2TRv+Mgq8XaI3fZLRZ+3MpicXfyEUaLGZNfsjkIe6yZt4bRY9OqTjaP7d8e sHrMOxnocb/7OJPH5iX1Hjsn7WXyOL7rFrtH35ZVjB6fN8kFcEXp2RTll5akKmTkF5fYKkUb WhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXoZRyfu4mtoFulYv7N9awNjE1yXYyc HBICJhIfXi9h7mLk4hASWMooceLXBFaIhIzEvLN9bBC2sMSfa11sEEWfGCU+Hm5gAUmwCZhK 3L77CaxIREBZ4u/EVYwgRcwCD1kl3i/sBEsIC3hIXPk2H2gqBweLgKrE4Qc8IGFeoPD+yR1Q C+Qkbp7rZAaxOQU8JT5+3MwOUi4EVHPhhu8ERr4FjAyrGEVSS4tz03OLjfSKE3OLS/PS9ZLz czcxAiNr27GfW3Ywdr0LPsQowMGoxMN7YsOFaCHWxLLiytxDjBIczEoivHtvX4wW4k1JrKxK LcqPLyrNSS0+xGgKdNJEZinR5Hxg1OeVxBuaGppbWBqaG5sbm1koifOeN6iMEhJITyxJzU5N LUgtgulj4uCUamDcxxQk/cLljYvNz6RNvw1qFRgZ/Eve3OvTr3p+aV6wa0kJ7y0ZCePa2NU7 a4MTml60RFsqh1bfX9Z8QzX0nmjeqZnzv6a+ubT34hSDjNIkOc5srTluHGePPC0/+CH+26U/ HvNms2YF2/rdLtT47LVaWMa/oFXrE6dT5pFl3NObru1dLLn+8X8lluKMREMt5qLiRADtV96r wgIAAA== Message-Id: <20181025162203eucas1p1cd2df1e4ee3d44b0dce0ac445a48dfe0~g5oMYhkK-1757217572eucas1p1Z@eucas1p1.samsung.com> X-CMS-MailID: 20181025162203eucas1p1cd2df1e4ee3d44b0dce0ac445a48dfe0 X-Msg-Generator: CA X-RootMTR: 20181025162203eucas1p1cd2df1e4ee3d44b0dce0ac445a48dfe0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181025162203eucas1p1cd2df1e4ee3d44b0dce0ac445a48dfe0 References: <1540484513-24274-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Fri, 26 Oct 2018 07:46:32 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , Lowry Li , Sean Paul , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The decon hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TM2 with Exynos 5433 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski --- v2 changes: - remove window blend property for the first (0) layer (currently zpos is immutable), - remove unused parameter in decon_win_set_bldmod, - move local variables to decon_win_set_pixfmt, - add alpha parameter in decon_win_set_bldmod, - don't call decon_win_set_bldmod for the first (0) layer, - move decon_win_set_bldmod call to bottom of decon_win_set_pixfmt, drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 33 +++++++++++++++++++++++++++ drivers/gpu/drm/exynos/regs-decon5433.h | 7 ++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 94529aa82339..2578db16750d 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -84,6 +84,14 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, }; +static const unsigned int capabilities[WINDOWS_NR] = { + 0, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, u32 val) { @@ -259,9 +267,30 @@ static void decon_commit(struct exynos_drm_crtc *crtc) decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } + +static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, + unsigned int alpha) +{ + u32 win_alpha = alpha >> 8; + u32 val = 0; + + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | + VIDOSD_Wx_ALPHA_G_F(win_alpha) | + VIDOSD_Wx_ALPHA_B_F(win_alpha); + decon_set_bits(ctx, DECON_VIDOSDxC(win), + VIDOSDxC_ALPHA0_RGB_MASK, val); + decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); + } +} + static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, struct drm_framebuffer *fb) { + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + unsigned int alpha = state->base.alpha; unsigned long val; val = readl(ctx->addr + DECON_WINCONx(win)); @@ -288,6 +317,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val |= WINCONx_BPPMODE_32BPP_A8888; val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCONx_ALPHA_MUL_F; break; } @@ -307,6 +337,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, } writel(val, ctx->addr + DECON_WINCONx(win)); + if (win > 0) + decon_win_set_bldmod(ctx, win, alpha); } static void decon_shadow_protect(struct decon_context *ctx, bool protect) @@ -561,6 +593,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); ctx->configs[win].zpos = win - ctx->first_win; ctx->configs[win].type = decon_win_types[win]; + ctx->configs[win].capabilities = capabilities[win]; ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, &ctx->configs[win]); diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index 19ad9e47945e..72648bda3142 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -104,6 +104,7 @@ #define WINCONx_BURSTLEN_16WORD (0x0 << 10) #define WINCONx_BURSTLEN_8WORD (0x1 << 10) #define WINCONx_BURSTLEN_4WORD (0x2 << 10) +#define WINCONx_ALPHA_MUL_F (1 << 7) #define WINCONx_BLD_PIX_F (1 << 6) #define WINCONx_BPPMODE_MASK (0xf << 2) #define WINCONx_BPPMODE_16BPP_565 (0x5 << 2) @@ -121,6 +122,9 @@ #define SHADOWCON_PROTECT_MASK GENMASK(14, 10) #define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n))) +/* VIDOSDxC */ +#define VIDOSDxC_ALPHA0_RGB_MASK (0xffffff) + /* VIDOSDxD */ #define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16) #define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8) @@ -206,4 +210,7 @@ #define CRCCTRL_CRCEN (0x1 << 0) #define CRCCTRL_MASK (0x7) +/* BLENDCON */ +#define BLEND_NEW (1 << 0) + #endif /* EXYNOS_REGS_DECON5433_H */ From patchwork Thu Oct 25 16:21:53 2018 Content-Type: text/plain; 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Thu, 25 Oct 2018 16:22:03 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH v4 2/2] drm/exynos: decon: Make pixel blend mode configurable Date: Thu, 25 Oct 2018 18:21:53 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540484513-24274-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSd0xTURTGc/smjTXPguEGnDUYbQQ1qLlx4oqPOFBJJEgcFV6ACBVbwT0x hiGWISkaUsGAYtmlgFRFC2hx0IJFrRDQOBIECVYsSmKNPJ7jv9/9zvnOd8/NpTGplfChY5WH OJVSEScjxXjdo1Grf/lgR8SCs3YadVVYCZRhfSxC1XmVBLLcKQao0zVEooa3Jgplv8nEUV9v B4407wcwZLNVUajt3GcKGd6/JJDdlE+iPFujCGlumwlU3tJDoUJnLY56cloAysv5RAZ5smW6 MsAa9KkkWz/ylmB1j7exb9ItIram6DTbkH1PxFpMXRR7yagH7LBh2lbxTvHyKC4uNolTzV+5 VxyTc+UClVDtf0TndpNnwC+/NOBBQ2YRbHOMUDxLmRIAe81T04B4jL8B6P7RiQuFYQAv/6DT AD1uSLmmEnpuAphZ7MD+GQae1wLeQDKLYXfPV5JnL2YWdGfpAd+EMXYC2q4Xjk/1ZELgeVMR wTPO+MEvpRpcuNI0+NqaivHswQRDp7OG4s2QcVJQa28enyphkqAx9z4lGNbBK/1DpMCesN9i /KNPgU9zLuKCORnArm8vCeGQCaC5NO1P3DJocPSL+OUwZi6sNM0X5NVQeyuPFHaeCB2Dk3gZ G8PsOi0myBKYckEqdM+GA0Yj+Te2b9gFBGZhVkU5LrxQPoAfaluJTDD96v+wAgD0wJtLVMdH c+pAJXc4QK2IVycqowMiD8QbwNgve/rL4roNGn/uawIMDWQTJK1V7RFSQpGkPhrfBCCNybwk 97o7IqSSKMXRY5zqwB5VYhynbgK+NC7zltzQVUdImWjFIW4/xyVwqr9VEe3hcwYEPcE0gWtj fj5sODiSuqGqN9xatf7kEjvKT17z6EQGDH7XMHPC8dYC+doZU0pWSR64Ip/5mnOrdfV9e3es dBxOR4Nh2t1Gp3YRu+K7Zsn2WE2AYsg/fEtQojyj/0QuZOV9Hze/mJccEtocGqbc5XfXb9PS 7DbtxvbiOa+iJp8aHb0sw9UxioVyTKVW/AaFTbDEYQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsVy+t/xu7pr3l6MNlh7h8Xi1rpzrBa9504y WWycsZ7V4vjupYwWV76+Z7PY+WAXu8Wk+xNYLF7cu8hi0f/4NbPF+fMb2C3ONr1ht9j0+Bqr xeVdc9gsZpzfx2TRv+Mgq8XaI3fZLRZ+3MpicXfyEUaLGZNfsjkIe6yZt4bRY9OqTjaP7d8e sHrMOxnocb/7OJPH5iX1Hjsn7WXyOL7rFrtH35ZVjB6fN8kFcEXp2RTll5akKmTkF5fYKkUb WhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXoZUye2cZesFG3Yt7fv2wNjP9Uuxg5 OCQETCQ65hd1MXJxCAksZZSYcWwPaxcjJ1BcRmLe2T42CFtY4s+1LjaIok+MEqsW3WcHSbAJ mErcvvsJrEhEQFni78RVjCBFzAIPWSXeL+wESwgL+Eo82boDbCqLgKrEh9X9LCA2r4CHxJXu PSwQG+Qkbp7rZAaxOQU8JT5+3MwOcp0QUM2FG74TGPkWMDKsYhRJLS3OTc8tNtIrTswtLs1L 10vOz93ECIysbcd+btnB2PUu+BCjAAejEg/viQ0XooVYE8uKK3MPMUpwMCuJ8O69fTFaiDcl sbIqtSg/vqg0J7X4EKMp0E0TmaVEk/OBUZ9XEm9oamhuYWlobmxubGahJM573qAySkggPbEk NTs1tSC1CKaPiYNTqoHxiFbX2fZ3XvaXe/TSM48uLNy9dJVFweuHzrGqNStiFwnWzPcru/XN QydbY7vppDezr3gaxMefMC7r/3StWUO7/vmfjatl49/xTe72fyKq9fuv+yP+I/c1NpZN6uwy LQniEeqcvTt6YVMku0JOt8yOgA+OynrHJYPyDDae/H9rlbf6ZI7mC5OVWIozEg21mIuKEwHa 62wrwgIAAA== Message-Id: <20181025162204eucas1p1e53a6081e5251ba3419c0a996ff055cc~g5oNlZp252803828038eucas1p1h@eucas1p1.samsung.com> X-CMS-MailID: 20181025162204eucas1p1e53a6081e5251ba3419c0a996ff055cc X-Msg-Generator: CA X-RootMTR: 20181025162204eucas1p1e53a6081e5251ba3419c0a996ff055cc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181025162204eucas1p1e53a6081e5251ba3419c0a996ff055cc References: <1540484513-24274-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Fri, 26 Oct 2018 07:46:32 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , Lowry Li , Sean Paul , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The decon hardware supports different blend modes. Add pixel blend mode property and make it configurable, by modifying the blend equation. Tested on TM2 with Exynos 5433 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski --- v4 changes: - set blend equation for DRM_MODE_BLEND_PIXEL_NONE explicitly, v3 changes: - fix compilation errors (previouslsy wrong patch was sent), v2 changes: - add premultiplied mode by setting blending equation accordingly, - remove no longer used blend mode settings from decon_win_set_pixfmt, drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 65 ++++++++++++++++++++++----- drivers/gpu/drm/exynos/regs-decon5433.h | 15 +++++++ 2 files changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 2578db16750d..68a42079679c 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -86,10 +86,10 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { static const unsigned int capabilities[WINDOWS_NR] = { 0, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }; static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, @@ -267,13 +267,51 @@ static void decon_commit(struct exynos_drm_crtc *crtc) decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } +static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win, + unsigned int alpha, unsigned int pixel_alpha) +{ + u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf); + u32 val = 0; + + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + case DRM_MODE_BLEND_COVERAGE: + val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A); + val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); + break; + case DRM_MODE_BLEND_PREMULTI: + default: + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0); + val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); + } else { + val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE); + val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); + } + break; + } + decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); +} static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, - unsigned int alpha) + unsigned int alpha, unsigned int pixel_alpha) { u32 win_alpha = alpha >> 8; u32 val = 0; + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + case DRM_MODE_BLEND_PREMULTI: + default: + val |= WINCONx_ALPHA_SEL_F; + val |= WINCONx_BLD_PIX_F; + val |= WINCONx_ALPHA_MUL_F; + break; + } + decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | VIDOSD_Wx_ALPHA_G_F(win_alpha) | @@ -291,8 +329,14 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, struct exynos_drm_plane_state *state = to_exynos_plane_state(plane.base.state); unsigned int alpha = state->base.alpha; + unsigned int pixel_alpha; unsigned long val; + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; + val = readl(ctx->addr + DECON_WINCONx(win)); val &= WINCONx_ENWIN_F; @@ -315,9 +359,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, case DRM_FORMAT_ARGB8888: default: val |= WINCONx_BPPMODE_32BPP_A8888; - val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; + val |= WINCONx_WSWP_F; val |= WINCONx_BURSTLEN_16WORD; - val |= WINCONx_ALPHA_MUL_F; break; } @@ -335,10 +378,12 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, val &= ~WINCONx_BURSTLEN_MASK; val |= WINCONx_BURSTLEN_8WORD; } + decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); - writel(val, ctx->addr + DECON_WINCONx(win)); - if (win > 0) - decon_win_set_bldmod(ctx, win, alpha); + if (win > 0) { + decon_win_set_bldmod(ctx, win, alpha, pixel_alpha); + decon_win_set_bldeq(ctx, win, alpha, pixel_alpha); + } } static void decon_shadow_protect(struct decon_context *ctx, bool protect) diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h index 72648bda3142..63db6974bf14 100644 --- a/drivers/gpu/drm/exynos/regs-decon5433.h +++ b/drivers/gpu/drm/exynos/regs-decon5433.h @@ -117,6 +117,7 @@ #define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2) #define WINCONx_ALPHA_SEL_F (1 << 1) #define WINCONx_ENWIN_F (1 << 0) +#define WINCONx_BLEND_MODE_MASK (0xc2) /* SHADOWCON */ #define SHADOWCON_PROTECT_MASK GENMASK(14, 10) @@ -213,4 +214,18 @@ /* BLENDCON */ #define BLEND_NEW (1 << 0) +/* BLENDERQx */ +#define BLENDERQ_ZERO 0x0 +#define BLENDERQ_ONE 0x1 +#define BLENDERQ_ALPHA_A 0x2 +#define BLENDERQ_ONE_MINUS_ALPHA_A 0x3 +#define BLENDERQ_ALPHA0 0x6 +#define BLENDERQ_Q_FUNC_F(n) (n << 18) +#define BLENDERQ_P_FUNC_F(n) (n << 12) +#define BLENDERQ_B_FUNC_F(n) (n << 6) +#define BLENDERQ_A_FUNC_F(n) (n << 0) + +/* BLENDCON */ +#define BLEND_NEW (1 << 0) + #endif /* EXYNOS_REGS_DECON5433_H */