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Thu, 25 Oct 2018 15:24:10 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 1/2] drm/exynos: fimd: Make plane alpha configurable Date: Thu, 25 Oct 2018 17:23:49 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540481030-15019-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOKsWRmVeSWpSXmKPExsWy7djPc7oyDy5GG8x4LWpxa905VovecyeZ LDbOWM9qcXz3UkaLK1/fs1lMuj+BxeLFvYssFv2PXzNbnD+/gd3ibNMbdotNj6+xWlzeNYfN Ysb5fUwWa4/cZbeYMfklmwO/x6ZVnWwe2789YPW4332cyWPzknqPvi2rGD0+b5ILYIvisklJ zcksSy3St0vgyvjV8paxYIdGxbNXOxgbGJcpdjFyckgImEh8OPWcGcQWEljBKPHmTRGE/YVR 4txD1i5GLiD7M6PEsffz2WEarvVvY4RILGeU2PJ4NhuEA9TxcPlMsFFsAqYSt+9+YgOxRQSU Jf5OXAXWwSywlUVi78kbTCAJYQF3ieWb/4E1sAioSky+2s8KsUJO4ua5TqA4BwengKfEgZv6 IL0SAtvYJWbsbgIbyitQJtH7dhIzRL2LROeGZ1DnCUu8Or4FypaR+L9zPhNEczOjxK0v11gh nAmMEgdXd7FAVFlLbLrxiglkG7OApsT6XfoQYUeJls/zWEHCEgJ8EjfeCoKEmYHMSdumM0OE eSU62oQgqtUkXm/Zwgaz9sXnr4wQtodE46NlzJAAmgMM0vcz2Scwys9CWLaAkXEVo3hqaXFu emqxcV5quV5xYm5xaV66XnJ+7iZGYPI5/e/41x2M+/4kHWIU4GBU4uE9seFCtBBrYllxZe4h RgkOZiUR3r23L0YL8aYkVlalFuXHF5XmpBYfYpTmYFES5102b2O0kEB6YklqdmpqQWoRTJaJ g1OqgTHYJ0rN9u7WR9ebZj78qc09vbDy02x+eckbySaXlmYs+bOKc6VvjdrsL+cfJhWss9vC 7+u1U2hRzLQ5khmK67+WvBc9/s20cWPWgk+1/zc7sDQV8fmkxv3suc60iO3zx3eFHKlnPL4z 7zRbIzdpVdDxBP3CSOWNCxbbPuyXFwhaIns2wrMkeo4SS3FGoqEWc1FxIgDkE1Z0OgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42I5/e/4XV2pBxejDRb9NLC4te4cq0XvuZNM FhtnrGe1OL57KaPFla/v2Swm3Z/AYvHi3kUWi/7Hr5ktzp/fwG5xtukNu8Wmx9dYLS7vmsNm MeP8PiaLtUfuslvMmPySzYHfY9OqTjaP7d8esHrc7z7O5LF5Sb1H35ZVjB6fN8kFsEXp2RTl l5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXoZfxqectYsEOj 4tmrHYwNjMsUuxg5OSQETCSu9W9j7GLk4hASWMoosenPeiaIhIzEvLN9bBC2sMSfa11sEEWf GCVO/9nNCpJgEzCVuH33E1iRiICyxN+Jq8AmMQscZJFo2XiGESQhLOAusXzzP2YQm0VAVWLy 1X6wZl4BD4mNt3sZITbISdw81wlUw8HBKeApceCmPkhYCKjk9cknrBMY+RYwMqxiFEktLc5N zy021CtOzC0uzUvXS87P3cQIjIZtx35u3sF4aWPwIUYBDkYlHt4TGy5EC7EmlhVX5h5ilOBg VhLh3Xv7YrQQb0piZVVqUX58UWlOavEhRlOgmyYyS4km5wMjNa8k3tDU0NzC0tDc2NzYzEJJ nPe8QWWUkEB6YklqdmpqQWoRTB8TB6dUAyPvZLNgLu3ubft2yklPauzt73uq03SEwW5ep/J2 t3mVQlP1qpZqhu6bv5tnKfejezPqFpxxvLuDr+e2VuGmt/enr13I0HtYkuGOxGad6KVrHlmt llacxuL1aXbN1Gm/ty/T4n7JMNFfeJPJ91amW4wqe+WvhUQwCZrvKrfU7Tyy6IR5fXu9xhYl luKMREMt5qLiRAAG1+5LnAIAAA== Message-Id: <20181025152411eucas1p1d9c15aaa67585ac888b72ef67c258b44~g41qpKjGp2269722697eucas1p1G@eucas1p1.samsung.com> X-CMS-MailID: 20181025152411eucas1p1d9c15aaa67585ac888b72ef67c258b44 X-Msg-Generator: CA X-RootMTR: 20181025152411eucas1p1d9c15aaa67585ac888b72ef67c258b44 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181025152411eucas1p1d9c15aaa67585ac888b72ef67c258b44 References: <1540481030-15019-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Fri, 26 Oct 2018 07:46:32 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The fimd hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TRATS2 with Exynos 4412 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski --- v2 changes: - write blue lower ALPHA0 value correctly, - set ALPHA1 to zero, - move local variables from set_bldmod to set_pixfmt, drivers/gpu/drm/exynos/exynos_drm_fimd.c | 75 +++++++++++++++++++++++--------- include/video/samsung_fimd.h | 1 + 2 files changed, 55 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b7f56935a46b..9c4ff60326b9 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -229,6 +229,21 @@ static const uint32_t fimd_formats[] = { DRM_FORMAT_ARGB8888, }; +static const unsigned int capabilities[WINDOWS_NR] = { + 0, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, +}; + +static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, + u32 val) +{ + val = (val & mask) | (readl(ctx->regs + reg) & ~mask); + writel(val, ctx->regs + reg); +} + static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; @@ -552,13 +567,43 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) writel(val, ctx->regs + VIDCON0); } +static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, + unsigned int alpha) +{ + u32 win_alpha_l = (alpha >> 8) & 0xf; + u32 win_alpha_h = alpha >> 12; + u32 val = 0; + + /* OSD alpha */ + val = VIDISD14C_ALPHA0_R(win_alpha_h) | + VIDISD14C_ALPHA0_G(win_alpha_h) | + VIDISD14C_ALPHA0_B(win_alpha_h) | + VIDISD14C_ALPHA1_R(0x0) | + VIDISD14C_ALPHA1_G(0x0) | + VIDISD14C_ALPHA1_B(0x0); + writel(val, ctx->regs + VIDOSD_C(win)); + + val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | + VIDW_ALPHA_B(win_alpha_l); + writel(val, ctx->regs + VIDWnALPHA0(win)); + + val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | + VIDW_ALPHA_B(0x0); + writel(val, ctx->regs + VIDWnALPHA1(win)); + + fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, + BLENDCON_NEW_8BIT_ALPHA_VALUE); +} static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, - uint32_t pixel_format, int width) + struct drm_framebuffer *fb, int width) { - unsigned long val; - - val = WINCONx_ENWIN; + struct exynos_drm_plane plane = ctx->planes[win]; + struct exynos_drm_plane_state *state = + to_exynos_plane_state(plane.base.state); + uint32_t pixel_format = fb->format->format; + unsigned int alpha = state->base.alpha; + u32 val = WINCONx_ENWIN; /* * In case of s3c64xx, window 0 doesn't support alpha channel. @@ -596,6 +641,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; + val |= WINCON1_ALPHA_MUL; break; } @@ -615,22 +661,8 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, writel(val, ctx->regs + WINCON(win)); /* hardware window 0 doesn't support alpha channel. */ - if (win != 0) { - /* OSD alpha */ - val = VIDISD14C_ALPHA0_R(0xf) | - VIDISD14C_ALPHA0_G(0xf) | - VIDISD14C_ALPHA0_B(0xf) | - VIDISD14C_ALPHA1_R(0xf) | - VIDISD14C_ALPHA1_G(0xf) | - VIDISD14C_ALPHA1_B(0xf); - - writel(val, ctx->regs + VIDOSD_C(win)); - - val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | - VIDW_ALPHA_G(0xf); - writel(val, ctx->regs + VIDWnALPHA0(win)); - writel(val, ctx->regs + VIDWnALPHA1(win)); - } + if (win != 0) + fimd_win_set_bldmod(ctx, win, alpha); } static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) @@ -786,7 +818,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc, DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); } - fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w); + fimd_win_set_pixfmt(ctx, win, fb, state->src.w); /* hardware window 0 doesn't support color key. */ if (win != 0) @@ -988,6 +1020,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); ctx->configs[i].zpos = i; ctx->configs[i].type = fimd_win_types[i]; + ctx->configs[i].capabilities = capabilities[i]; ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, &ctx->configs[i]); if (ret) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index d8fc96ed11e9..f070b7c0d2cf 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -211,6 +211,7 @@ #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) #define WINCON1_LOCALSEL_CAMIF (1 << 23) +#define WINCON1_ALPHA_MUL (1 << 7) #define WINCON1_BLD_PIX (1 << 6) #define WINCON1_BPPMODE_MASK (0xf << 2) #define WINCON1_BPPMODE_SHIFT 2 From patchwork Thu Oct 25 15:23:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Manszewski X-Patchwork-Id: 10657025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 28344109C for ; Fri, 26 Oct 2018 07:47:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 197042B57F for ; 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Thu, 25 Oct 2018 15:24:12 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20181025152412eusmtrp178c22e8758df13130918aa3c28aca94b~g41rrzKcJ0121301213eusmtrp1p; Thu, 25 Oct 2018 15:24:12 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-39-5bd1e01cb098 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id E7.95.04128.C10E1DB5; Thu, 25 Oct 2018 16:24:12 +0100 (BST) Received: from AMDC2034.DIGITAL.local (unknown [106.120.51.41]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20181025152411eusmtip1dc7e3ee2b38a2b41204320933548daec~g41rBkQyw2540325403eusmtip1y; Thu, 25 Oct 2018 15:24:11 +0000 (GMT) From: Christoph Manszewski To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 2/2] drm/exynos: fimd: Make pixel blend mode configurable Date: Thu, 25 Oct 2018 17:23:50 +0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540481030-15019-1-git-send-email-c.manszewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm27kqLY9T8vOS0qwoI00qOFGEgeGi6PKnH02rk550pFN33EwJ HCrivaVEoiLD8tI0L8u7KKnVUmlmXprOG1h5y8IrJSW5Ha1/z/s87/M+7/vxkYioDHMhZfIY ViFnwsW4Ldrw9pfxqNtUv/RYavoperTKiNFZxm4BXZtXjdGG1hJAD679wOmcSQ1Kz070o/TD 6QWE7uurIej3id8IWj89jNEDLYU4ndfXLqBfvB4n6LzcOdzPTqLXpeGSxvUpTDKZYRBIXj5L kGTX6YBkRe9+Fb9heyaEDZepWIXP2du2YdnD9SBqw+t+V3eVQA2aPdOBDQmpE9Cs3QDpwJYU UeUA5nw3E3yxCuDy45VtZQXAL5vaLYW0WvQlly1uEVUG4FDBxX+GN61jmEXAqZPQPL6MW7Aj 5Qn/PNJZByFUPQrbuk0Ci+BAXYJJbd1WjFIHYM1SPuB3cocjxjTEEmZDXYCvRnwsXkg1ELC0 Msc6VEip4GaNabvfHy4Xp+A8doDzhjqCx26wNzcT5c1JAI6uDmN8oQGwoyId5btOQ71pXmBJ Q6jDsLrFh6fPwcEhI85fvBuaFu0tNLIFcxqeIDwthKkpIr77IFyoq8N3YmdX1rZXk8CujiyE f6BCAMvVE6gGeOT/D9MCoANOrJKLCGU5Xzkb680xEZxSHuodHBmhB1vfp3fTsNwE1j7e6QQU CcS7hO9qPkhFGKPi4iI6ASQRsaOwzdwvFQlDmLh4VhF5S6EMZ7lO4EqiYidhaVGtVESFMjHs PZaNYhU7qoC0cVGDBO3S0yY4W/t575z2d/Ihv6C4oj1Vsb6yENVX++PZQTMVY5lBaLvSH1sM nJFd6UeavJrUP/2iiQmNa6lhLiAwau5Irm4k8eYn/wzxebXzYDQX30zLCq4FJCs9elrGrg8M BdsRXT3JyuIHGiYSrtcPdyqem+/u29/ovLAaXRkuRrkwxtcLUXDMXz4qsDQ6AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e/4XV2ZBxejDbpaWS1urTvHatF77iST xcYZ61ktju9eymhx5et7NotJ9yewWLy4d5HFov/xa2aL8+c3sFucbXrDbrHp8TVWi8u75rBZ zDi/j8li7ZG77BYzJr9kc+D32LSqk81j+7cHrB73u48zeWxeUu/Rt2UVo8fnTXIBbFF6NkX5 pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZllqUX6dgl6GX3XtjIW/NKq OHxyHVMD407lLkYODgkBE4lNS/26GLk4hASWMkq83LWErYuREyguIzHvbB+ULSzx51oXG0TR J0aJ7zteMYIk2ARMJW7f/QRWJCKgLPF34ipGkCJmgYMsEi0bz4AVCQv4SDTvPckEYrMIqEps +DgLLM4r4CExd801FogNchI3z3Uyg1zEKeApceCmPkhYCKjk9cknrBMY+RYwMqxiFEktLc5N zy020itOzC0uzUvXS87P3cQIjIVtx35u2cHY9S74EKMAB6MSD++JDReihVgTy4orcw8xSnAw K4nw7r19MVqINyWxsiq1KD++qDQntfgQoynQTROZpUST84FxmlcSb2hqaG5haWhubG5sZqEk znveoDJKSCA9sSQ1OzW1ILUIpo+Jg1OqgXHdWWnjP5Iv8icpr7luNnHhYfuzSbXyYWIhD8Vm qT0U1kq0fxV47n1lcqjgAqGpG3TrThufrE5T5mi76inicvOHKF9OwPlA71lBOsJXhKJe+Zwz Y+X8p39j6pPzE7+7GbHkp+5x37VqyWHrnjvGB4tqbNMe5YofDfjY/Ubn3qYdM7Z73VB43anE UpyRaKjFXFScCACmjOMFmwIAAA== Message-Id: <20181025152412eucas1p290814b0ac4ce25e64fa166b691819e69~g41r7Mkz81123611236eucas1p2W@eucas1p2.samsung.com> X-CMS-MailID: 20181025152412eucas1p290814b0ac4ce25e64fa166b691819e69 X-Msg-Generator: CA X-RootMTR: 20181025152412eucas1p290814b0ac4ce25e64fa166b691819e69 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181025152412eucas1p290814b0ac4ce25e64fa166b691819e69 References: <1540481030-15019-1-git-send-email-c.manszewski@samsung.com> X-Mailman-Approved-At: Fri, 26 Oct 2018 07:46:32 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , Christoph Manszewski , Seung-Woo Kim , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , David Airlie , Kyungmin Park , Kukjin Kim , linux-arm-kernel@lists.infradead.org, Marek Szyprowski MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The fimd hardware supports different blend modes. Add pixel blend mode property and make it configurable, by modifying the blend equation. Tested on TRATS2 with Exynos 4412 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski --- changes in v2: - add premultiplied mode by setting blending equation accordingly, drivers/gpu/drm/exynos/exynos_drm_fimd.c | 68 ++++++++++++++++++++++++++------ include/video/samsung_fimd.h | 9 +++++ 2 files changed, 65 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 9c4ff60326b9..fbf9bfa20e9a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -231,10 +231,10 @@ static const uint32_t fimd_formats[] = { static const unsigned int capabilities[WINDOWS_NR] = { 0, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }; static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, @@ -567,13 +567,52 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) writel(val, ctx->regs + VIDCON0); } +static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, + unsigned int alpha, unsigned int pixel_alpha) +{ + u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); + u32 val = 0; + + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + case DRM_MODE_BLEND_COVERAGE: + val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); + val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); + break; + case DRM_MODE_BLEND_PREMULTI: + default: + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); + val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); + } else { + val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); + val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); + } + break; + } + fimd_set_bits(ctx, BLENDEQx(win), mask, val); +} + static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, - unsigned int alpha) + unsigned int alpha, unsigned int pixel_alpha) { u32 win_alpha_l = (alpha >> 8) & 0xf; u32 win_alpha_h = alpha >> 12; u32 val = 0; + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + case DRM_MODE_BLEND_PREMULTI: + default: + val |= WINCON1_ALPHA_SEL; + val |= WINCON1_BLD_PIX; + val |= WINCON1_ALPHA_MUL; + break; + } + fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); + /* OSD alpha */ val = VIDISD14C_ALPHA0_R(win_alpha_h) | VIDISD14C_ALPHA0_G(win_alpha_h) | @@ -604,6 +643,12 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, uint32_t pixel_format = fb->format->format; unsigned int alpha = state->base.alpha; u32 val = WINCONx_ENWIN; + unsigned int pixel_alpha; + + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; /* * In case of s3c64xx, window 0 doesn't support alpha channel. @@ -637,11 +682,9 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, break; case DRM_FORMAT_ARGB8888: default: - val |= WINCON1_BPPMODE_25BPP_A1888 - | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; + val |= WINCON1_BPPMODE_25BPP_A1888; val |= WINCONx_WSWP; val |= WINCONx_BURSTLEN_16WORD; - val |= WINCON1_ALPHA_MUL; break; } @@ -657,12 +700,13 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, val &= ~WINCONx_BURSTLEN_MASK; val |= WINCONx_BURSTLEN_4WORD; } - - writel(val, ctx->regs + WINCON(win)); + fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); /* hardware window 0 doesn't support alpha channel. */ - if (win != 0) - fimd_win_set_bldmod(ctx, win, alpha); + if (win != 0) { + fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); + fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); + } } static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index f070b7c0d2cf..4ba5efe8d086 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -198,6 +198,7 @@ #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) #define WINCONx_ENWIN (1 << 0) +#define WINCONx_BLEND_MODE_MASK (0xc2) #define WINCON0_BPPMODE_MASK (0xf << 2) #define WINCON0_BPPMODE_SHIFT 2 @@ -438,6 +439,14 @@ #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) /* Blending equation control */ +#define BLENDEQx(_win) (0x244 + ((_win - 1) * 4)) +#define BLENDEQ_ZERO 0x0 +#define BLENDEQ_ONE 0x1 +#define BLENDEQ_ALPHA_A 0x2 +#define BLENDEQ_ONE_MINUS_ALPHA_A 0x3 +#define BLENDEQ_ALPHA0 0x6 +#define BLENDEQ_B_FUNC_F(_x) (_x << 6) +#define BLENDEQ_A_FUNC_F(_x) (_x << 0) #define BLENDCON 0x260 #define BLENDCON_NEW_MASK (1 << 0) #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)