From patchwork Fri Oct 26 07:51:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 10657041 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C507109C for ; Fri, 26 Oct 2018 07:54:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 500332C23D for ; Fri, 26 Oct 2018 07:54:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4332B2C24D; Fri, 26 Oct 2018 07:54:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7E172C23D for ; Fri, 26 Oct 2018 07:54:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FCfWaqu2rGzWt2Py3xxl04Hqi6f4JiXsr5S08eXeL60=; b=Ee/JHproMIzfwO V3P6BO0TTXtemq0ESRzMVnAZ3AZROm6OavOo8g/mOWcQiiqXY9FdcaCd99pcGZPk/n+Lm2NbZQoYn GfezTe7UcTm0dZ1eUSsdV7e06LYj6P8cyajt7ZkhDrrK8cA6Ns0N7qn1EYlLU7ZPeIZEtuy+9pxcY yMwmH8d0WdnDg2cl2/XATYaMR8++wgxTwxL+CdYH0M7zYx8Tm0jZWyUAjUhfvIkxKybBGdA0qAsCF 8n0tsZDP7fDcZ9RnL3eaF0GxL36czhFq7UDfntmoo6TJeYMQyEzxo/1iDQjq4Gmlfx7Fv+bFh6ULh B9o7saY+vdSzfFRyUcBQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwwr-0001vU-3p; Fri, 26 Oct 2018 07:54:25 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuN-0000iX-O2 for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 07:51:55 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7437439C1721C; Fri, 26 Oct 2018 15:51:29 +0800 (CST) Received: from localhost (10.177.19.219) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.408.0; Fri, 26 Oct 2018 15:51:24 +0800 From: Yang Yingliang To: , Subject: [PATCH v2 1/4] irqchip/gic-v3-mbi: fix uninitialized mbi_lock Date: Fri, 26 Oct 2018 15:51:17 +0800 Message-ID: <1540540280-26612-2-git-send-email-yangyingliang@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> References: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.219] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_005151_992822_C3EF29FA X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, tglx@linutronix.de, yangyingliang@huawei.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP mbi_lock is uninitialized, use marco DEFINE_MUTEX to initialize it. Signed-off-by: Yang Yingliang --- drivers/irqchip/irq-gic-v3-mbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index ad70e7c..fbfa7ff 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -24,7 +24,7 @@ struct mbi_range { unsigned long *bm; }; -static struct mutex mbi_lock; +static DEFINE_MUTEX(mbi_lock); static phys_addr_t mbi_phys_base; static struct mbi_range *mbi_ranges; static unsigned int mbi_range_nr; From patchwork Fri Oct 26 07:51:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 10657055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 095B114BD for ; Fri, 26 Oct 2018 08:02:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF1842BDBB for ; Fri, 26 Oct 2018 08:02:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E38462BDCE; Fri, 26 Oct 2018 08:02:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9B70E2BDBB for ; Fri, 26 Oct 2018 08:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2MXCtp7gHKUQIbzpI/CYCnoSsOt/Vx/vSDTEdTj0Qx0=; b=I/wZCiEnMRdvd3 aikUd96o/iyVEcojk5r0JW4wMHNPXHYcV/4AiUZoGSS4zleGNp1jPbbkQ7z1Jzm8/eD44XSkcq8o4 6XES6ERTzPF+EOOvbGBD/AbGEzgfL3cHMeusIjYBqI92EFvbKiVBB/ZC7H8oZDadQMRXitiMi3OHI RSgNmO9oMxRbmRFZ7uictp/DugkAvy8/GXX0dmC+PdbBJhpp0dpMIK/wUDP1FowoLQNNV73m4kE4l qsbfla4lXeFPkE6BezaKF4pFs4PMYlgYMzGM0lYswt0iMqUyChlXM4yIcov04BqT3ROEefd5xu31P xu2OqJ8qMw2C4ZmiFG9Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFx4T-0006HI-Vm; Fri, 26 Oct 2018 08:02:18 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuN-0000iY-OE for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 07:51:55 +0000 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id A5C65416B622D; Fri, 26 Oct 2018 15:51:30 +0800 (CST) Received: from localhost (10.177.19.219) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.408.0; Fri, 26 Oct 2018 15:51:25 +0800 From: Yang Yingliang To: , Subject: [PATCH v2 2/4] irqchip/mbigen: rename register marcros Date: Fri, 26 Oct 2018 15:51:18 +0800 Message-ID: <1540540280-26612-3-git-send-email-yangyingliang@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> References: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.219] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_005152_010253_D78461B8 X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, tglx@linutronix.de, yangyingliang@huawei.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP A MBIGEN can also be used for generating SPIs, so let's rename register macros to make them more resonable. The first 64-pins of MBIGEN is used by SPIs, so rename RESERVED_IRQ_PER_MBIGEN_CHIP to SPI_NUM_PER_MBIGEN_CHIP and change the comment for this marcro. Signed-off-by: Yang Yingliang --- drivers/irqchip/irq-mbigen.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 567b29c..f05998f 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -30,14 +30,14 @@ /* Interrupt numbers per mbigen node supported */ #define IRQS_PER_MBIGEN_NODE 128 -/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ -#define RESERVED_IRQ_PER_MBIGEN_CHIP 64 +/* 64 irqs (Pin0-pin63) are used for SPIs on each mbigen chip */ +#define SPI_NUM_PER_MBIGEN_CHIP 64 /* The maximum IRQ pin number of mbigen chip(start from 0) */ #define MAXIMUM_IRQ_PIN_NUM 1407 /** - * In mbigen vector register + * In mbigen lpi vector register * bit[21:12]: event id value * bit[11:0]: device id */ @@ -48,7 +48,7 @@ #define MBIGEN_NODE_OFFSET 0x1000 /* offset of vector register in mbigen node */ -#define REG_MBIGEN_VEC_OFFSET 0x200 +#define REG_MBIGEN_LPI_VEC_OFFSET 0x200 /** * offset of clear register in mbigen node @@ -62,7 +62,7 @@ * This register is used to configure interrupt * trigger type */ -#define REG_MBIGEN_TYPE_OFFSET 0x0 +#define REG_MBIGEN_LPI_TYPE_OFFSET 0x0 /** * struct mbigen_device - holds the information of mbigen device. @@ -79,12 +79,12 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) { unsigned int nid, pin; - hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; pin = hwirq % IRQS_PER_MBIGEN_NODE; return pin * 4 + nid * MBIGEN_NODE_OFFSET - + REG_MBIGEN_VEC_OFFSET; + + REG_MBIGEN_LPI_VEC_OFFSET; } static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, @@ -92,7 +92,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, { unsigned int nid, irq_ofst, ofst; - hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; @@ -100,7 +100,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, ofst = irq_ofst / 32 * 4; *addr = ofst + nid * MBIGEN_NODE_OFFSET - + REG_MBIGEN_TYPE_OFFSET; + + REG_MBIGEN_LPI_TYPE_OFFSET; } static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, @@ -183,7 +183,7 @@ static int mbigen_domain_translate(struct irq_domain *d, return -EINVAL; if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || - (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) + (fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP)) return -EINVAL; else *hwirq = fwspec->param[0]; From patchwork Fri Oct 26 07:51:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 10657039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDF07109C for ; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF9E227EED for ; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1E3927FB7; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3721227EED for ; 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Fri, 26 Oct 2018 07:53:10 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuN-0000ip-O5 for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 07:51:55 +0000 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id D9C85AE3095BF; Fri, 26 Oct 2018 15:51:34 +0800 (CST) Received: from localhost (10.177.19.219) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.408.0; Fri, 26 Oct 2018 15:51:26 +0800 From: Yang Yingliang To: , Subject: [PATCH v2 3/4] irqchip/mbigen: add support for a MBIGEN generating SPIs Date: Fri, 26 Oct 2018 15:51:19 +0800 Message-ID: <1540540280-26612-4-git-send-email-yangyingliang@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> References: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.219] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_005151_956254_DC153853 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, tglx@linutronix.de, yangyingliang@huawei.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now with 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"), we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR. The first 64-pins of each MBIGEN chip is used to generate SPIs, and each MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate the pin index in a unified way in mbigen_domain_translate(). Also Add TYPE and VEC registers that used by generating SPIs, the driver can access them when MBIGEN is used to generate SPIs. Signed-off-by: Yang Yingliang --- drivers/irqchip/irq-mbigen.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index f05998f..72db969 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -48,6 +48,7 @@ #define MBIGEN_NODE_OFFSET 0x1000 /* offset of vector register in mbigen node */ +#define REG_MBIGEN_SPI_VEC_OFFSET 0x500 #define REG_MBIGEN_LPI_VEC_OFFSET 0x200 /** @@ -62,6 +63,7 @@ * This register is used to configure interrupt * trigger type */ +#define REG_MBIGEN_SPI_TYPE_OFFSET 0x400 #define REG_MBIGEN_LPI_TYPE_OFFSET 0x0 /** @@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) { unsigned int nid, pin; + if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) + return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET); + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; pin = hwirq % IRQS_PER_MBIGEN_NODE; @@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, { unsigned int nid, irq_ofst, ofst; + if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) { + *mask = 1 << (hwirq % 32); + ofst = hwirq / 32 * 4; + *addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET; + return; + } + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; @@ -162,14 +174,22 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) u32 val; base += get_mbigen_vec_reg(d->hwirq); + + /* + * The address of GICD_SETSPI_NSR and GITS_TRANSLATER + * is encoded in mbigen register by default. So,we don't + * need to program the doorbell address at here. + */ + if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) { + writel_relaxed(msg->data, base); + return; + } + val = readl_relaxed(base); val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); val |= (msg->data << IRQ_EVENT_ID_SHIFT); - /* The address of doorbell is encoded in mbigen register by default - * So,we don't need to program the doorbell address at here - */ writel_relaxed(val, base); } @@ -182,8 +202,7 @@ static int mbigen_domain_translate(struct irq_domain *d, if (fwspec->param_count != 2) return -EINVAL; - if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || - (fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP)) + if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) return -EINVAL; else *hwirq = fwspec->param[0]; From patchwork Fri Oct 26 07:51:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 10657035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFEA7109C for ; Fri, 26 Oct 2018 07:52:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E48C42C217 for ; Fri, 26 Oct 2018 07:52:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D634E2C21C; Fri, 26 Oct 2018 07:52:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 56E602C217 for ; Fri, 26 Oct 2018 07:52:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=II7b0wcXBZeoIEzquz/tuecQL+KL6L2Ci/0ylhvJF/I=; b=mHsjzaAoo7h4lD Kh01EUd2t7+HOl5Z0n4TiGd9Gnp/Iz5jQl27hc6KDDHjR7io1RJya2VPu+pSlWg+FB30KpMKKwHGD MeAphLZrCZflWIt4EzmP9XpVmg5XGm8HKbe7lMyq0wn5jVtPbn196ni/OEhmvdeSm/W+fEbbAOI6M VvMf6w1t9cHc9OWNV+BYibRTkyndF6XDmJjRT7vsLvDV1fpoN4NYcZjg0IPLGOp9XNwolojrn8vGR fx331hUxrzBD+2c3luDoAApEUGCp9ZD07J2UiRcdyp+wERLNKWSIPXWgMMa/SwfQI9/ds4ReCO4wt 84FpFn77uxXqWQ8TZB4A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuS-0000mU-Vy; Fri, 26 Oct 2018 07:51:57 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuN-0000ir-O8 for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 07:51:53 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 99CFFCE03FEB3; Fri, 26 Oct 2018 15:51:34 +0800 (CST) Received: from localhost (10.177.19.219) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.408.0; Fri, 26 Oct 2018 15:51:27 +0800 From: Yang Yingliang To: , Subject: [PATCH v2 4/4] dt-bindings/irqchip/mbigen: add example of MBIGEN generate SPIs Date: Fri, 26 Oct 2018 15:51:20 +0800 Message-ID: <1540540280-26612-5-git-send-email-yangyingliang@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> References: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.219] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_005151_970765_F3A67B0C X-CRM114-Status: UNSURE ( 9.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, tglx@linutronix.de, yangyingliang@huawei.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now MBIGEN can support to generate SPIs by writing GICD_SETSPIR. Add dt example to help document. Signed-off-by: Yang Yingliang --- .../interrupt-controller/hisilicon,mbigen-v2.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt index a6813a0..298c033 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt @@ -10,7 +10,7 @@ Hisilicon designed mbigen to collect and generate interrupt. Non-pci devices can connect to mbigen and generate the -interrupt by writing ITS register. +interrupt by writing GICD or ITS register. The mbigen chip and devices connect to mbigen have the following properties: @@ -64,6 +64,13 @@ Examples: num-pins = <2>; #interrupt-cells = <2>; }; + + mbigen_spi_example:spi_example { + interrupt-controller; + msi-parent = <&gic>; + num-pins = <2>; + #interrupt-cells = <2>; + }; }; Devices connect to mbigen required properties: @@ -82,3 +89,11 @@ Examples: interrupts = <656 1>, <657 1>; }; + + spi_example: spi0@0 { + compatible = "spi,example"; + reg = <0 0 0 0>; + interrupt-parent = <&mbigen_spi_example>; + interrupts = <13 4>, + <14 4>; + };