From patchwork Mon Sep 21 11:02:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCC5A112C for ; Mon, 21 Sep 2020 11:28:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF73E207BC for ; Mon, 21 Sep 2020 11:28:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF73E207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF5DD6E267; Mon, 21 Sep 2020 11:28:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C84836E25F; Mon, 21 Sep 2020 11:28:27 +0000 (UTC) IronPort-SDR: 185DM48JHxbBtEdj6ttXrULNckMVPRzcWaQdffGO3NqOj+5Gm5ePs0Dg8SBR4N4cji0Wy9YKaW MpKoXAkiB6Nw== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="148107494" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="148107494" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:23 -0700 IronPort-SDR: LhtCOg19lLAweiwtuJmjyFQGXp/IgOign8fAteI9hrWstJrUhVToNhHEe06TwAQj7uqzkR02Xu JKXwXHHHcCVA== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009022" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:20 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 1/8] drm/i915: Add enable/disable flip done and flip done handler Date: Mon, 21 Sep 2020 16:32:03 +0530 Message-Id: <20200921110210.21182-2-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add enable/disable flip done functions and the flip done handler function which handles the flip done interrupt. Enable the flip done interrupt in IER. Enable flip done function is called before writing the surface address register as the write to this register triggers the flip done interrupt Flip done handler is used to send the page flip event as soon as the surface address is written as per the requirement of async flips. The interrupt is disabled after the event is sent. v2: -Change function name from icl_* to skl_* (Paulo) -Move flip handler to this patch (Paulo) -Remove vblank_put() (Paulo) -Enable flip done interrupt for gen9+ only (Paulo) -Enable flip done interrupt in power_well_post_enable hook (Paulo) -Removed the event check in flip done handler to handle async flips without pageflip events. v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) -Make the pending vblank event NULL in the beginning of flip_done_handler to remove sporadic WARN_ON that is seen. v4: -Calculate timestamps using flip done time stamp and current timestamp for async flips (Ville) v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter' static.(Reported-by: kernel test robot ) -Fix the typo in commit message. v6: -Revert back to old time stamping code. -Remove the break while calling skl_enable_flip_done. (Paulo) v7: -Rebased. v8: -Rebased. v9: -Use struct drm_i915_private *i915 in new code. (Ville) -Use intel_crtc instead of drm_crtc. (Ville) -Do not mix the flip done and vblank hooks. (Ville) v10: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 8 +++ drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.h | 3 ++ 3 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5a9d933e425a..171d293a0d88 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15607,6 +15607,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_dbuf_pre_plane_update(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + skl_enable_flip_done(crtc); + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); @@ -15628,6 +15633,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_flip_done(dev, &state->base); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + skl_disable_flip_done(crtc); + if (new_crtc_state->hw.active && !needs_modeset(new_crtc_state) && !new_crtc_state->preload_luts && diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 759f523c6a6b..9b8796c1a256 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1245,6 +1245,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 crc4) {} #endif +static void flip_done_handler(struct drm_i915_private *i915, + enum pipe pipe) +{ + struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe); + struct drm_crtc_state *crtc_state = crtc->base.state; + struct drm_pending_vblank_event *e = crtc_state->event; + struct drm_device *dev = &i915->drm; + unsigned long irqflags; + + spin_lock_irqsave(&dev->event_lock, irqflags); + + crtc_state->event = NULL; + + drm_crtc_send_vblank_event(&crtc->base, e); + + spin_unlock_irqrestore(&dev->event_lock, irqflags); +} static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -2329,6 +2346,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) + flip_done_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2650,6 +2670,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) return 0; } +void skl_enable_flip_done(struct intel_crtc *crtc) +{ + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&i915->irq_lock, irqflags); + + bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&i915->irq_lock, irqflags); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ @@ -2710,6 +2743,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } +void skl_disable_flip_done(struct intel_crtc *crtc) +{ + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&i915->irq_lock, irqflags); + + bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&i915->irq_lock, irqflags); +} + static void ibx_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -2920,6 +2966,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; + if (INTEL_GEN(dev_priv) >= 9) + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; + spin_lock_irq(&dev_priv->irq_lock); if (!intel_irqs_enabled(dev_priv)) { @@ -3403,6 +3452,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; + if (INTEL_GEN(dev_priv) >= 9) + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; + de_port_enables = de_port_masked; if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 25f25cd95818..2efe609519ca 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -118,6 +118,9 @@ void i965_disable_vblank(struct drm_crtc *crtc); void ilk_disable_vblank(struct drm_crtc *crtc); void bdw_disable_vblank(struct drm_crtc *crtc); +void skl_enable_flip_done(struct intel_crtc *crtc); +void skl_disable_flip_done(struct intel_crtc *crtc); + void gen2_irq_reset(struct intel_uncore *uncore); void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier); From patchwork Mon Sep 21 11:02:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 767F36CA for ; Mon, 21 Sep 2020 11:28:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52E18207BC for ; Mon, 21 Sep 2020 11:28:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52E18207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 918EC6E266; Mon, 21 Sep 2020 11:28:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id A34966E26C; Mon, 21 Sep 2020 11:28:28 +0000 (UTC) IronPort-SDR: f2F1YTlBGDvix0PRbeHlnJnD7Fr9UP0fQcFDHchTQ/UN0jm1qSkpRMlH2ZuFaDOvFqMXzP2HUz dV4dFAmGfevQ== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="148107511" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="148107511" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:28 -0700 IronPort-SDR: RyLwb35ErvFaZClXM7+Ha9qw1uiUBzy3Co1qBzzQLAAYd6lX6r3vWwhfPsyzKRb8X/SfHkoPvd viadxsDpN8/Q== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009064" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:25 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 2/8] drm/i915: Add support for async flips in I915 Date: Mon, 21 Sep 2020 16:32:04 +0530 Message-Id: <20200921110210.21182-3-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Set the Async Address Update Enable bit in plane ctl when async flip is requested. v2: -Move the Async flip enablement to individual patch (Paulo) v3: -Rebased. v4: -Add separate plane hook for async flip case (Ville) v5: -Rebased. v6: -Move the plane hook to separate patch. (Paulo) -Remove the early return in skl_plane_ctl. (Paulo) v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville) v8: -Rebased. v9: -Rebased. v10: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 171d293a0d88..30e8908ee263 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 plane_ctl = 0; + if (crtc_state->uapi.async_flip) + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return plane_ctl; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d805d4da6181..e94ca1f8f6b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6923,6 +6923,7 @@ enum { #define PLANE_CTL_TILED_X (1 << 10) #define PLANE_CTL_TILED_Y (4 << 10) #define PLANE_CTL_TILED_YF (5 << 10) +#define PLANE_CTL_ASYNC_FLIP (1 << 9) #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ From patchwork Mon Sep 21 11:02:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D5696CA for ; Mon, 21 Sep 2020 11:29:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4C0320EDD for ; Mon, 21 Sep 2020 11:29:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4C0320EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E50C36E284; Mon, 21 Sep 2020 11:29:08 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7767B6E279; Mon, 21 Sep 2020 11:28:37 +0000 (UTC) IronPort-SDR: 7hqRauCYiFuxsJcQ/zRiZKAE2tUb6ZiPlw47SopphzXb8mQMhdp14H7UaiNZd14FldhhhOIuTE SJCYL4UVI5MA== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="245190777" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="245190777" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:34 -0700 IronPort-SDR: YDshiuJShMqiPlCzhvyVvsBNgbDKsnBcVuy48moc3dCxJVmpSuP2AWh8utEPcFB0DpkJfKOLL7 w42UgwKDC3OA== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009142" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:31 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v11 3/8] drm/i915: Add checks specific to async flips Date: Mon, 21 Sep 2020 16:32:05 +0530 Message-Id: <20200921110210.21182-4-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" If flip is requested on any other plane, reject it. Make sure there is no change in fbc, offset and framebuffer modifiers when async flip is requested. If any of these are modified, reject async flip. v2: -Replace DRM_ERROR (Paulo) -Add check for changes in OFFSET, FBC, RC(Paulo) v3: -Removed TODO as benchmarking tests have been run now. v4: -Added more state checks for async flip (Ville) -Moved intel_atomic_check_async to the end of intel_atomic_check as the plane checks needs to pass before this. (Ville) -Removed crtc_state->enable_fbc check. (Ville) -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async flip case as scanline counter is not reliable here. v5: -Fix typo and other check patch errors seen in CI in 'intel_atomic_check_async' function. v6: -Don't call intel_atomic_check_async multiple times. (Ville) -Remove the check for n_planes in intel_atomic_check_async -Added documentation for async flips. (Paulo) v7: -Replace 'intel_plane' with 'plane'. (Ville) -Replace all uapi.foo as hw.foo. (Ville) -Do not use intel_wm_need_update function. (Ville) -Add destination coordinate check. (Ville) -Do not allow async flip with linear buffer on older hw as it has issues with this. (Ville) -Remove break after intel_atomic_check_async. (Ville) v8: -Rebased. v9: -Replace DRM_DEBUG_KMS with drm_dbg_kms(). (Ville) -Fix comment formatting. (Ville) -Remove gen specific checks. (Ville) -Remove irrelevant FB size check. (Ville) -Add missing stride check. (Ville) -Use drm_rect_equals() instead of individual checks. (Ville) -Call intel_atomic_check_async before state dump. (Ville) v10: -Fix the checkpatch errors seen on CI. v11: -Use const for all plane/crtc states. (Ville) -Use 'switch' instead of 'if' for modifier check. (Ville) -Move documentation changes to a single patch. (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 121 +++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 30e8908ee263..b3ec08f17c65 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14877,6 +14877,121 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, return false; } +static int intel_atomic_check_async(struct intel_atomic_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *old_crtc_state, *new_crtc_state; + const struct intel_plane_state *new_plane_state, *old_plane_state; + struct intel_crtc *crtc; + struct intel_plane *plane; + int i; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (needs_modeset(new_crtc_state)) { + drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n"); + return -EINVAL; + } + + if (!new_crtc_state->hw.active) { + drm_dbg_kms(&i915->drm, "CRTC inactive\n"); + return -EINVAL; + } + if (old_crtc_state->active_planes != new_crtc_state->active_planes) { + drm_dbg_kms(&i915->drm, + "Active planes cannot be changed during async flip\n"); + return -EINVAL; + } + } + + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, + new_plane_state, i) { + /* + * TODO: Async flip is only supported through the page flip IOCTL + * as of now. So support currently added for primary plane only. + * Support for other planes on platforms on which supports + * this(vlv/chv and icl+) should be added when async flip is + * enabled in the atomic IOCTL path. + */ + if (plane->id != PLANE_PRIMARY) + return -EINVAL; + + /* + * FIXME: This check is kept generic for all platforms. + * Need to verify this for all gen9 and gen10 platforms to enable + * this selectively if required. + */ + switch (new_plane_state->hw.fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Yf_TILED: + break; + default: + drm_dbg_kms(&i915->drm, + "Linear memory/CCS does not support async flips\n"); + return -EINVAL; + } + + if (old_plane_state->color_plane[0].stride != + new_plane_state->color_plane[0].stride) { + drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.fb->modifier != + new_plane_state->hw.fb->modifier) { + drm_dbg_kms(&i915->drm, + "Framebuffer modifiers cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.fb->format != + new_plane_state->hw.fb->format) { + drm_dbg_kms(&i915->drm, + "Framebuffer format cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.rotation != + new_plane_state->hw.rotation) { + drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n"); + return -EINVAL; + } + + if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || + !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { + drm_dbg_kms(&i915->drm, + "Plane size/co-ordinates cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { + drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.pixel_blend_mode != + new_plane_state->hw.pixel_blend_mode) { + drm_dbg_kms(&i915->drm, + "Pixel blend mode cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { + drm_dbg_kms(&i915->drm, + "Color encoding cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { + drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n"); + return -EINVAL; + } + } + + return 0; +} + /** * intel_atomic_check - validate state object * @dev: drm device @@ -15045,6 +15160,12 @@ static int intel_atomic_check(struct drm_device *dev, for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) { + ret = intel_atomic_check_async(state); + if (ret) + goto fail; + } + if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) continue; From patchwork Mon Sep 21 11:02:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789423 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2BBBF16BC for ; Mon, 21 Sep 2020 11:29:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F0A2207BC for ; Mon, 21 Sep 2020 11:29:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0F0A2207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2ACFB6E27A; Mon, 21 Sep 2020 11:28:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 07A806E27A; Mon, 21 Sep 2020 11:28:43 +0000 (UTC) IronPort-SDR: MlSl6xzQ6idi491btU+lZCZRbVqToHBF+05nGwBYaOahYKb/S4vwITIuYZI+jRIH7gde4IDmFa wpqQ4SWGTNWw== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738328" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738328" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:40 -0700 IronPort-SDR: CHCJa41bd0hiBAFVVl6kV2J7/1PF4gTNh8YKIFPCfKWW0YRb8+2VWi+R/LD94T+ISl08nK3L2P WCVyYpDaxE1g== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009234" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:36 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips Date: Mon, 21 Sep 2020 16:32:06 +0530 Message-Id: <20200921110210.21182-5-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the flip done event will be sent in the flip_done_handler, no need to add the event to the list and delay it for later. v2: -Moved the async check above vblank_get as it was causing issues for PSR. v3: -No need to wait for vblank to pass, as this wait was causing a 16ms delay once every few flips. v4: -Rebased. v5: -Rebased. v6: -Rebased. v7: -No need of irq disable if we are not doing vblank evade. (Ville) v8: -Rebased. v9: -Move the return in intel_pipe_update_end before tracepoint. (Ville) v10: Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 63040cb0d4e1..76a3d9bfe0de 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) DEFINE_WAIT(wait); u32 psr_status; + if (new_crtc_state->uapi.async_flip) + return; + vblank_start = adjusted_mode->crtc_vblank_start; if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) vblank_start = DIV_ROUND_UP(vblank_start, 2); @@ -200,6 +203,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + if (new_crtc_state->uapi.async_flip) + return; + trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); /* We're still in the vblank-evade critical section, this can't race. From patchwork Mon Sep 21 11:02:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BCC66CA for ; Mon, 21 Sep 2020 11:29:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80335207BC for ; Mon, 21 Sep 2020 11:29:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80335207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 153096E287; Mon, 21 Sep 2020 11:29:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0868E6E282; Mon, 21 Sep 2020 11:28:46 +0000 (UTC) IronPort-SDR: JB/A3WT+PYBZHcYTngJGXLF6EpJisBv0KsaMayzTMLkiKEmDaFsGpiPGHLbnxHcuC4GdDdJlwI 3zPKOMOxW9dQ== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738338" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738338" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:45 -0700 IronPort-SDR: 8ZPLBd8QJx1EnEklOYkI2DI1Y1N/2zTEBGScDllvaP5WAdgbIU5whwsZmu+pDcJxbGvIxCrIqI z/ZmEIxlJvMw== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009268" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:41 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v11 5/8] drm/i915: Add dedicated plane hook for async flip case Date: Mon, 21 Sep 2020 16:32:07 +0530 Message-Id: <20200921110210.21182-6-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This hook is added to avoid writing other plane registers in case of async flips, so that we do not write the double buffered registers during async surface address update. v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville) -Add a vfunc for skl_program_async_surface_address and call it from intel_update_plane. (Ville) v8: -Rebased. v9: -Use if-else instead of return in intel_update_plane(). (Ville) -Rename 'program_async_surface_address' to 'async_flip'. (Ville) v10: -Check if async_flip hook is present before calling it. Otherwise it will OOPS during legacy cursor updates. (Ville) v11: -Rename skl_program_async_surface_address(). (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 ++++- .../drm/i915/display/intel_display_types.h | 3 +++ drivers/gpu/drm/i915/display/intel_sprite.c | 24 +++++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 79032701873a..6bd8e6cdd477 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -408,7 +408,11 @@ void intel_update_plane(struct intel_plane *plane, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); trace_intel_update_plane(&plane->base, crtc); - plane->update_plane(plane, crtc_state, plane_state); + + if (crtc_state->uapi.async_flip && plane->async_flip) + plane->async_flip(plane, crtc_state, plane_state); + else + plane->update_plane(plane, crtc_state, plane_state); } void intel_disable_plane(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3d4bf9b6a0a2..e3339e41ddf7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1183,6 +1183,9 @@ struct intel_plane { struct intel_plane_state *plane_state); int (*min_cdclk)(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); + void (*async_flip)(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); }; struct intel_watermark_params { diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 76a3d9bfe0de..d4b8ba7e8015 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static void +skl_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + unsigned long irqflags; + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + u32 surf_addr = plane_state->color_plane[0].offset; + u32 plane_ctl = plane_state->ctl; + + plane_ctl |= skl_plane_ctl_crtc(crtc_state); + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + static void skl_program_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -3095,6 +3118,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; plane->min_cdclk = skl_plane_min_cdclk; + plane->async_flip = skl_plane_async_flip; if (INTEL_GEN(dev_priv) >= 11) formats = icl_get_plane_formats(dev_priv, pipe, From patchwork Mon Sep 21 11:02:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789439 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B001F112C for ; Mon, 21 Sep 2020 11:29:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9390E20EDD for ; Mon, 21 Sep 2020 11:29:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9390E20EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A2056E29A; Mon, 21 Sep 2020 11:29:14 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 833956E283; Mon, 21 Sep 2020 11:28:50 +0000 (UTC) IronPort-SDR: FKbUzGCpuwZS764iKuOCqvlpHLPi/ALj8oJB+gcipPfoGmcMcI7+BF+M8zMfFX/2sf62WtNdRR 3Xemyxt5oKrw== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738351" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738351" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:50 -0700 IronPort-SDR: mnWzimn1ewagnbTjtrN09b3dgCo1T9xbTLFvDklQQytix/P7gmFCx8HAdFVgS0a7sE4rZlEWHV F9W/wN/hUQBA== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009324" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:46 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 6/8] drm/i915: WA for platforms with double buffered address update enable bit Date: Mon, 21 Sep 2020 16:32:08 +0530 Message-Id: <20200921110210.21182-7-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated before continuing with the normal commit for sync flip. v9: -Rename skl_toggle_async_sync() to skl_disable_async_flip_wa(). (Ville) -Place the declarations appropriately as per need. (Ville) -Take the lock before the reg read. (Ville) -Fix comment and formatting. (Ville) -Use IS_GEN_RANGE() for gen check. (Ville) -Move skl_disable_async_flip_wa() to intel_pre_plane_update(). (Ville) v10: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b3ec08f17c65..dda32ab389b7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6562,6 +6562,43 @@ static void intel_post_plane_update(struct intel_atomic_state *state, icl_wa_scalerclkgating(dev_priv, pipe, false); } +static void skl_disable_async_flip_wa(struct intel_atomic_state *state, + struct intel_crtc *crtc, + const struct intel_crtc_state *new_crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_plane *plane; + struct intel_plane_state *new_plane_state; + int i; + + for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { + u32 update_mask = new_crtc_state->update_planes; + u32 plane_ctl, surf_addr; + enum plane_id plane_id; + unsigned long irqflags; + enum pipe pipe; + + if (crtc->pipe != plane->pipe || + !(update_mask & BIT(plane->id))) + continue; + + plane_id = plane->id; + pipe = plane->pipe; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id)); + surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + + plane_ctl &= ~PLANE_CTL_ASYNC_FLIP; + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); + } + + intel_wait_for_vblank(dev_priv, crtc->pipe); +} + static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -6647,6 +6684,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, */ if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + + /* + * WA for platforms where async address update enable bit + * is double buffered and only latched at start of vblank. + */ + if (old_crtc_state->uapi.async_flip && + !new_crtc_state->uapi.async_flip && + IS_GEN_RANGE(dev_priv, 9, 10)) + skl_disable_async_flip_wa(state, crtc, new_crtc_state); } static void intel_crtc_disable_planes(struct intel_atomic_state *state, From patchwork Mon Sep 21 11:02:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789443 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34D0C6CA for ; Mon, 21 Sep 2020 11:29:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 17C6920EDD for ; Mon, 21 Sep 2020 11:29:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 17C6920EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 909D56E291; Mon, 21 Sep 2020 11:29:19 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B7F16E27A; Mon, 21 Sep 2020 11:28:55 +0000 (UTC) IronPort-SDR: wqi2xqFikxEBajXlf0leGftQ54QRm7CezKpOzypHUwdlLOaYYyVII/bky5sUertDgGdSKxZ1jd dJ6w1Z7GPQYw== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738365" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738365" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:54 -0700 IronPort-SDR: mHNrKb6yOGfCnLzCNxo/Q8B+dQ+BA/0eiZHNrzofPNa/1zx5z/JphLtsahv88hByWoKjyP2ljk I4rOSwL1ORDg== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009375" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:51 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 7/8] Documentation/gpu: Add asynchronous flip documentation for i915 Date: Mon, 21 Sep 2020 16:32:09 +0530 Message-Id: <20200921110210.21182-8-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the details of the implementation of asynchronous flips for i915. v7: -Rebased. v8: -Rebased. v9: -Rebased. v10: Move all documentation changes to this patch. (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- Documentation/gpu/i915.rst | 6 ++++++ drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 33cc6ddf8f64..84ead508f7ad 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -118,6 +118,12 @@ Atomic Plane Helpers .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c :internal: +Asynchronous Page Flip +---------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c + :doc: asynchronous flip implementation + Output Probing -------------- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index dda32ab389b7..c0e0c8992982 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14923,6 +14923,24 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, return false; } +/** + * DOC: asynchronous flip implementation + * + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. + * Correspondingly, support is currently added for primary plane only. + * + * Async flip can only change the plane surface address, so anything else + * changing is rejected from the intel_atomic_check_async() function. + * Once this check is cleared, flip done interrupt is enabled using + * the skl_enable_flip_done() function. + * + * As soon as the surface address register is written, flip done interrupt is + * generated and the requested events are sent to the usersapce in the interrupt + * handler itself. The timestamp and sequence sent during the flip done event + * correspond to the last vblank and have no relation to the actual time when + * the flip done event was sent. + */ static int intel_atomic_check_async(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); From patchwork Mon Sep 21 11:02:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11789441 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4DC61112C for ; Mon, 21 Sep 2020 11:29:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3029A20EDD for ; Mon, 21 Sep 2020 11:29:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3029A20EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C2D6F6E293; Mon, 21 Sep 2020 11:29:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC88D6E282; Mon, 21 Sep 2020 11:28:59 +0000 (UTC) IronPort-SDR: vXso0hWPVgLTIxleLsKvE+TEVMS72RyET3YbvYCtYwrfR7UbepoqUKD0n8M/nKm2JhbIwXqyiB JeFt4gS4g1tg== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="157738378" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="157738378" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 04:28:59 -0700 IronPort-SDR: s7hs4Y7lbsg3WTpW66uF69pCthoQcDhhQ0betjZ3UCl3b3hYzMB/u4wkwIohFnc4IZm7SPQ+sx 2KNrxLpUHr7w== X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="454009428" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2020 04:28:56 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v10 8/8] drm/i915: Enable async flips in i915 Date: Mon, 21 Sep 2020 16:32:10 +0530 Message-Id: <20200921110210.21182-9-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200921110210.21182-1-karthik.b.s@intel.com> References: <20200921110210.21182-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable asynchronous flips in i915 for gen9+ platforms. v2: -Async flip enablement should be a stand alone patch (Paulo) v3: -Move the patch to the end of the series (Paulo) v4: -Rebased. v5: -Rebased. v6: -Rebased. v7: -Rebased. v8: -Rebased. v9: -Rebased. v10: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c0e0c8992982..5bb029cfd440 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -18004,6 +18004,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915) mode_config->funcs = &intel_mode_funcs; + if (INTEL_GEN(i915) >= 9) + mode_config->async_page_flip = true; + /* * Maximum framebuffer dimensions, chosen to match * the maximum render engine surface size on gen4+.