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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id t66-v6sm3224263wmt.5.2018.10.26.04.16.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:42 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 1/9] mailbox: Support blocking transfers in atomic context Date: Fri, 26 Oct 2018 13:16:30 +0200 Message-Id: <20181026111638.10759-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041655_281201_EBD341F4 X-CRM114-Status: GOOD ( 15.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding The mailbox framework supports blocking transfers via completions for clients that can sleep. In order to support blocking transfers in cases where the transmission is not permitted to sleep, add a new ->flush() callback that controller drivers can implement to busy loop until the transmission has been completed. This will automatically be called when available and interrupts are disabled for clients that request blocking transfers. Signed-off-by: Thierry Reding --- drivers/mailbox/mailbox.c | 8 ++++++++ include/linux/mailbox_controller.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 674b35f402f5..0eaf21259874 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -267,6 +267,14 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg) unsigned long wait; int ret; + if (irqs_disabled() && chan->mbox->ops->flush) { + ret = chan->mbox->ops->flush(chan, chan->cl->tx_tout); + if (ret < 0) + tx_tick(chan, ret); + + return ret; + } + if (!chan->cl->tx_tout) /* wait forever */ wait = msecs_to_jiffies(3600000); else diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 74deadb42d76..2a07d93f781a 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -24,6 +24,9 @@ struct mbox_chan; * transmission of data is reported by the controller via * mbox_chan_txdone (if it has some TX ACK irq). It must not * sleep. + * @flush: Called when a client requests transmissions to be blocking but + * the context doesn't allow sleeping. Typically the controller + * will implement a busy loop waiting for the data to flush out. * @startup: Called when a client requests the chan. The controller * could ask clients for additional parameters of communication * to be provided via client's chan_data. This call may @@ -46,6 +49,7 @@ struct mbox_chan; */ struct mbox_chan_ops { int (*send_data)(struct mbox_chan *chan, void *data); + int (*flush)(struct mbox_chan *chan, unsigned long timeout); int (*startup)(struct mbox_chan *chan); void (*shutdown)(struct mbox_chan *chan); bool (*last_tx_done)(struct mbox_chan *chan); From patchwork Fri Oct 26 11:16:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10657261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 638F513BF for ; Fri, 26 Oct 2018 11:31:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F5D02BCFB for ; Fri, 26 Oct 2018 11:31:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41FB02BD14; Fri, 26 Oct 2018 11:31:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DFF4D2BCFB for ; Fri, 26 Oct 2018 11:31:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MB0bVmLyCJSDL2G7C/L9MTOJxjaSkXegvnDfSqekOhc=; b=PGieBGybNGImlc gNPVW8AqzOFy0oCTzbbTPIV20rMTbMpgBWv1nA7Vo/T8dkqjv4Vg7K9g9KTjDMd3ASr9c8otu5pJM Fwt+WBuTpWV4cQ5HK+iTAJgREDBEjBW79qv1CtTpOM+EBNlx8zybFvmQiwb8pGlf6nLoj0np+EFLI heFAKee3PNLfS6Ivn9KszjwQPgTfRsvUVFZeRLjfyMJWPWIgjQ4E8EVye74nObyrA4YRvYttNMA0k kQ/2KxpR5Znc483BgWhAgkBUItppjIIEGQeG/qS/xjOGUjqzwocdK/ztY8tMNvDvj4BrB8zhGO7fi aN9Xmwsk5KYaxHtBUtaw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG0LH-0002sv-M9; Fri, 26 Oct 2018 11:31:51 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG06q-0003eQ-OS for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 11:17:01 +0000 Received: by mail-wr1-x441.google.com with SMTP id i17-v6so893929wre.7 for ; Fri, 26 Oct 2018 04:16:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JZ4YTuB3It2WTh2s9CHheVKlVJx+N83OyNKjw3ja39k=; b=qKdzsUU/RJzo/YihJKzjnaYZs1j56JJnmVTkJ347iJ4ahLQyqmhB20iPdle6aS4/2X bJ/GoC/sqDnKbxsElbErRLeLGk5y6Ee2PDSUheTNfi3Ew4Tvyr7wZ7Tryq+G+b1oIgyM 6zTSeUFOa+jpglUe5zpUGBsJurxdSjfUOXP6nGsac4k79Yu3XnfkNgJ5amdB2rARiWt8 CH6LQyUoxj3i/uJKophCaIQXKKd/14yIMg3XTZSdJYeM0xNNw7g9yNgF85S3mq4pTzrC ChygJv6MiDEZRPqSXM85fXy74QtYsAPFI27PVcPUTiwR3/t5y37mP/NSolImrkCS6r70 aD1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JZ4YTuB3It2WTh2s9CHheVKlVJx+N83OyNKjw3ja39k=; b=BVLdsqx/RY7DeJe+jNY8hhXmyV2bt6RldXlGPRWLntGwASVTsNpCadStN4BOkAFni+ jYw4KF1FXs22bmfFftT/bktCnIs3tS7q/pBMeepIBPm0iuPj8lNNxTwp0t+Hm2yHJqG0 FNq+OD7+hAiiWdqelMdpHbIGTNrfIKFIi1RfBKhvSCLZBu8xq2xnbFMxqZB33u5wPy24 sKsY2QCdU3xLNn+ij6oYUDf+HFlbZZdwMssOhl6ix7ohxK/Elmyh8cq7aoYkxq5ZSlBd zzxlGJmLy2w5QKjtVpANpo1UwZiF5LG5jS8rxn/fF7CKuVPLkm59QTyIK4wkQZ68flZ3 H0fg== X-Gm-Message-State: AGRZ1gL2VZMmhbnjyMfKjv+ftINBpT98fSz1vMADa0+7g0LUNO4kYxtp 2dLAcEU+XBMtflpG7GRGTmQ= X-Google-Smtp-Source: AJdET5dOu+C/2dVlN45lD3RawGcPQNlPD2ESVgv3qCJ8a5Gyv548/8qmAwvU/Zp6DnzMjgxLQFrqPA== X-Received: by 2002:a05:6000:8:: with SMTP id h8mr5255014wrx.103.1540552604877; Fri, 26 Oct 2018 04:16:44 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id q190-v6sm5994451wmg.40.2018.10.26.04.16.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:44 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 2/9] mailbox: Allow multiple controllers per device Date: Fri, 26 Oct 2018 13:16:31 +0200 Message-Id: <20181026111638.10759-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041656_859169_6F6E12FD X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen Look through the whole controller list when mapping device tree phandles to controllers instead of stopping at the first one. Each controller is intended to only contain one kind of mailbox, but some devices (like Tegra HSP) implement multiple kinds and use the same device tree node for all of them. As such, we need to allow multiple mbox_controllers per device tree node. Signed-off-by: Mikko Perttunen --- drivers/mailbox/mailbox.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 0eaf21259874..f34820bcf33c 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -335,7 +335,8 @@ struct mbox_chan *mbox_request_channel(struct mbox_client *cl, int index) list_for_each_entry(mbox, &mbox_cons, node) if (mbox->dev->of_node == spec.np) { chan = mbox->of_xlate(mbox, &spec); - break; + if (!IS_ERR(chan)) + break; } of_node_put(spec.np); From patchwork Fri Oct 26 11:16:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10657243 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6026A109C for ; Fri, 26 Oct 2018 11:19:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49F4D2BB72 for ; Fri, 26 Oct 2018 11:19:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CAB22BF53; Fri, 26 Oct 2018 11:19:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B982E2BB72 for ; Fri, 26 Oct 2018 11:19:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=roiOoAB8CUgI2OfWlrmiD7Yj0udOJGwYZEpUy2GVmpk=; b=oe/Cu160096+jY a1o0iQKw8TjB5wezHNGF6Eu/O0/t9cNEu/IkdI4VSCd2Q6Zo20lAh+bnUgAwDVs2knUuwK4b8qZqk FtSi/yILxY9W+GBS8uZYdfJlZKA+lN1EDBbZPlxhHw15M/NG4RFcgLpWyMxHhpDFpZ2Nv6xiYvYTh s2X7FaZs2eL/X2b3YyWgk+ECoIV686IS9n5q7fVSNZ9VVRB0QFWmSJeLX/gkkZ9UG5MHkIKeKUECo VZcbcMwsjFWjcSST2lcl9tqkVw9ERbc/KlFkqchinBUKZiJqmEDptGbaKApZ60jismQ9UjDwQ1tca XbPiepvDxhRAVyEwKszQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG08y-0004aF-Gs; Fri, 26 Oct 2018 11:19:08 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG06q-0003eW-OY for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 11:17:02 +0000 Received: by mail-wr1-x441.google.com with SMTP id d17-v6so643520wre.11 for ; Fri, 26 Oct 2018 04:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X0uobgskPDvtt66nH74oPn5cyeTQ7D3Fue2q+TPC/RI=; b=R/ZvAVbKKjzEyXKDcuIoPSUbZlb64PmJP5Naps83k0gxN57CvefYm+1qquIfwTS8i2 W8H9gANo9kO4V6O67WOpkm9QvfAgBnShl9VBaxuOybFMskaWAVwX1dt5jtJxv8nJVEJN zl3qmmBp6kyVVqOYJ4gRexm6PdU/foMWzR5RPLy/guAFTThanJlUxxHyw51ZyghIBUVX Uo5tLZcv15ZWmQE6IFgEwkd9rXy02p3aoaQpO+A77ZoHdUK0s6R0+wUABrV2UYKBQPBs 6npaCTrqv1ROOcp47qcLFpdowTI7gP7pF+nJ/CwjMsVu3o+5jkZYcsMbRuAM+0ltHowN 7/Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X0uobgskPDvtt66nH74oPn5cyeTQ7D3Fue2q+TPC/RI=; b=RC4wXsu4fsctNHRawArtMQ4uEdnuc4WkdBDS+LkMgZaNSYL8P4pHnQvZ7DW1k6Jq+V HWyCcBmSezHl5yyW+P2dxkdfPlnmk9+FpYH3yGV9Tdk9ssb933McmGFDS6GtFFFoLIG/ VJC4cl29oaoQlxmS+tuHP7sJmoQAsJrFU+LM0dIS1MxzkzbnB5wr38a91vhcGL77UgRb ObQrfMeaFKXAHyQaWW55pw4jLHFuKVciYGwfAPun8KtzPtPD3zdtwCsqLq+6WShAfAs7 Ll3U3mSgcsJTjj7GYAOUD9RTeSYnsB+WDGjizWaedTN6JBk5pL403HzPmPa0n2SqlMgU aN+Q== X-Gm-Message-State: AGRZ1gLbsRHlHFPQuhIhyIiZzIdPGyCBZbjnZ/cC5aURfxfDPItfvbF4 Udj4zy3Q5IapHUXeERoLTMqbceTW X-Google-Smtp-Source: AJdET5eOHFyQj8UmAXpplwL1Em0ZaVpUifoVxqZ9A5CL92MTbsFiA7WAxsrESAcB6En11O7Acd2jWg== X-Received: by 2002:adf:b6a8:: with SMTP id j40-v6mr4971221wre.55.1540552606624; Fri, 26 Oct 2018 04:16:46 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id j6-v6sm5348687wmd.29.2018.10.26.04.16.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:46 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 3/9] dt-bindings: tegra186-hsp: Add shared interrupts Date: Fri, 26 Oct 2018 13:16:32 +0200 Message-Id: <20181026111638.10759-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041656_830505_5605EB68 X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen HSP interrupts can be routed through exposed "shared interrupts". These interrupts can be mapped to various internal interrupt lines. Add interrupt properties for shared interrupts to the tegra186-hsp device tree bindings. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Reviewed-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt index b99d25fc2f26..620c249363ca 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -15,12 +15,15 @@ Required properties: Array of strings. one of: - "nvidia,tegra186-hsp" + - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" - reg : Offset and length of the register set for the device. - interrupt-names Array of strings. Contains a list of names for the interrupts described by the interrupt property. May contain the following entries, in any order: - "doorbell" + - "sharedN", where 'N' is a number from zero up to the number of + external interrupts supported by the HSP instance minus one. Users of this binding MUST look up entries in the interrupt property by name, using this interrupt-names property to do so. - interrupts From patchwork Fri Oct 26 11:16:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10657257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C121109C for ; Fri, 26 Oct 2018 11:23:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3689B2BF9B for ; Fri, 26 Oct 2018 11:23:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2659C2BFDA; Fri, 26 Oct 2018 11:23:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DD00B2BF9B for ; Fri, 26 Oct 2018 11:23:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DLRbpQPrI+DBIrF/ildjeEcmdkDGZbQM5wRGFlHwh6k=; b=prNXUphI9gwk3I q70KlD6WxgXZIyV+4jFwFHG44kwITcvZaT8lQfbN39Xgq9O7fZheHSFvNtvCO3kVRSEQJ7btRaCsh ILUQaSbygb+m2mkCjdU7v6toZaGkwWyUU2VNfqf0CbAnWDLFz+gb5OSmIKq9g+EPWRIJrW2kWsPNq /lzpxegM++ustz+r0SuA77MW4OvRbfL3ucfSdYKMhBimuAQIaYDpaWm6aGThnAH4XQsAxtY3KxztI 0W8JfPQyFFsXKYsnmJPaJg1fmjIE5dPgqaw4V9r7fH5BHqB1vint1A/S9K5Zbdg2Jn7DyE0AhmVWC r+w7w6bjAlFSfnkYu3oA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG0D4-0007nu-NJ; Fri, 26 Oct 2018 11:23:22 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG06u-0003f4-HP for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 11:17:44 +0000 Received: by mail-wr1-x443.google.com with SMTP id y15-v6so929386wru.9 for ; Fri, 26 Oct 2018 04:16:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KZybGOtSAemy1CjzjcNF/ZknXxngxz/81lJVUnTVdE8=; b=kWGcJCGv3xOwk11103zPArswoi0cPmdmbZm1ViSXHChh9Qo5T/Z6SeKBDbXrR9d4AP nclyKjUSu4gfYYaD1Yj71yT6rjtmmZgdolSPItDRJaE8XUQpb19b9YJe+hQsSDxJXZom /D8QC4b9iSyyvX3Zl/3CPRgL6WdMUrXW+FV5ksGyCcs5zItg2KcUgX1F6oyp1lGMhclk GucwGwCEsEyem7dAMJ9D+maE/eK5UNEg473PMUswjMqJa/jnOmYcInmkJhJdt5ht81/j JJbkmWA2afTe6bX2LP61ita9AicvCNAhJwqClFbi9lVAq9XGMjWEmbDWuqbLeo5qgqXr NGRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KZybGOtSAemy1CjzjcNF/ZknXxngxz/81lJVUnTVdE8=; b=obNphj9ai5TQdkNc+5LLDj1ZXkCA6Zce3gBa6oX0fnpBjA04DRBHMGf5a6geNO55Mz 0B5rUeepOFhihKhDp12o0x/06IPk816tb4xJeF4n5T/4l/Q2ux/CrWZZSQQkDgo/k3P7 gNXekw7i29aYq0C1W9au6wSg9/fbls9NyU3HjQHK418DdRMHfh+iizckGIGtGAaJyz2f vhf1r1OxMqpnC3hPcu9lf0q/iYwJHtDsqxWu7OLW27ekYYQbT7tz5svtlShZnpBC+w8F YWx5a7Bp5Rzy/1OsD8m6MCWqwny7Yacf3qRTEiNwV7HlKJy+TuKa7hjZVJTM0fOju6s7 Rywg== X-Gm-Message-State: AGRZ1gLdicKe5PQaY6FTmuDCU8g7jo/l+DGreSzmaQ0KUBjErU+sadCc zH9Dr1JMl5c4rCPMr8PzK6E= X-Google-Smtp-Source: AJdET5dNejX/Bib3KP2Bb8i07vSUL2/JbOcZt0e9nw+F4rdAmrtfjtA0Z+82T+pKuyNeYEXle+9QMg== X-Received: by 2002:a5d:488a:: with SMTP id g10-v6mr5428331wrq.0.1540552608459; Fri, 26 Oct 2018 04:16:48 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id c2-v6sm8553496wrt.77.2018.10.26.04.16.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:47 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 4/9] mailbox: tegra-hsp: Add support for shared mailboxes Date: Fri, 26 Oct 2018 13:16:33 +0200 Message-Id: <20181026111638.10759-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041700_657287_39BDE3C3 X-CRM114-Status: GOOD ( 25.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding The Tegra HSP block supports 'shared mailboxes' that are simple 32-bit registers consisting of a FULL bit in MSB position and 31 bits of data. The hardware can be configured to trigger interrupts when a mailbox is empty or full. Add support for these shared mailboxes to the HSP driver. The initial use for the mailboxes is the Tegra Combined UART. For this purpose, we use interrupts to receive data, and spinning to wait for the transmit mailbox to be emptied to minimize unnecessary overhead. Based on work by Mikko Perttunen . Signed-off-by: Thierry Reding --- drivers/mailbox/tegra-hsp.c | 476 +++++++++++++++++++++++++++++++----- 1 file changed, 415 insertions(+), 61 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 0cde356c11ab..d070c8e38375 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -11,6 +11,7 @@ * more details. */ +#include #include #include #include @@ -21,6 +22,17 @@ #include +#include "mailbox.h" + +#define HSP_INT_IE(x) (0x100 + ((x) * 4)) +#define HSP_INT_IV 0x300 +#define HSP_INT_IR 0x304 + +#define HSP_INT_EMPTY_SHIFT 0 +#define HSP_INT_EMPTY_MASK 0xff +#define HSP_INT_FULL_SHIFT 8 +#define HSP_INT_FULL_MASK 0xff + #define HSP_INT_DIMENSIONING 0x380 #define HSP_nSM_SHIFT 0 #define HSP_nSS_SHIFT 4 @@ -34,6 +46,11 @@ #define HSP_DB_RAW 0x8 #define HSP_DB_PENDING 0xc +#define HSP_SM_SHRD_MBOX 0x0 +#define HSP_SM_SHRD_MBOX_FULL BIT(31) +#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 +#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 + #define HSP_DB_CCPLEX 1 #define HSP_DB_BPMP 3 #define HSP_DB_MAX 7 @@ -55,6 +72,12 @@ struct tegra_hsp_doorbell { unsigned int index; }; +struct tegra_hsp_mailbox { + struct tegra_hsp_channel channel; + unsigned int index; + bool sending; +}; + struct tegra_hsp_db_map { const char *name; unsigned int master; @@ -66,10 +89,13 @@ struct tegra_hsp_soc { }; struct tegra_hsp { + struct device *dev; const struct tegra_hsp_soc *soc; - struct mbox_controller mbox; + struct mbox_controller mbox_db; + struct mbox_controller mbox_sm; void __iomem *regs; - unsigned int irq; + unsigned int doorbell_irq; + unsigned int *shared_irqs; unsigned int num_sm; unsigned int num_as; unsigned int num_ss; @@ -78,14 +104,9 @@ struct tegra_hsp { spinlock_t lock; struct list_head doorbells; + struct tegra_hsp_mailbox *mailboxes; }; -static inline struct tegra_hsp * -to_tegra_hsp(struct mbox_controller *mbox) -{ - return container_of(mbox, struct tegra_hsp, mbox); -} - static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) { return readl(hsp->regs + offset); @@ -158,7 +179,7 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) spin_lock(&hsp->lock); - for_each_set_bit(master, &value, hsp->mbox.num_chans) { + for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { struct tegra_hsp_doorbell *db; db = __tegra_hsp_doorbell_get(hsp, master); @@ -182,6 +203,84 @@ static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t tegra_hsp_shared_full_irq(int irq, void *data) +{ + struct tegra_hsp *hsp = data; + unsigned long bit, mask; + u32 status, value; + void *msg; + + status = tegra_hsp_readl(hsp, HSP_INT_IR); + + /* only interested in FULL interrupts */ + mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; + + if (!mask) + return IRQ_NONE; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (!mb->sending) { + value = tegra_hsp_channel_readl(&mb->channel, + HSP_SM_SHRD_MBOX); + value &= ~HSP_SM_SHRD_MBOX_FULL; + msg = (void *)(unsigned long)value; + mbox_chan_received_data(mb->channel.chan, msg); + + /* + * Need to clear all bits here since some producers, + * such as TCU, depend on fields in the register + * getting cleared by the consumer. + * + * The mailbox API doesn't give the consumers a way + * of doing that explicitly, so we have to make sure + * we cover all possible cases. + */ + tegra_hsp_channel_writel(&mb->channel, 0x0, + HSP_SM_SHRD_MBOX); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t tegra_hsp_shared_empty_irq(int irq, void *data) +{ + struct tegra_hsp *hsp = data; + unsigned long bit, mask; + u32 status, value; + + status = tegra_hsp_readl(hsp, HSP_INT_IR); + + /* only interested in EMPTY interrupts */ + mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; + + if (!mask) + return IRQ_NONE; + + for_each_set_bit(bit, &mask, hsp->num_sm) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; + + if (mb->sending) { + /* + * Disable EMPTY interrupts until data is sent + * with the next message. These interrupts are + * level-triggered, so if we kept them enabled + * they would constantly trigger until we next + * write data into the message. + */ + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + mbox_chan_txdone(mb->channel.chan, 0); + } + } + + return IRQ_HANDLED; +} + static struct tegra_hsp_channel * tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, unsigned int master, unsigned int index) @@ -194,7 +293,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, if (!db) return ERR_PTR(-ENOMEM); - offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16; + offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; offset += index * 0x100; db->channel.regs = hsp->regs + offset; @@ -235,8 +334,8 @@ static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) unsigned long flags; u32 value; - if (db->master >= hsp->mbox.num_chans) { - dev_err(hsp->mbox.dev, + if (db->master >= chan->mbox->num_chans) { + dev_err(chan->mbox->dev, "invalid master ID %u for HSP channel\n", db->master); return -EINVAL; @@ -281,46 +380,147 @@ static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) spin_unlock_irqrestore(&hsp->lock, flags); } -static const struct mbox_chan_ops tegra_hsp_doorbell_ops = { +static const struct mbox_chan_ops tegra_hsp_db_ops = { .send_data = tegra_hsp_doorbell_send_data, .startup = tegra_hsp_doorbell_startup, .shutdown = tegra_hsp_doorbell_shutdown, }; -static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, +static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + mb->sending = true; + + /* copy data and mark mailbox full */ + value = (u32)(unsigned long)data; + value |= HSP_SM_SHRD_MBOX_FULL; + + tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX); + + if (!irqs_disabled()) { + /* enable EMPTY interrupt for the shared mailbox */ + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + } + + return 0; +} + +static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, + unsigned long timeout) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + u32 value; + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_before(jiffies, timeout)) { + value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); + if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { + mbox_chan_txdone(chan, 0); + return 0; + } + + udelay(1); + } + + return -ETIME; +} + +static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + chan->txdone_method = TXDONE_BY_IRQ; + + /* + * Shared mailboxes start out as consumers by default. FULL interrupts + * are coalesced at shared interrupt 0, while EMPTY interrupts will be + * coalesced at shared interrupt 1. + * + * Keep EMPTY interrupts disabled at startup and only enable them when + * the mailbox is actually full. This is required because the FULL and + * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts + * enabled all the time would cause an interrupt storm while mailboxes + * are idle. + */ + + value = tegra_hsp_readl(hsp, HSP_INT_IE(0)); + value |= BIT(HSP_INT_FULL_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(0)); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + tegra_hsp_channel_writel(ch, 0x1, HSP_SM_SHRD_MBOX_FULL_INT_IE); + tegra_hsp_channel_writel(ch, 0x1, HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + + return 0; +} + +static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) +{ + struct tegra_hsp_mailbox *mb = chan->con_priv; + struct tegra_hsp_channel *ch = &mb->channel; + struct tegra_hsp *hsp = mb->channel.hsp; + u32 value; + + tegra_hsp_channel_writel(ch, 0x0, HSP_SM_SHRD_MBOX_EMPTY_INT_IE); + tegra_hsp_channel_writel(ch, 0x0, HSP_SM_SHRD_MBOX_FULL_INT_IE); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(1)); + value &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(1)); + + value = tegra_hsp_readl(hsp, HSP_INT_IE(0)); + value &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); + tegra_hsp_writel(hsp, value, HSP_INT_IE(0)); +} + +static const struct mbox_chan_ops tegra_hsp_sm_ops = { + .send_data = tegra_hsp_mailbox_send_data, + .flush = tegra_hsp_mailbox_flush, + .startup = tegra_hsp_mailbox_startup, + .shutdown = tegra_hsp_mailbox_shutdown, +}; + +static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, const struct of_phandle_args *args) { + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); + unsigned int type = args->args[0], master = args->args[1]; struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); - struct tegra_hsp *hsp = to_tegra_hsp(mbox); - unsigned int type = args->args[0]; - unsigned int master = args->args[1]; struct tegra_hsp_doorbell *db; struct mbox_chan *chan; unsigned long flags; unsigned int i; - switch (type) { - case TEGRA_HSP_MBOX_TYPE_DB: - db = tegra_hsp_doorbell_get(hsp, master); - if (db) - channel = &db->channel; + if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) + return ERR_PTR(-ENODEV); - break; - - default: - break; - } + db = tegra_hsp_doorbell_get(hsp, master); + if (db) + channel = &db->channel; if (IS_ERR(channel)) return ERR_CAST(channel); spin_lock_irqsave(&hsp->lock, flags); - for (i = 0; i < hsp->mbox.num_chans; i++) { - chan = &hsp->mbox.chans[i]; + for (i = 0; i < mbox->num_chans; i++) { + chan = &mbox->chans[i]; if (!chan->con_priv) { - chan->con_priv = channel; channel->chan = chan; + chan->con_priv = db; break; } @@ -332,6 +532,19 @@ static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox, return chan ?: ERR_PTR(-EBUSY); } +static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *args) +{ + struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); + unsigned int type = args->args[0], index = args->args[1]; + + if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || + index >= hsp->num_sm) + return ERR_PTR(-ENODEV); + + return hsp->mailboxes[index].channel.chan; +} + static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp) { struct tegra_hsp_doorbell *db, *tmp; @@ -364,10 +577,72 @@ static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) return 0; } +static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) +{ + int i; + + hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), + GFP_KERNEL); + if (!hsp->mailboxes) + return -ENOMEM; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + mb->index = i; + mb->sending = false; + + mb->channel.hsp = hsp; + mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; + mb->channel.chan = &hsp->mbox_sm.chans[i]; + mb->channel.chan->con_priv = mb; + } + + return 0; +} + +static int tegra_hsp_request_shared_irqs(struct tegra_hsp *hsp) +{ + int err; + + if (hsp->shared_irqs[0] > 0) { + err = devm_request_irq(hsp->dev, hsp->shared_irqs[0], + tegra_hsp_shared_full_irq, 0, + dev_name(hsp->dev), hsp); + if (err < 0) { + dev_err(hsp->dev, + "failed to request full interrupt: %d\n", + err); + return err; + } + + dev_dbg(hsp->dev, "full interrupt requested: %u\n", + hsp->shared_irqs[0]); + } + + if (hsp->shared_irqs[1] > 0) { + err = devm_request_irq(hsp->dev, hsp->shared_irqs[1], + tegra_hsp_shared_empty_irq, 0, + dev_name(hsp->dev), hsp); + if (err < 0) { + dev_err(hsp->dev, + "failed to request empty interrupt: %d\n", + err); + return err; + } + + dev_dbg(hsp->dev, "empty interrupt requested: %u\n", + hsp->shared_irqs[1]); + } + + return 0; +} + static int tegra_hsp_probe(struct platform_device *pdev) { struct tegra_hsp *hsp; struct resource *res; + unsigned int i; u32 value; int err; @@ -375,6 +650,7 @@ static int tegra_hsp_probe(struct platform_device *pdev) if (!hsp) return -ENOMEM; + hsp->dev = &pdev->dev; hsp->soc = of_device_get_match_data(&pdev->dev); INIT_LIST_HEAD(&hsp->doorbells); spin_lock_init(&hsp->lock); @@ -392,58 +668,136 @@ static int tegra_hsp_probe(struct platform_device *pdev) hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; err = platform_get_irq_byname(pdev, "doorbell"); - if (err < 0) { - dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err); - return err; + if (err >= 0) + hsp->doorbell_irq = err; + + if (hsp->num_si > 0) { + unsigned int count = 0; + + hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, + sizeof(*hsp->shared_irqs), + GFP_KERNEL); + if (!hsp->shared_irqs) + return -ENOMEM; + + for (i = 0; i < hsp->num_si; i++) { + char *name; + + name = kasprintf(GFP_KERNEL, "shared%u", i); + if (!name) + return -ENOMEM; + + err = platform_get_irq_byname(pdev, name); + if (err >= 0) { + hsp->shared_irqs[i] = err; + count++; + } + + kfree(name); + } + + if (count == 0) { + devm_kfree(&pdev->dev, hsp->shared_irqs); + hsp->shared_irqs = NULL; + } } - hsp->irq = err; + /* setup the doorbell controller */ + hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; + hsp->mbox_db.num_chans = 32; + hsp->mbox_db.dev = &pdev->dev; + hsp->mbox_db.ops = &tegra_hsp_db_ops; - hsp->mbox.of_xlate = of_tegra_hsp_xlate; - hsp->mbox.num_chans = 32; - hsp->mbox.dev = &pdev->dev; - hsp->mbox.txdone_irq = false; - hsp->mbox.txdone_poll = false; - hsp->mbox.ops = &tegra_hsp_doorbell_ops; + hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, + sizeof(*hsp->mbox_db.chans), + GFP_KERNEL); + if (!hsp->mbox_db.chans) + return -ENOMEM; - hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans, - sizeof(*hsp->mbox.chans), - GFP_KERNEL); - if (!hsp->mbox.chans) + if (hsp->doorbell_irq) { + err = tegra_hsp_add_doorbells(hsp); + if (err < 0) { + dev_err(&pdev->dev, "failed to add doorbells: %d\n", + err); + return err; + } + } + + err = mbox_controller_register(&hsp->mbox_db); + if (err < 0) { + dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", err); + goto remove_doorbells; + } + + /* setup the shared mailbox controller */ + hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; + hsp->mbox_sm.num_chans = hsp->num_sm; + hsp->mbox_sm.dev = &pdev->dev; + hsp->mbox_sm.ops = &tegra_hsp_sm_ops; + + hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, + sizeof(*hsp->mbox_sm.chans), + GFP_KERNEL); + if (!hsp->mbox_sm.chans) return -ENOMEM; - err = tegra_hsp_add_doorbells(hsp); + if (hsp->shared_irqs) { + err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); + if (err < 0) { + dev_err(&pdev->dev, "failed to add mailboxes: %d\n", + err); + goto unregister_mbox_db; + } + } + + err = mbox_controller_register(&hsp->mbox_sm); if (err < 0) { - dev_err(&pdev->dev, "failed to add doorbells: %d\n", err); - return err; + dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", err); + goto unregister_mbox_db; } platform_set_drvdata(pdev, hsp); - err = mbox_controller_register(&hsp->mbox); - if (err) { - dev_err(&pdev->dev, "failed to register mailbox: %d\n", err); - tegra_hsp_remove_doorbells(hsp); - return err; + if (hsp->doorbell_irq) { + err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, + tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, + dev_name(&pdev->dev), hsp); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request doorbell IRQ#%u: %d\n", + hsp->doorbell_irq, err); + goto unregister_mbox_sm; + } } - err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq, - IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", - hsp->irq, err); - return err; + if (hsp->shared_irqs) { + err = tegra_hsp_request_shared_irqs(hsp); + if (err < 0) + goto unregister_mbox_sm; } return 0; + +unregister_mbox_sm: + mbox_controller_unregister(&hsp->mbox_sm); +unregister_mbox_db: + mbox_controller_unregister(&hsp->mbox_db); +remove_doorbells: + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); + + return err; } static int tegra_hsp_remove(struct platform_device *pdev) { struct tegra_hsp *hsp = platform_get_drvdata(pdev); - mbox_controller_unregister(&hsp->mbox); - tegra_hsp_remove_doorbells(hsp); + mbox_controller_unregister(&hsp->mbox_sm); + mbox_controller_unregister(&hsp->mbox_db); + + if (hsp->doorbell_irq) + tegra_hsp_remove_doorbells(hsp); return 0; } From patchwork Fri Oct 26 11:16:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10657249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2ED1109C for ; Fri, 26 Oct 2018 11:21:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F2C22BF69 for ; Fri, 26 Oct 2018 11:21:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 812692BFA4; Fri, 26 Oct 2018 11:21:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 071302BF69 for ; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id a2-v6sm1743870wmf.12.2018.10.26.04.16.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 5/9] mailbox: tegra-hsp: Add suspend/resume support Date: Fri, 26 Oct 2018 13:16:34 +0200 Message-Id: <20181026111638.10759-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041702_093178_65FBF4E1 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Upon resuming from a system sleep state, the interrupts for all active shared mailboxes need to be reenabled, otherwise they will not work. Signed-off-by: Thierry Reding --- drivers/mailbox/tegra-hsp.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index d070c8e38375..043f7173af8f 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -802,6 +803,23 @@ static int tegra_hsp_remove(struct platform_device *pdev) return 0; } +static int tegra_hsp_resume(struct device *dev) +{ + struct tegra_hsp *hsp = dev_get_drvdata(dev); + unsigned int i; + + for (i = 0; i < hsp->num_sm; i++) { + struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; + + if (mb->channel.chan->cl) + tegra_hsp_mailbox_startup(mb->channel.chan); + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume); + static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, @@ -821,6 +839,7 @@ static struct platform_driver tegra_hsp_driver = { .driver = { .name = "tegra-hsp", .of_match_table = tegra_hsp_match, + .pm = &tegra_hsp_pm_ops, }, .probe = tegra_hsp_probe, .remove = tegra_hsp_remove, From patchwork Fri Oct 26 11:16:35 2018 Content-Type: text/plain; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id q77-v6sm5757398wmd.33.2018.10.26.04.16.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 6/9] dt-bindings: serial: Add bindings for nvidia, tegra194-tcu Date: Fri, 26 Oct 2018 13:16:35 +0200 Message-Id: <20181026111638.10759-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041700_628862_9B387DF0 X-CRM114-Status: GOOD ( 15.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen Add bindings for the Tegra Combined UART device used to talk to the UART console on Tegra194 systems. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt new file mode 100644 index 000000000000..a8becf6efd2a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra Combined UART (TCU) + +The TCU is a system for sharing a hardware UART instance among multiple +systems within the Tegra SoC. It is implemented through a mailbox- +based protocol where each "virtual UART" has a pair of mailboxes, one +for transmitting and one for receiving, that is used to communicate +with the hardware implementing the TCU. + +Required properties: +- name : Should be tcu +- compatible + Array of strings + One of: + - "nvidia,tegra194-tcu" +- mbox-names: + "rx" - Mailbox for receiving data from hardware UART + "tx" - Mailbox for transmitting data to hardware UART +- mboxes: Mailboxes corresponding to the mbox-names. + +This node is a mailbox consumer. See the following files for details of +the mailbox subsystem, and the specifiers implemented by the relevant +provider(s): + +- .../mailbox/mailbox.txt +- .../mailbox/nvidia,tegra186-hsp.txt + +Example bindings: +----------------- + +tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; +}; From patchwork Fri Oct 26 11:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 10657253 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 85C7F14BD for ; Fri, 26 Oct 2018 11:22:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 718612BF9B for ; Fri, 26 Oct 2018 11:22:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 64BF32BFDA; Fri, 26 Oct 2018 11:22:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 639102BF9B for ; Fri, 26 Oct 2018 11:22:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nz5gWhCYaK/MV2rG8jKlhESfnFtp3m752CBTi5D/aYE=; b=sgnv/7l+9jTw+J 9fLXINBGhX0lXGkvkOimjcYPpwdIYUm3xEm1vLhX7jkbqZ41drE/YWQCrjeuhuS8weqjcxa2mrELZ Zz0GzyN8Lwq3ZKCkjjCd+iM54/SVT5BdfWmzzVfapWC0E2GYr7IJg5KW9/90WL+nz2jdQIA86qpXs BXxhM5cLN68vxKiGGY5u0klrQtwT1ETnZb5426vKFFhYxkVYRvi8X5+5gEJlORedcxsHhofGNVjt4 oyViLL8YKOytr7b8+nOo/uvk/2qwifi9NkxSullL1l0NOsDmSsctx4Z79xdnE1c5WKDhp/2WOpYSe 3/vd3MJfgKZrgYbH2H6Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG0CM-0007Sw-HX; Fri, 26 Oct 2018 11:22:38 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gG06v-0003fU-Vb for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 11:17:33 +0000 Received: by mail-wr1-x442.google.com with SMTP id n5-v6so918591wrw.12 for ; Fri, 26 Oct 2018 04:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t0SsqNzZTENUg3cef2avj+k6dlilGRNUZUBNqnDuQY8=; b=RY9+BIsrumY8ePdidBrujhUl2GfBZrj+XUj/pshWioPizS435NzMLIm+bSMPsF3Rnc Pugj6QgPDzReqgvBkwXILinJFp05pjDxAx+U2uHiTMFXqZSBou++Zr//7oE9ytgQciFd bl1F/fhuJQJ4F/kLJ6IAmuQdOBIHFKmDx3ptNjB24+OGUsCpVBobHxLswleumQpbcKq4 NyhOGtQhSSLTiqPNp30/gnOF7GYt3eZPb3gDJVgmlymf9wbF5ckqlFreuiiE1cpmAhHv SiwA+kC2TIGPvjEo3z3xgQ3J91ZU9WCGypva8J5t60setY5FiwhfnsP3gOyEvC+PUHqz Avhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t0SsqNzZTENUg3cef2avj+k6dlilGRNUZUBNqnDuQY8=; b=ijvjSQBqhQsGRF4z/8NuAuwIhWvZRxgZJlPnNwGfJwHVR/xgaZpQsRDID6cr8y4T04 lwtKccdZIImXFGDUA3Rcxav6ydPwXcpGlR4Kn/JxqElA7hSv6SZAMkAiqtkHlY/xsG5h vJ8HQBDXvlbUbw4DBj9CYj1w6tiVK3bK3I/pJuNzKcbFsu9EQa3qn/X6ShbgMShriAi2 /lWy5SIS+QbSAXfRH55WD5ujbWLibIOpd3etuC+gH2i7MIfnXKb23ival1+FzgWC6vQr bBD5bUEHyr9okTv52ms4cCVr/O6AcgH1zxzYZr9quj5buxuQblY8h0Rd6DRJgYoeKGIY 7k3Q== X-Gm-Message-State: AGRZ1gJVkE0x2pUjgyZGJ5KagB7uANQXyrWkloxvDl9ljUGAxI2+CFqH NZNlMUOLD6okhm81JWy2RXM= X-Google-Smtp-Source: AJdET5feOeZcPaKS2eIVrNMlwRa/X0gvfisQPWEgQsufsxoRWfud4mZc3DzMzfEtDNnDhF0JRVLxeg== X-Received: by 2002:a5d:620b:: with SMTP id y11-v6mr5216349wru.105.1540552613320; Fri, 26 Oct 2018 04:16:53 -0700 (PDT) Received: from localhost (pD9E511F8.dip0.t-ipconnect.de. [217.229.17.248]) by smtp.gmail.com with ESMTPSA id z185-v6sm6601402wmz.47.2018.10.26.04.16.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:52 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 7/9] serial: Add Tegra Combined UART driver Date: Fri, 26 Oct 2018 13:16:36 +0200 Message-Id: <20181026111638.10759-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041702_105166_8DFCA265 X-CRM114-Status: GOOD ( 24.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows multiplexing multiple "virtual UARTs" into a single hardware serial port. The TCU is the primary serial port on Tegra194 devices. Add a TCU driver utilizing the mailbox framework, as the used mailboxes are part of Tegra HSP blocks that are already controlled by the Tegra HSP mailbox driver. Based on work by Mikko Perttunen . Signed-off-by: Thierry Reding Acked-by: Greg Kroah-Hartman --- drivers/tty/serial/Kconfig | 22 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/tegra-tcu.c | 299 +++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 325 insertions(+) create mode 100644 drivers/tty/serial/tegra-tcu.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 32886c304641..785306388aa4 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -323,6 +323,28 @@ config SERIAL_TEGRA are enabled). This driver uses the APB DMA to achieve higher baudrate and better performance. +config SERIAL_TEGRA_TCU + tristate "NVIDIA Tegra Combined UART" + depends on ARCH_TEGRA && TEGRA_HSP_MBOX + select SERIAL_CORE + help + Support for the mailbox-based TCU (Tegra Combined UART) serial port. + TCU is a virtual serial port that allows multiplexing multiple data + streams into a single hardware serial port. + +config SERIAL_TEGRA_TCU_CONSOLE + bool "Support for console on a Tegra TCU serial port" + depends on SERIAL_TEGRA_TCU=y + select SERIAL_CORE_CONSOLE + default y + ---help--- + If you say Y here, it will be possible to use a the Tegra TCU as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + If unsure, say Y. + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index daac675612df..4ad82231ff8a 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o +obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o obj-$(CONFIG_SERIAL_ARC) += arc_uart.o diff --git a/drivers/tty/serial/tegra-tcu.c b/drivers/tty/serial/tegra-tcu.c new file mode 100644 index 000000000000..1d360cd03b18 --- /dev/null +++ b/drivers/tty/serial/tegra-tcu.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TCU_MBOX_BYTE(i, x) ((x) << (i * 8)) +#define TCU_MBOX_BYTE_V(x, i) (((x) >> (i * 8)) & 0xff) +#define TCU_MBOX_NUM_BYTES(x) ((x) << 24) +#define TCU_MBOX_NUM_BYTES_V(x) (((x) >> 24) & 0x3) + +struct tegra_tcu { + struct uart_driver driver; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + struct console console; +#endif + struct uart_port port; + + struct mbox_client tx_client, rx_client; + struct mbox_chan *tx, *rx; +}; + +static unsigned int tegra_tcu_uart_tx_empty(struct uart_port *port) +{ + return TIOCSER_TEMT; +} + +static void tegra_tcu_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int tegra_tcu_uart_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_stop_tx(struct uart_port *port) +{ +} + +static void tegra_tcu_write_one(struct tegra_tcu *tcu, u32 value, + unsigned int count) +{ + void *msg; + + value |= TCU_MBOX_NUM_BYTES(count); + msg = (void *)(unsigned long)value; + mbox_send_message(tcu->tx, msg); +} + +static void tegra_tcu_write(struct tegra_tcu *tcu, const char *s, + unsigned int count) +{ + unsigned int written = 0, i = 0; + bool insert_nl = false; + u32 value = 0; + + while (i < count) { + if (insert_nl) { + value |= TCU_MBOX_BYTE(written++, '\n'); + insert_nl = false; + i++; + } else if (s[i] == '\n') { + value |= TCU_MBOX_BYTE(written++, '\r'); + insert_nl = true; + } else { + value |= TCU_MBOX_BYTE(written++, s[i++]); + } + + if (written == 3) { + tegra_tcu_write_one(tcu, value, 3); + value = written = 0; + } + } + + if (written) + tegra_tcu_write_one(tcu, value, written); +} + +static void tegra_tcu_uart_start_tx(struct uart_port *port) +{ + struct tegra_tcu *tcu = port->private_data; + struct circ_buf *xmit = &port->state->xmit; + unsigned long count; + + for (;;) { + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + if (!count) + break; + + tegra_tcu_write(tcu, &xmit->buf[xmit->tail], count); + xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); + } + + uart_write_wakeup(port); +} + +static void tegra_tcu_uart_stop_rx(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_break_ctl(struct uart_port *port, int ctl) +{ +} + +static int tegra_tcu_uart_startup(struct uart_port *port) +{ + return 0; +} + +static void tegra_tcu_uart_shutdown(struct uart_port *port) +{ +} + +static void tegra_tcu_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ +} + +static const struct uart_ops tegra_tcu_uart_ops = { + .tx_empty = tegra_tcu_uart_tx_empty, + .set_mctrl = tegra_tcu_uart_set_mctrl, + .get_mctrl = tegra_tcu_uart_get_mctrl, + .stop_tx = tegra_tcu_uart_stop_tx, + .start_tx = tegra_tcu_uart_start_tx, + .stop_rx = tegra_tcu_uart_stop_rx, + .break_ctl = tegra_tcu_uart_break_ctl, + .startup = tegra_tcu_uart_startup, + .shutdown = tegra_tcu_uart_shutdown, + .set_termios = tegra_tcu_uart_set_termios, +}; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) +static void tegra_tcu_console_write(struct console *cons, const char *s, + unsigned int count) +{ + struct tegra_tcu *tcu = container_of(cons, struct tegra_tcu, console); + + tegra_tcu_write(tcu, s, count); +} + +static int tegra_tcu_console_setup(struct console *cons, char *options) +{ + return 0; +} +#endif + +static void tegra_tcu_receive(struct mbox_client *cl, void *msg) +{ + struct tegra_tcu *tcu = container_of(cl, struct tegra_tcu, rx_client); + struct tty_port *port = &tcu->port.state->port; + u32 value = (u32)(unsigned long)msg; + unsigned int num_bytes, i; + + num_bytes = TCU_MBOX_NUM_BYTES_V(value); + + for (i = 0; i < num_bytes; i++) + tty_insert_flip_char(port, TCU_MBOX_BYTE_V(value, i), + TTY_NORMAL); + + tty_flip_buffer_push(port); +} + +static int tegra_tcu_probe(struct platform_device *pdev) +{ + struct uart_port *port; + struct tegra_tcu *tcu; + int err; + + tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->tx_client.dev = &pdev->dev; + tcu->tx_client.tx_block = true; + tcu->tx_client.tx_tout = 10000; + tcu->rx_client.dev = &pdev->dev; + tcu->rx_client.rx_callback = tegra_tcu_receive; + + tcu->tx = mbox_request_channel_byname(&tcu->tx_client, "tx"); + if (IS_ERR(tcu->tx)) { + err = PTR_ERR(tcu->tx); + dev_err(&pdev->dev, "failed to get tx mailbox: %d\n", err); + return err; + } + + tcu->rx = mbox_request_channel_byname(&tcu->rx_client, "rx"); + if (IS_ERR(tcu->rx)) { + err = PTR_ERR(tcu->rx); + dev_err(&pdev->dev, "failed to get rx mailbox: %d\n", err); + goto free_tx; + } + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + /* setup the console */ + strcpy(tcu->console.name, "ttyTCU"); + tcu->console.device = uart_console_device; + tcu->console.flags = CON_PRINTBUFFER | CON_ANYTIME; + tcu->console.index = -1; + tcu->console.write = tegra_tcu_console_write; + tcu->console.setup = tegra_tcu_console_setup; + tcu->console.data = &tcu->driver; +#endif + + /* setup the driver */ + tcu->driver.owner = THIS_MODULE; + tcu->driver.driver_name = "tegra-tcu"; + tcu->driver.dev_name = "ttyTCU"; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + tcu->driver.cons = &tcu->console; +#endif + tcu->driver.nr = 1; + + err = uart_register_driver(&tcu->driver); + if (err) { + dev_err(&pdev->dev, "failed to register UART driver: %d\n", + err); + goto free_rx; + } + + /* setup the port */ + port = &tcu->port; + spin_lock_init(&port->lock); + port->dev = &pdev->dev; + port->type = PORT_TEGRA_TCU; + port->ops = &tegra_tcu_uart_ops; + port->fifosize = 1; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->private_data = tcu; + + err = uart_add_one_port(&tcu->driver, port); + if (err) { + dev_err(&pdev->dev, "failed to add UART port: %d\n", err); + goto unregister_uart; + } + + platform_set_drvdata(pdev, tcu); +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + register_console(&tcu->console); +#endif + + return 0; + +unregister_uart: + uart_unregister_driver(&tcu->driver); +free_rx: + mbox_free_channel(tcu->rx); +free_tx: + mbox_free_channel(tcu->tx); + + return err; +} + +static int tegra_tcu_remove(struct platform_device *pdev) +{ + struct tegra_tcu *tcu = platform_get_drvdata(pdev); + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE) + unregister_console(&tcu->console); +#endif + uart_remove_one_port(&tcu->driver, &tcu->port); + uart_unregister_driver(&tcu->driver); + mbox_free_channel(tcu->rx); + mbox_free_channel(tcu->tx); + + return 0; +} + +static const struct of_device_id tegra_tcu_match[] = { + { .compatible = "nvidia,tegra194-tcu" }, + { } +}; + +static struct platform_driver tegra_tcu_driver = { + .driver = { + .name = "tegra-tcu", + .of_match_table = tegra_tcu_match, + }, + .probe = tegra_tcu_probe, + .remove = tegra_tcu_remove, +}; +module_platform_driver(tegra_tcu_driver); + +MODULE_AUTHOR("Mikko Perttunen "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("NVIDIA Tegra Combined UART driver"); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index dce5f9dae121..69883c32cb98 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -79,6 +79,9 @@ /* Nuvoton UART */ #define PORT_NPCM 40 +/* NVIDIA Tegra Combined UART */ +#define PORT_TEGRA_TCU 41 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45 From patchwork Fri Oct 26 11:16:37 2018 Content-Type: text/plain; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id y195-v6sm4485038wme.22.2018.10.26.04.16.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:54 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 8/9] arm64: tegra: Add nodes for TCU on Tegra194 Date: Fri, 26 Oct 2018 13:16:37 +0200 Message-Id: <20181026111638.10759-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041656_856186_8AD6E7E2 X-CRM114-Status: GOOD ( 15.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..521d13be0457 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -340,10 +340,35 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + reg = <0x0c150000 0xa0000>; + interrupts = , + , + , + ; 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[217.229.17.248]) by smtp.gmail.com with ESMTPSA id c2-v6sm8553896wrt.77.2018.10.26.04.16.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Oct 2018 04:16:56 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Jassi Brar , Greg Kroah-Hartman Subject: [PATCH 9/9] arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 Date: Fri, 26 Oct 2018 13:16:38 +0200 Message-Id: <20181026111638.10759-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181026111638.10759-1-thierry.reding@gmail.com> References: <20181026111638.10759-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_041708_703384_AEBE89BE X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mika Liljeberg , Mikko Perttunen , Timo Alho , linux-serial@vger.kernel.org, Jiri Slaby , linux-tegra@vger.kernel.org, Pekka Pessi , Jon Hunter , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 57d3f00464ce..fcbe2a88f8db 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -10,7 +10,7 @@ aliases { sdhci0 = "/cbb/sdhci@3460000"; sdhci1 = "/cbb/sdhci@3400000"; - serial0 = &uartb; + serial0 = &tcu; i2c0 = "/bpmp/i2c"; i2c1 = "/cbb/i2c@3160000"; i2c2 = "/cbb/i2c@c240000";