From patchwork Tue Sep 22 10:12:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8A506CB for ; Tue, 22 Sep 2020 10:14:50 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A520238D6 for ; Tue, 22 Sep 2020 10:14:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Ot+Q1L56" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A520238D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/FTVdGO8vnQeFtFIejK+JPFBKXyj4aLROrqUJk7GkGU=; b=Ot+Q1L56YYV3vavje/TFsMimAh 4LT6CI0PAzHbCIsnyYDVkFZLJekGuHVdkaesaEgwPr4dUMPX2B4PGU8zVC30DEm8QKbfwsQVvFEa2 DpAil5ThOGciicujzc7S1UbKb++Nr2T8EGIZbQpuNt1dUVz9iACJp7y8RU7X7HV/i8wBtweEAq1GC plcLPaDWiQQ1JrGw05oWOoXCX0a8JEfF/CYaBQrkcqj8IUsDvGUXubcv45tb4oSZARHpRne/GENeC 6/hlA0duNTBmbd81xm63U2KC/5jZsm2xCOXHHPNe/vUX4JWS1Uu6W4qTZftv6JAzkvVwA99GjdKFW x58T2dmw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfI8-0006YM-SR; Tue, 22 Sep 2020 10:12:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfHs-0006T9-JL for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 10:12:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2168512FC; Tue, 22 Sep 2020 03:12:34 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 242653F718; Tue, 22 Sep 2020 03:12:32 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register Date: Tue, 22 Sep 2020 11:12:21 +0100 Message-Id: <20200922101225.183554-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061241_040282_9C89D505 X-CRM114-Status: GOOD ( 13.61 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARMv8.3-SPE extension adds some new bits for the event filter. Remove bits 11, 17 and 18 from the RES0 mask, so they can be used correctly. Signed-off-by: Andre Przywara --- arch/arm64/include/asm/sysreg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 554a7e8ecb07..efca4ee28671 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -281,7 +281,7 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL +#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00f90755UL #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 From patchwork Tue Sep 22 10:12:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1CD7618 for ; Tue, 22 Sep 2020 10:14:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79CC7238D6 for ; Tue, 22 Sep 2020 10:14:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QQcOZvPq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 79CC7238D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Ao+WFUAi52raSBwGmaahux1KJk+AowD9nFzUWvb4A2g=; b=QQcOZvPqs/tI4NOjUGukxxhWNf jebXiveEN/60QE4lFXSALy/1U7i4ogjQ9VEQuzRuEpj7RD4k6wAjUCY8O2LVbkpAPsztcBau66kqS 99daI66w2rzhmGJSnJ6igAxboMt/9IerKZEt65AXdSWQTBDDv8YxeItNHBloboXJHKJjBWbj2sxyr rN9KpYeZmwCVKCof+MT9rDUGAKxFkGjfP5o31GkmOn/KO8ahEv0v081f/Dj5rkmFcgbC6oyxpJ9pf DG0Vs0rr5bR3PzugavWJOZ8dj8A++4dXQitzHkK3bNhZdVt+Pq4ivYSswqtqhebRxvaojkj6Waeu1 +Hx+hHYQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfI3-0006XU-BD; Tue, 22 Sep 2020 10:12:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfHs-0006T7-JP for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 10:12:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52CEB1396; Tue, 22 Sep 2020 03:12:36 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 540E53F718; Tue, 22 Sep 2020 03:12:34 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 2/5] perf: arm_spe: Add new event packet bits Date: Tue, 22 Sep 2020 11:12:22 +0100 Message-Id: <20200922101225.183554-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061241_034414_AA033270 X-CRM114-Status: GOOD ( 12.08 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARMv8.3-SPE extension adds some new bits to the event packet fields. Handle bits 11 (alignment), 17 and 18 (SVE predication) when decoding the SPE buffer content. Signed-off-by: Andre Przywara --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index b94001b756c7..e633bb5b8e65 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -346,6 +346,23 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, buf += ret; blen -= ret; } + if (payload & BIT(11)) { + ret = snprintf(buf, buf_len, " ALIGNMENT"); + buf += ret; + blen -= ret; + } + } + if (idx > 2) { + if (payload & BIT(17)) { + ret = snprintf(buf, buf_len, " SVE-PARTIAL-PRED"); + buf += ret; + blen -= ret; + } + if (payload & BIT(18)) { + ret = snprintf(buf, buf_len, " SVE-EMPTY-PRED"); + buf += ret; + blen -= ret; + } } if (ret < 0) return ret; From patchwork Tue Sep 22 10:12:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81B7D618 for ; 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Tue, 22 Sep 2020 03:12:36 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 3/5] perf: arm_spe: Add nested virt event decoding Date: Tue, 22 Sep 2020 11:12:23 +0100 Message-Id: <20200922101225.183554-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061241_037695_96B84FED X-CRM114-Status: GOOD ( 12.38 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARMv8.4 nested virtualisation extension can redirect system register accesses to a memory page controlled by the hypervisor. The SPE profiling feature in newer implementations can tag those memory accesses accordingly. Add the bit pattern describing this load/store type, so that the perf tool can decode it properly. Signed-off-by: Andre Przywara --- tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index e633bb5b8e65..943e4155b246 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -398,6 +398,10 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, buf += ret; blen -= ret; } + } else if ((payload & 0xfe) == 0x30) { + ret = snprintf(buf, buf_len, " NV-SYSREG"); + buf += ret; + blen -= ret; } else if (payload & 0x4) { ret = snprintf(buf, buf_len, " SIMD-FP"); buf += ret; From patchwork Tue Sep 22 10:12:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1375B618 for ; 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Tue, 22 Sep 2020 03:12:38 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 4/5] perf: arm_spe: Decode memory tagging properties Date: Tue, 22 Sep 2020 11:12:24 +0100 Message-Id: <20200922101225.183554-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061241_375847_EBEF5D95 X-CRM114-Status: GOOD ( 13.12 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org When SPE records a physical address, it can additionally tag the event with information from the Memory Tagging architecture extension. Decode the two additional fields in the SPE event payload. Signed-off-by: Andre Przywara Reviewed-by: Leo Yan --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index 943e4155b246..a033f34846a6 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -8,13 +8,14 @@ #include #include #include +#include #include "arm-spe-pkt-decoder.h" -#define BIT(n) (1ULL << (n)) - #define NS_FLAG BIT(63) #define EL_FLAG (BIT(62) | BIT(61)) +#define CH_FLAG BIT(62) +#define PAT_FLAG GENMASK_ULL(59, 56) #define SPE_HEADER0_PAD 0x0 #define SPE_HEADER0_END 0x1 @@ -447,10 +448,16 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, return snprintf(buf, buf_len, "%s 0x%llx el%d ns=%d", (idx == 1) ? "TGT" : "PC", payload, el, ns); case 2: return snprintf(buf, buf_len, "VA 0x%llx", payload); - case 3: ns = !!(packet->payload & NS_FLAG); + case 3: { + int ch = !!(packet->payload & CH_FLAG); + int pat = (packet->payload & PAT_FLAG) >> 56; + + ns = !!(packet->payload & NS_FLAG); payload &= ~(0xffULL << 56); - return snprintf(buf, buf_len, "PA 0x%llx ns=%d", - payload, ns); + return snprintf(buf, buf_len, + "PA 0x%llx ns=%d ch=%d, pat=%x", + payload, ns, ch, pat); + } default: return 0; } case ARM_SPE_CONTEXT: From patchwork Tue Sep 22 10:12:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11792069 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A9B76CB for ; Tue, 22 Sep 2020 10:15:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4934238D6 for ; Tue, 22 Sep 2020 10:15:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vxdGBYBW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C4934238D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xxmRUhXLzw1pRcGcFzHQ1DIllI92a4B/Iu8/ByhOkGE=; b=vxdGBYBW7XGqgxWI61o/1Ys58k r7PidGsOxSp/7uIVGEFpjrlTL1IBo6cv+9ndwIJhxVfWlCHYfgOQjhsfLunWTM+Eo8gxEkwFrFbuy 0Hdu5KfIn8lSlR4tqcqfILrDSA/mAqen0t8AYJbhWsuMGK/OHkOxXkA19yA5dZuR9WEpFTYmdjfIj Ch5zGXQOxzuS5ZkqZJTpAwjKWTla2p1HfyyxcLw1v2+pV/6umpVDmK5HSzSfncT2PgaULzdRouWNT MTp+qFT+0Dmew6B8xWsiY4myXMuKbW1Inb4mY6aXGBYYbWbICIx9tjaLUXsdVTOIdGQgAF3/C2PuU e8ieRnzA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfIW-0006dL-1v; Tue, 22 Sep 2020 10:13:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfHw-0006Vb-A5 for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 10:12:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDD1613D5; Tue, 22 Sep 2020 03:12:42 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F03373F718; Tue, 22 Sep 2020 03:12:40 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 5/5] perf: arm_spe: Decode SVE events Date: Tue, 22 Sep 2020 11:12:25 +0100 Message-Id: <20200922101225.183554-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061245_732657_4A1FFCE5 X-CRM114-Status: GOOD ( 15.22 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Scalable Vector Extension (SVE) is an ARMv8 architecture extension that introduces very long vector operations (up to 2048 bits). The SPE profiling feature can tag SVE instructions with additional properties like predication or the effective vector length. Decode the new operation type bits in the SPE decoder to allow the perf tool to correctly report about SVE instructions. Signed-off-by: Andre Przywara --- .../arm-spe-decoder/arm-spe-pkt-decoder.c | 48 ++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index a033f34846a6..f0c369259554 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -372,8 +372,35 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, } case ARM_SPE_OP_TYPE: switch (idx) { - case 0: return snprintf(buf, buf_len, "%s", payload & 0x1 ? + case 0: { + size_t blen = buf_len; + + if ((payload & 0x89) == 0x08) { + ret = snprintf(buf, buf_len, "SVE"); + buf += ret; + blen -= ret; + if (payload & 0x2) + ret = snprintf(buf, buf_len, " FP"); + else + ret = snprintf(buf, buf_len, " INT"); + buf += ret; + blen -= ret; + if (payload & 0x4) { + ret = snprintf(buf, buf_len, " PRED"); + buf += ret; + blen -= ret; + } + /* Bits [7..4] encode the vector length */ + ret = snprintf(buf, buf_len, " EVLEN%d", + 32 << ((payload >> 4) & 0x7)); + buf += ret; + blen -= ret; + return buf_len - blen; + } + + return snprintf(buf, buf_len, "%s", payload & 0x1 ? "COND-SELECT" : "INSN-OTHER"); + } case 1: { size_t blen = buf_len; @@ -403,6 +430,25 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, ret = snprintf(buf, buf_len, " NV-SYSREG"); buf += ret; blen -= ret; + } else if ((payload & 0x0a) == 0x08) { + ret = snprintf(buf, buf_len, " SVE"); + buf += ret; + blen -= ret; + if (payload & 0x4) { + ret = snprintf(buf, buf_len, " PRED"); + buf += ret; + blen -= ret; + } + if (payload & 0x80) { + ret = snprintf(buf, buf_len, " SG"); + buf += ret; + blen -= ret; + } + /* Bits [7..4] encode the vector length */ + ret = snprintf(buf, buf_len, " EVLEN%d", + 32 << ((payload >> 4) & 0x7)); + buf += ret; + blen -= ret; } else if (payload & 0x4) { ret = snprintf(buf, buf_len, " SIMD-FP"); buf += ret;