From patchwork Tue Sep 22 13:47:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 11792587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A229112C for ; Tue, 22 Sep 2020 13:47:27 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 15B9C239A1; Tue, 22 Sep 2020 13:47:27 +0000 (UTC) Delivered-To: soc@kernel.org Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8D532395B; Tue, 22 Sep 2020 13:47:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nKggUnn5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8D532395B Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=tempfail smtp.mailfrom=nm@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08MDlNAS052939; Tue, 22 Sep 2020 08:47:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600782443; bh=fAyQZ7elzBl6I1cjgQaG39fhlMZO3dkZE9iUXTvmgfY=; h=Date:From:To:CC:Subject; b=nKggUnn5gXIYlojYovbvybfmxUP6uSq8VcfyaBhIb3XAupSL77Lp8gaBRR5B2KSot xryXq1Rp52izPLVK+IvXqz8/DziD8icUi+9oURzQfzOBFKhXi0j8AlZF7E1cIUCUVE tLUwgtXI/Ee23q2GmjLMVKO6Nyhw2KazlHmMxqq4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08MDlNho030940 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Sep 2020 08:47:23 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Sep 2020 08:47:23 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Sep 2020 08:47:22 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08MDlMG8111593; Tue, 22 Sep 2020 08:47:22 -0500 Date: Tue, 22 Sep 2020 08:47:22 -0500 From: Nishanth Menon List-Id: To: Olof Johansson , Arnd Bergmann , , CC: , , , Keerthy J , Suman Anna , Sekhar Nori , Kishon Vijay Abraham Israel Vijayponraj Subject: [GIT PULL] arm64: TI K3 DT updates for v5.10 Message-ID: <20200922134722.2y5kqxu4lghbwp5u@akan> MIME-Version: 1.0 Content-Disposition: inline User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi, Please pull the following for 5.10 cycle (had to base on 5.9-rc3 due to a bad dependency): - dts fixups for dtbs_check and W=2 build of dtbs, node names. - am654 adds crypto nodes and an erratum workaround for PCIe(down to Gen2) - j721e adds C66, C71 DSP and PCIe nodes The following changes since commit f75aef392f869018f78cfedf3c320a6b3fcfda6b: Linux 5.9-rc3 (2020-08-30 16:01:54 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git tags/ti-k3-dt-for-v5.10 for you to fetch changes up to 66db854b1f62dbee48ec7373f149fa30e4b3dd4e: arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances (2020-09-22 08:19:47 -0500) ---------------------------------------------------------------- Device tree updates towards 5.10-rc1 for TI K3 platform. ---------------------------------------------------------------- Keerthy (2): arm64: dts: ti: k3-am6: Add crypto accelarator node arm64: dts: ti: k3-j721e-main: Add crypto accelerator node Kishon Vijay Abraham I (2): arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances Nishanth Menon (8): arm64: dts: ti: k3-j721e: Use lower case hexadecimal arm64: dts: ti: k3-am65-main: Use lower case hexadecimal arm64: dts: ti: k3-am65*: Use generic gpio for node names arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names arm64: dts: ti: k3-*: Use generic pinctrl for node names arm64: dts: ti: k3-am65-base-board Use generic camera for node name instead of ov5640 arm64: dts: ti: k3-am65-wakeup: Use generic temperature-sensor for node name arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings Sekhar Nori (1): arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed Suman Anna (10): arm64: dts: ti: k3-am65: Fix interconnect node names arm64: dts: ti: k3-j721e: Fix interconnect node names arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs arm64: dts: ti: k3-j721e-main: Add C71x DSP node arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52 +++- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 +- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 +- arch/arm64/boot/dts/ti/k3-am65.dtsi | 6 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 18 +- .../boot/dts/ti/k3-am654-industrial-thermal.dtsi | 12 +- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 191 ++++++------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 301 ++++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 +- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 155 ++++++++++- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 11 +- 11 files changed, 608 insertions(+), 152 deletions(-)