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Date: Wed, 23 Sep 2020 20:34:27 +0200 Message-ID: <20200923183427.9258-1-nadeem@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40c891d3-2eac-4b92-6a50-08d85fef522a X-MS-TrafficTypeDiagnostic: DM6PR07MB6233: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DqbbvMx0/8R19szloqOzmE5fkKWLoTg/KXHLNLNKiZmCy7Bm8jHtnVWTLnjLlR665DteB8UMMedncfqDGNLxJV5zAowmoThaqsEEEbYOgy6iqv4gASp9WbgeoPIMKbYPtUJHjYfgmY+fGgVCnTplVdb61Ts7qQDAcp5QndtOy6UlnEQODJbmTH3wUdt8X8D+gfD8Z/Uh2i2CG8AoNL93JSM7+Vmg2Vo51RGtDgkzB3CZdG3kPL4VqfpHcPvHVbF2q/DVAQiGW8eSqxnjTC1RWaRAs/zXjhSGaLeaPw0nCu2EYfL7CF6dx20QnbpJsjQ0vQzmkU6h4UnM64snhwZlnPBDkIJLxvKJiziKSp2QTBzWWYzBaHLSCMasoB4jvWmgzs784SprAr72JRcBbuMqXHjU8de9LDJEmVACKoPpVwV8t2cIPxQa65c8YqqUqwrd35wjSrYOeLgIaf+IkBfmViSbGBBwgBJSIkvVzsHgGAk= X-Forefront-Antispam-Report: CIP:199.43.4.23;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:rmmaillnx1.cadence.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(346002)(376002)(136003)(39860400002)(396003)(36092001)(46966005)(70586007)(42186006)(82310400003)(110136005)(4326008)(107886003)(54906003)(316002)(1076003)(2906002)(36756003)(478600001)(8936002)(6666004)(2616005)(70206006)(36906005)(26005)(186003)(5660300002)(426003)(86362001)(336012)(47076004)(82740400003)(81166007)(356005)(83380400001)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2020 18:34:35.2539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40c891d3-2eac-4b92-6a50-08d85fef522a X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9;Ip=[199.43.4.23];Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM12FT030.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6233 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-23_13:2020-09-23,2020-09-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 impostorscore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 adultscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009230139 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain bit is set as a quirk to trigger this speed change. Signed-off-by: Nadeem Athani --- drivers/pci/controller/cadence/pcie-cadence-host.c | 14 ++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 15 +++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 4550e0d469ca..a2317614268d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -83,6 +83,9 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) struct cdns_pcie *pcie = &rc->pcie; u32 value, ctrl; u32 id; + u32 link_cap = CDNS_PCIE_LINK_CAP_OFFSET; + u8 sls; + u16 lnk_ctl; /* * Set the root complex BAR configuration register: @@ -111,6 +114,17 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) if (rc->device_id != 0xffff) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); + /* Quirk to enable autonomous speed change for GEN2 controller */ + /* Reading Supported Link Speed value */ + sls = PCI_EXP_LNKCAP_SLS & + cdns_pcie_rp_readb(pcie, link_cap + PCI_EXP_LNKCAP); + if (sls == PCI_EXP_LNKCAP_SLS_5_0GB) { + /* Since this a Gen2 controller, set Retrain Link(RL) bit */ + lnk_ctl = cdns_pcie_rp_readw(pcie, link_cap + PCI_EXP_LNKCTL); + lnk_ctl |= PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, link_cap + PCI_EXP_LNKCTL, lnk_ctl); + } + cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0); cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index feed1e3038f4..fe560480c573 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -120,6 +120,7 @@ */ #define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_LINK_CAP_OFFSET 0xC0 /* * Address Translation Registers @@ -413,6 +414,20 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, cdns_pcie_write_sz(addr, 0x2, value); } +static inline u8 cdns_pcie_rp_readb(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x1); +} + +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value)