From patchwork Sat Sep 26 12:51:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801321 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AF21618 for ; Sat, 26 Sep 2020 12:52:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D85522211 for ; Sat, 26 Sep 2020 12:52:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RbjddDmE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729383AbgIZMv5 (ORCPT ); Sat, 26 Sep 2020 08:51:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726183AbgIZMv4 (ORCPT ); Sat, 26 Sep 2020 08:51:56 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E5BFC0613CE; Sat, 26 Sep 2020 05:51:56 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id q9so1936264wmj.2; Sat, 26 Sep 2020 05:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WtnGFz89R34zMewLz4xKY9RsBgKhUDP7y7BnbgJVIuk=; b=RbjddDmEq2v1dCLPsdcA1GlQymeCxffB55PzVyb6bDVA+C7qnVykp3AfY4/uvWhfu8 nHD4oQR1bMSE6FUzeckQnT+VzZT3tEO1w3q/RosnrURt3SDmrQdoN+v9VcBaIr/V8hUj BQCOVymTMNacNO+hdE5GKTGbJHSF1Ojz7Vxk94vPMe0TGUouJxYppjsQXDshMybVdYMt 1AlZpH5tMmWt8P2vTZxkBEUx4xzaSAAErXSxehvwqi+6LxBrY483/gZYfei8MpKOOPxn Q9lHdfGf44okhdLfNWQznOZIykrsKn2s2hHvXfdbUZMa4CzzQjjljo8Sgl3ygzTYTNmT DfIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WtnGFz89R34zMewLz4xKY9RsBgKhUDP7y7BnbgJVIuk=; b=jkBvxk1oMjAyP9t35gyZNyoHx5ih/VDkbPpoKQTXoWYPIqaawsyiEPdBZmGqhEICFi onwz5gaqnch6+PR8RqH2r+Zn2918HwAK8xWopxoOYvx+FfMCb0hRRJEF0jNp0oldBnRn 08x0yAro2az02MVWSnxZLwtf0LAdCZFoq2Co4RKX3vdhzyR1xuhwl5WsisG62riKWsdM 9g7GlbBAojkU8ad359raJD93pvERnXIXUspRmPr0M2JRsFQL02vvYeuruOWy2r3NzSKr s63G/Tg/3aKfz7KPDy5L7WK3VNxQn/rY2icPMKgZlguEAiri6Ot6XF7q9DTn9GyjKmAx Hppg== X-Gm-Message-State: AOAM533QUG65TQBGU5BP0fJxPSEkjF4e792unwMtZD6pp1TmLvuXS4k4 Za5V+XNbE2x13e0xMB/vMQU= X-Google-Smtp-Source: ABdhPJztqPYuaxUqhiJHnlgspPDWDKt+SSYEyAxLwzTILjR/AIFGICR1CkT656KMnZk6HY1AdKTS0g== X-Received: by 2002:a1c:6254:: with SMTP id w81mr2444847wmb.94.1601124714991; Sat, 26 Sep 2020 05:51:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:51:54 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register Date: Sat, 26 Sep 2020 14:51:40 +0200 Message-Id: <20200926125146.12859-2-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets programmed to some different values on a per-model basis. At least, this is what we intend to do here; Unfortunately, though, this register is being overwritten with a static magic number, right after applying the GPU-specific configuration (including the GPU-specific quirks) and that is effectively nullifying the efforts. Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL register in order to retain the wanted configuration for the target GPU. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 91726da82ed6..6262603e6e2e 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -594,8 +594,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); - /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); From patchwork Sat Sep 26 12:51:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801333 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3679618 for ; Sat, 26 Sep 2020 12:52:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9E80221EA for ; Sat, 26 Sep 2020 12:52:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iUl9jLvl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729486AbgIZMwT (ORCPT ); Sat, 26 Sep 2020 08:52:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729399AbgIZMv5 (ORCPT ); Sat, 26 Sep 2020 08:51:57 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60A34C0613CE; Sat, 26 Sep 2020 05:51:57 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id e2so2108558wme.1; Sat, 26 Sep 2020 05:51:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b1cxEWVtTchv9LulFIq5cTpW0TIwhYIam0Ax8XR7gpQ=; b=iUl9jLvlfWcKeH+Yw4X0PQOfTIudyWMz0fQTsHxVRomHClbQEjXWjpweVcW1W0AQaR QKyIEKdtaYwQeMM6nkSOcBETwg1sKbFfvi4YELIVMlnoAdGPyrntjn59raMcHUuR1HC5 xFEJcKonKy7Zx030gD7d6U8pvViEbYLuTWOBrt0bxwajBHMPCVWe6NoWwPBcbbEF6Q0O SWYUysbXgPlXQ2wMHfFiqVYoY2H6Fp4sJkC8d74vbFhWaVmHSu7/z/i4u10ClqrZZfCU vpTktjziitJfehmosT7Dy+RR6nCcqHz7rrh7t4/24qvDOZebHEBtg6egU26ckjKSDiS5 XJJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b1cxEWVtTchv9LulFIq5cTpW0TIwhYIam0Ax8XR7gpQ=; b=jx6xSLhF2gwUySVyjSqqKnGmpPH0UomYIGCxPUWuS9KrGrBHq9QqDYB1+drt359S1a mJgmZygGPdTXKomnCQzfJGFuJdjiO0lrTDh42NKKhRyxIx0kxdNyVY4OYOznon0z2lf5 x6lPA6zkVnxJC6AV4v940G+/TUZuD+/vcxY5xsEhs2R8+yRTS0fyIzdbLpfOvqTOPWdz PCBhdNaUxcA7yt6SwjBvODh6RePYOxlHd6XpZFwLoSN/d8274CFMAl3OdLSnDUKK7EP0 I6w4u3hZSOwNNwegEuWtbhHq+XBYCZxUDcoMvLaeJfo3T1p8YY54wFzOWZztH0EeMSo/ 477Q== X-Gm-Message-State: AOAM530QXr8XZoKl5KYBxlWy/TV5HocfeE1BUTj06pzlxbaaiDNPchjA YnoA0c6xL7VmYCgmKPR+W+Y= X-Google-Smtp-Source: ABdhPJy7la5lEzdeHF2t0BlcyTOiYk2AU/h/MX3uOvPeWKgvVLnOfRYQMeImquyCmu1XpVvVYIliiw== X-Received: by 2002:a1c:4455:: with SMTP id r82mr2498441wma.60.1601124716004; Sat, 26 Sep 2020 05:51:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:51:55 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch Date: Sat, 26 Sep 2020 14:51:41 +0200 Message-Id: <20200926125146.12859-3-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno The "main" if branch where we program the other regsiters for the Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL register programming because this has logical similarity differences from all the others. A later commit will show the entire sense of this. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 6262603e6e2e..f98f0844838c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -577,8 +577,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, - (0x200 << 11 | 0x200 << 22)); } else { gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); if (adreno_is_a530(adreno_gpu)) @@ -587,9 +585,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); + } + + if (adreno_is_a510(adreno_gpu)) + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x200 << 11 | 0x200 << 22)); + else gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); - } if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); From patchwork Sat Sep 26 12:51:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFF41618 for ; Sat, 26 Sep 2020 12:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9605221EC for ; Sat, 26 Sep 2020 12:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jg+IYhvv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729469AbgIZMwD (ORCPT ); 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Sat, 26 Sep 2020 05:51:56 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs Date: Sat, 26 Sep 2020 14:51:42 +0200 Message-Id: <20200926125146.12859-4-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno The Adreno 508/509/512 GPUs are stripped versions of the Adreno 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and SDA variants; these SoCs are usually provided with ZAP firmwares, but they have no available GPMU. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Martin Botka Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 172 ++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a5xx_power.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 60 +++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 15 ++ 4 files changed, 231 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f98f0844838c..9bcbf6cd5a28 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -212,7 +212,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, a5xx_preempt_trigger(gpu); } -static const struct { +static const struct adreno_five_hwcg_regs { u32 offset; u32 value; } a5xx_hwcg[] = { @@ -308,16 +308,124 @@ static const struct { {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222} +}, a50x_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, +}, a512_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, }; void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - unsigned int i; + const struct adreno_five_hwcg_regs *regs; + unsigned int i, sz; + + if (adreno_is_a508(adreno_gpu)) { + regs = a50x_hwcg; + sz = ARRAY_SIZE(a50x_hwcg); + } else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) { + regs = a512_hwcg; + sz = ARRAY_SIZE(a512_hwcg); + } else { + regs = a5xx_hwcg; + sz = ARRAY_SIZE(a5xx_hwcg); + } - for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++) - gpu_write(gpu, a5xx_hwcg[i].offset, - state ? a5xx_hwcg[i].value : 0); + for (i = 0; i < sz; i++) + gpu_write(gpu, regs[i].offset, + state ? regs[i].value : 0); if (adreno_is_a540(adreno_gpu)) { gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); @@ -506,11 +614,13 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) static int a5xx_hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u32 bit; int ret; gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); - if (adreno_is_a540(adreno_gpu)) + if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a540(adreno_gpu)) gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); /* Make all blocks contribute to the GPU BUSY perf counter */ @@ -572,22 +682,29 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 0x00100000 + adreno_gpu->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); - if (adreno_is_a510(adreno_gpu)) { + if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) { gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); - gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); + if (adreno_is_a508(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); + else + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); } else { gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); if (adreno_is_a530(adreno_gpu)) gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); - if (adreno_is_a540(adreno_gpu)) + else gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); } - if (adreno_is_a510(adreno_gpu)) + if (adreno_is_a508(adreno_gpu)) + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, + (0x100 << 11 | 0x100 << 22)); + else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) || + adreno_is_a512(adreno_gpu)) gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x200 << 11 | 0x200 << 22)); else @@ -597,6 +714,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); + /* + * Disable the RB sampler datapath DP2 clock gating optimization + * for 1-SP GPUs, as it is enabled by default. + */ + if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a512(adreno_gpu)) + gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); @@ -622,10 +747,17 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); /* Set the highest bank bit */ - gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7); - gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1); if (adreno_is_a540(adreno_gpu)) - gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2); + bit = 2; + else + bit = 1; + + gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, bit << 7); + gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, bit << 1); + + if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a540(adreno_gpu)) + gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, bit); /* Protect registers from the CP */ gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); @@ -662,7 +794,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); - if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu)) + if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) || + adreno_is_a530(adreno_gpu)) gpu_write(gpu, REG_A5XX_CP_PROTECT(17), ADRENO_PROTECT_RW(0x10000, 0x8000)); @@ -704,7 +838,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (ret) return ret; - if (!adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) || + adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu))) a5xx_gpmu_ucode_init(gpu); ret = a5xx_ucode_init(gpu); @@ -1117,7 +1252,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) if (ret) return ret; - if (adreno_is_a510(adreno_gpu)) { + /* Adreno 508, 509, 510, 512 needs manual RBBM sus/res control */ + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) { /* Halt the sp_input_clk at HM level */ gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); a5xx_set_hwcg(gpu, true); @@ -1157,8 +1293,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); u32 mask = 0xf; - /* A510 has 3 XIN ports in VBIF */ - if (adreno_is_a510(adreno_gpu)) + /* A508, A510 have 3 XIN ports in VBIF */ + if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) mask = 0x7; /* Clear the VBIF pipe before shutting down */ diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 321a8061fd32..31c45ae6875e 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -298,7 +298,7 @@ int a5xx_power_init(struct msm_gpu *gpu) int ret; /* Not all A5xx chips have a GPMU */ - if (adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) return 0; /* Set up the limits management */ @@ -330,7 +330,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) unsigned int *data, *ptr, *cmds; unsigned int cmds_size; - if (adreno_is_a510(adreno_gpu)) + if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) return; if (a5xx_gpu->gpmu_bo) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9eeb46bf2a5d..40465b4e9da8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -129,6 +129,41 @@ static const struct adreno_info gpulist[] = { .gmem = (SZ_1M + SZ_512K), .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .revn = 508, + .name = "A508", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a508_zap.mdt", + }, { + .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .revn = 509, + .name = "A509", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + /* Adreno 509 uses the same ZAP as 512 */ + .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, @@ -144,6 +179,23 @@ static const struct adreno_info gpulist[] = { */ .inactive_period = 250, .init = a5xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .revn = 512, + .name = "A512", + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, @@ -240,6 +292,14 @@ MODULE_FIRMWARE("qcom/a330_pm4.fw"); MODULE_FIRMWARE("qcom/a330_pfp.fw"); MODULE_FIRMWARE("qcom/a420_pm4.fw"); MODULE_FIRMWARE("qcom/a420_pfp.fw"); +MODULE_FIRMWARE("qcom/a508_zap.mdt"); +MODULE_FIRMWARE("qcom/a508_zap.b00"); +MODULE_FIRMWARE("qcom/a508_zap.b01"); +MODULE_FIRMWARE("qcom/a508_zap.b02"); +MODULE_FIRMWARE("qcom/a512_zap.mdt"); +MODULE_FIRMWARE("qcom/a512_zap.b00"); +MODULE_FIRMWARE("qcom/a512_zap.b01"); +MODULE_FIRMWARE("qcom/a512_zap.b02"); MODULE_FIRMWARE("qcom/a530_pm4.fw"); MODULE_FIRMWARE("qcom/a530_pfp.fw"); MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e55abae365b5..61d86a52e6ea 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -227,11 +227,26 @@ static inline int adreno_is_a430(struct adreno_gpu *gpu) return gpu->revn == 430; } +static inline int adreno_is_a508(struct adreno_gpu *gpu) +{ + return gpu->revn == 508; +} + +static inline int adreno_is_a509(struct adreno_gpu *gpu) +{ + return gpu->revn == 509; +} + static inline int adreno_is_a510(struct adreno_gpu *gpu) { return gpu->revn == 510; } +static inline int adreno_is_a512(struct adreno_gpu *gpu) +{ + return gpu->revn == 512; +} + static inline int adreno_is_a530(struct adreno_gpu *gpu) { return gpu->revn == 530; From patchwork Sat Sep 26 12:51:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46A6C112E for ; Sat, 26 Sep 2020 12:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B02D22204 for ; Sat, 26 Sep 2020 12:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IzmQm6Xb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729480AbgIZMwD (ORCPT ); Sat, 26 Sep 2020 08:52:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35118 "EHLO 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(PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.51.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:51:57 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530 Date: Sat, 26 Sep 2020 14:51:43 +0200 Message-Id: <20200926125146.12859-5-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Resetting the VBIF before power collapse is done to avoid getting bogus FIFO entries during the suspend sequence or subsequent resume, but this is doable only on Adreno 510 and Adreno 530, as the other units will tendentially lock up. Especially on Adreno 508, the GPU will show lockups and very bad slownesses after processing the first frame. Avoiding to execute the RBBM SW Reset before suspend will stop the lockup issue from happening on at least Adreno 508/509/512. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 9bcbf6cd5a28..00df5de3c8e3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1306,10 +1306,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) /* * Reset the VBIF before power collapse to avoid issue with FIFO - * entries + * entries on Adreno A510 and A530 (the others will tend to lock up) */ - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) { + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + } return msm_gpu_pm_suspend(gpu); } From patchwork Sat Sep 26 12:51:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801329 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBBF5112E for ; Sat, 26 Sep 2020 12:52:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CFA41221ED for ; Sat, 26 Sep 2020 12:52:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FCm0rhLw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729445AbgIZMwC (ORCPT ); Sat, 26 Sep 2020 08:52:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729391AbgIZMwB (ORCPT ); Sat, 26 Sep 2020 08:52:01 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 969FBC0613D5; Sat, 26 Sep 2020 05:52:00 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id s12so6820252wrw.11; Sat, 26 Sep 2020 05:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ScwFgjf4CVFLL0QbktoshjK86UH6jL1pgVGi1tkj42M=; b=FCm0rhLweV4v32CvpTVH22mVrlTllzq3je8W8VDTa7EwNOCixcG+mM6SoFBejJ4VnP 6jIINolttCNWgAhQxEvNE5kMtet6duC+LkCoOhgyN8XtXQjcQ1qhurpJHEgulFtln4XD /JQ5GMSFBIeUxS28yJLRp3qzyjALaujMXWJW8oO8vyI1NKEmCjY6YbJ9Wfv1sYUdSdA1 MxFieGfCBIaWcXwAdHQnO1a88HlaA5qol3fTTOm3eCTyZfAIRPuVX/nFYiYfvEQ1TvbZ +CJyFxzVk7/jiR/5p16X2SVQQImY8+I3Pp0EdojZTsZKTgwgpEtCSw8EodOmNyJuwh99 qdnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ScwFgjf4CVFLL0QbktoshjK86UH6jL1pgVGi1tkj42M=; b=gTVTnMc8RY4CyCD+z3y5qs1ExbVnw6ZvC59KK+yj0JyjSKYQ6rHpSiS549YnJsIKHB VtaIb+0UxbZ3TbWiVmjMCOPDKo3YbqXHJyThvIppkQtQ81TnYPYgZezug+CEGykKiXnQ PReUZp/b0FblMkLAGpouuABoIirObIi6ZCk7W3IGDmSZo39ZiXCMId0RFfpHcE/yCeik T947Hfuz7D0nw0dUWFs+s7UapKJ6tBXiTD1r/Sg8TF7YYyjcN9Abmt6rAznSL5YZ2NFv YtrQnK1MnZt5nXtbN7JEfUeb0Z4ukUQe59uIWg/xhksqnEBYVwupkIj9TXqzg3txIZqo g4Jw== X-Gm-Message-State: AOAM5304qu25aoTsfYJlXStpPRrKs2M1w+zZqIjUq5ut0JpcNfR5IFVK YIgko7u2ulSxBrVcGvstJws= X-Google-Smtp-Source: ABdhPJwRsAcaiieSYbXlX01tJPbMNfAAj8VCdZihppRjta/A7uJCVk3jfoMBRnSfNtoMf7RIQuNDWg== X-Received: by 2002:adf:f80a:: with SMTP id s10mr9908215wrp.351.1601124719194; Sat, 26 Sep 2020 05:51:59 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:51:58 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write() Date: Sat, 26 Sep 2020 14:51:44 +0200 Message-Id: <20200926125146.12859-6-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio The upstream API for some reason uses logbase2 instead of just passing the argument as-is, whereas downstream CAF kernel does the latter. Hence, a mistake has been made when porting: 4 is the value that's supposed to be passed, but log2(4) = 2. Changing the value to 16 (= 2^4) fixes the issue. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 00df5de3c8e3..b2670af638a3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -789,7 +789,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* VPC */ gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); From patchwork Sat Sep 26 12:51:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F7A8618 for ; Sat, 26 Sep 2020 12:52:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4649C2080C for ; Sat, 26 Sep 2020 12:52:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="izIYuruD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729434AbgIZMwC (ORCPT ); Sat, 26 Sep 2020 08:52:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729425AbgIZMwB (ORCPT ); Sat, 26 Sep 2020 08:52:01 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91B2EC0613D6; Sat, 26 Sep 2020 05:52:01 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id c18so6823908wrm.9; Sat, 26 Sep 2020 05:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffJxais4qGP0gvCu5GJ1ov8h/Ob+gH0ZybsxZFb8CJU=; b=izIYuruDFNqXltczjPsA76PTw+n862sTor1TddTJvNUgDDa2BvRL9Vzs1uzG5NOhTM XoSUS6FGEBarLJWx/a+UBeNjt0X7+XqzUZ6CQrW0tF1uTTrfFHRg93otdCE1Gl0SVzbO SKLCRHJujWHhSuPVTpjE/nfqWcrHs+1ijjGxJ4gdBfZIhBty8Lt1wjH9TGS8hq7NIMu5 xh8+1vVgqorRd8aW40KfrnAsviUQ3DSjh5+R4CR1pBd/oG2d+DyevmFHrX2/2XgmljIH b6QEB8NsrIE0VAnMIQniDcWcUGNrAQTY6b9pCC4NjAfSmMAkz2COsWcUHU23C7N0gE8w suqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffJxais4qGP0gvCu5GJ1ov8h/Ob+gH0ZybsxZFb8CJU=; b=leK7Fjrel6KRJ6hoKdN5o94IuD45HWBpje4sOD8E4WDchyDc97pIxR+b6KKiK9f/om L5mWzZ3QvZwaTrX06dR7Dj9/q0ZmxKgVnwgFV3KxlacfHBx30hC13qU4ZYhmTHFV9/nS 0eLcy8yNciWlw1gpCOWTn1Y4SRFutMdTA4rhjCGvS/MHU28c4CnUhaUd95qZ9ISraTpe 3vT+gG8n/HnAYQdxmPhTLLwe2mhPga+uj0CLvL+yDCMFOlmI4VAQWSMwGNJ9Na/K6BvW jcr7SE6Xqpki9W6wIjtggLGqIxn5WzUbP29zOquJY5bUlkKnulW0x6MghQVwpyKIOZTo j9mg== X-Gm-Message-State: AOAM531YtHGGyvjFvYnDO4ZrJ1wLaSaloW0yibnxPgbnqbIV0XvseM8z Bq1eug+weoS/fpWFmCnLOQHh1hoCUqIapg== X-Google-Smtp-Source: ABdhPJzeh/cPOy171Ct8PCqoVlJxp4O7WFQ7ahtAhPDNX1aSK65lu0g3sgP+HxnGbJxVLw9sVIPkPw== X-Received: by 2002:a05:6000:12c3:: with SMTP id l3mr9997979wrx.164.1601124720185; Sat, 26 Sep 2020 05:52:00 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:51:59 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] drm/msm/a5xx: Disable flat shading optimization Date: Sat, 26 Sep 2020 14:51:45 +0200 Message-Id: <20200926125146.12859-7-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index b2670af638a3..bdc852e7d979 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -759,6 +759,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a540(adreno_gpu)) gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, bit); + /* Disable All flat shading optimization */ + gpu_rmw(gpu, 0x00000E60, 0, 0x1 << 10); + /* Protect registers from the CP */ gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); From patchwork Sat Sep 26 12:51:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A43FB112E for ; Sat, 26 Sep 2020 12:52:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8836B20BED for ; Sat, 26 Sep 2020 12:52:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HZ5zxkP2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729574AbgIZMwO (ORCPT ); Sat, 26 Sep 2020 08:52:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729448AbgIZMwD (ORCPT ); Sat, 26 Sep 2020 08:52:03 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D7B5C0613CE; Sat, 26 Sep 2020 05:52:02 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id k15so6806555wrn.10; Sat, 26 Sep 2020 05:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=foqK6d6PeFS41hCQFnmZHZLvMNZeja8GwkTNzpenNPE=; b=HZ5zxkP2mVnrLayUJOr3gUjOa49srhi8RntJAa++LZmdX4rp3uW0qGuZBgLxsOBB14 qOJ8QQqciOxgx6cjavko9c0jfKNfSyAKC02HUBiwGszIzhTG9jf8O7Vmq7uTm/acLfPo 6G1n9WMFR0r/PxgAYrmlQZDp0lcqDTq4Q0D+2Vjg3GghubLw2PPsl8x9qOYkab1LTl7h 4k4YlEGyVYrCFXpDvdQ05hGKmVqqeJhaj6i0YS1a9vLC3aD40D7/1+V2wDmJ90K7GPw0 W23gaq6402ta5qnpbhx4eISlTXdHEOleAHtnPofynlrq/zr0fuGyx5liHS7gm1f1t9Va 9YJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=foqK6d6PeFS41hCQFnmZHZLvMNZeja8GwkTNzpenNPE=; b=Eow24aJ9OLfdLKG+y7w2GEG7KqSvDYfhZWPN4bCZOpMFaeSAGlgGgoXpgq8iGcFIOJ DaJBfmTU3XzJG3MMhu0o63YfDFA57MhxwOiU4PnA1S/rw3sN0AKes6de3vxV1ZeHwKzC a5Ak9J3UmNys6xSAS7WBvHcx7V05cpI+1VNegUfFAHFW6Vf0iY8ozVHKxHv9lMYjOebQ Zjj/gIaWLe7WLEJTWWtCu6Zod0rLFZM6Hvu2XREhkbuz0lLb/dqMnkXrsU2PSP1RIFI4 eiNROPj6fl91wgxPuv+sDK7FrQSPwWpogeAVe4YCfF0YX+Ij14mv+qATC57tsfpfQXMY MsqA== X-Gm-Message-State: AOAM532rr0xchNHNvfnEjGF8jonpb//K3iMPnwpc75p1A2a3X9vFwOLe D7AT4zKQ9pOVv2eUQNowHyk= X-Google-Smtp-Source: ABdhPJzj57ykvAkR8sPQK4WXT9fZ19k0L75upjkVIzxAPQQFacUyUnq9zlGMYnqhP+HWrKhHLLJlLw== X-Received: by 2002:adf:cd05:: with SMTP id w5mr9428546wrm.62.1601124721243; Sat, 26 Sep 2020 05:52:01 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id a10sm2520451wmj.38.2020.09.26.05.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 05:52:00 -0700 (PDT) From: kholk11@gmail.com To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, konradybcio@gmail.com, kholk11@gmail.com, marijns95@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] drm/msm/a5xx: Disable UCHE global filter Date: Sat, 26 Sep 2020 14:51:46 +0200 Message-Id: <20200926125146.12859-8-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926125146.12859-1-kholk11@gmail.com> References: <20200926125146.12859-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index bdc852e7d979..71cd8a3a6bf1 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -722,6 +722,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a512(adreno_gpu)) gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, 0x00000E81, BIT(29)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);