From patchwork Sat Sep 26 12:59:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801367 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE410112E for ; Sat, 26 Sep 2020 13:00:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0E33221ED for ; Sat, 26 Sep 2020 13:00:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tiXXJpYz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727499AbgIZNAN (ORCPT ); Sat, 26 Sep 2020 09:00:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729093AbgIZNAL (ORCPT ); Sat, 26 Sep 2020 09:00:11 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8616C0613D3; Sat, 26 Sep 2020 06:00:10 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id j2so6855239wrx.7; Sat, 26 Sep 2020 06:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eMld5gY+2zvkyoWP4cdMGVU0dV27KoJaLDxKtwGwGLw=; b=tiXXJpYzUvhrdD8vLBz52cA1Xryg8QnRxF5Vvj4CD1UYFpJ4gZWwfHjbOH0/uyRx0D O/B7N0jLT5yTYDayB0yrr4euzD6DCYo2RtRckWk92nl0NfWWgd5oBcXkUGcCf3yVJjNj /MfY7ARJVFg7jA7rtFTEcLk3YgBbSlLDjd+7jBZpzQJ68Fn8a2Vi9/f5nYoh9KMkY/kb Zok5LC+yYrfRDDwkkAJs5UuHprRkl5Aljt1EgY5qcV/cy/4WxLq0a8by1TCjSh6aevuz 76hCDNiN+0giaPfjnHlb9yHR3mafxv7ebw9bdA+Dq8CbfD1HC3QDqTCK7jzrCo2Ga7Vl GnpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eMld5gY+2zvkyoWP4cdMGVU0dV27KoJaLDxKtwGwGLw=; b=OHOMANjQlS22eEPOgbwZqaMJps0lU3Sep1bzAQjL/TlhQwY3cfWm9D63TKnvmpIF5a G11N0hxrz+qpHYYiNzYdZGy+7G6W/DxIfFp0FWKuDvnDpqyKTtG+0vn+ec7nI9jTCe3I mYtuzEstVPeODUw44ykEIgb/eQR+3HSFyWEK07SzRQghGxQAwp86jGXQkzG1sJ3vUUig 4KdhmKHfAPDXbvzb1/LT4JATmqtsAJibzOHVGsDF/oVwEEACRvZCvJull6grsyuKKtw5 mpkc2b8iUrTReDNe3raZRLTy8M/35mmUG00YwusmNkP9MUd5Y3fWIl4LTgnpYdIZM6vE IooQ== X-Gm-Message-State: AOAM530RyzOYsoIuJois0EIetJ+AULdXX6KlNrv0GrHNSYiwu7XGnRDx punm9spteCxu+dIREV0tGXQ= X-Google-Smtp-Source: ABdhPJyX9Pl2HPvTtJFa+EQBU2CcFjI2zDkLLJXHjvlXOdf/yDfQGadlMN2YIudnBdFmBttCOlnnCg== X-Received: by 2002:adf:c3cc:: with SMTP id d12mr9607388wrg.399.1601125209518; Sat, 26 Sep 2020 06:00:09 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id b11sm6462896wrt.38.2020.09.26.06.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:00:09 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] iommu/arm-smmu-qcom: Rename qcom_smmu_impl to qcom_smmu500_impl Date: Sat, 26 Sep 2020 14:59:57 +0200 Message-Id: <20200926130004.13528-2-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Rename qcom_smmu_impl to qcom_smmu500_impl, as it refers only to the MMU-500 in Qualcomm SoCs, in preparation for adding implementation details for ones having SMMUv2. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index be4318044f96..7859fd0db22a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -60,7 +60,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) return 0; } -static const struct arm_smmu_impl qcom_smmu_impl = { +static const struct arm_smmu_impl qcom_smmu500_impl = { .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; @@ -75,7 +75,7 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) qsmmu->smmu = *smmu; - qsmmu->smmu.impl = &qcom_smmu_impl; + qsmmu->smmu.impl = &qcom_smmu500_impl; devm_kfree(smmu->dev, smmu); return &qsmmu->smmu; From patchwork Sat Sep 26 12:59:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7716D16BC for ; Sat, 26 Sep 2020 13:00:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AB9322204 for ; Sat, 26 Sep 2020 13:00:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bh7kQkJw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729283AbgIZNAO (ORCPT ); Sat, 26 Sep 2020 09:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728466AbgIZNAM (ORCPT ); Sat, 26 Sep 2020 09:00:12 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F39DDC0613D4; Sat, 26 Sep 2020 06:00:11 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id m6so6910440wrn.0; Sat, 26 Sep 2020 06:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bY8xzUZwfiRgG++8UhbUZ4PhMonRbvfxxs1/C1VhNr8=; b=bh7kQkJwX2m931m/aoB/kEq4oBF/pUu4FaDCgI1FK44ZubMuxK8CfmGFL2NtcUaa4g 4jorXQKRCP3vcizvjaFTUCq8GEvfZdiPQ1qqEGcewDwl3NB+DTBN6fJm3jiZq0zSc0p5 +mhGTmRvvtT6T9Fua4KpcGCTS+8y69RKs2/9cCsAMivHwFHUl+4RPoBTzeeP68vav2BQ e6Nd+2DO9dnIiksFJ7+S7UJEJuuduiic1yT3YG0ItIyrNzBVbuaJUeSdyCXEoZmflDhM k5p8XCyrT9ajdJOyXOlSzThp4PVmk9NWuO3zkYKnNAWymwRa5CapmPc54KF0dVFikUja BFBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bY8xzUZwfiRgG++8UhbUZ4PhMonRbvfxxs1/C1VhNr8=; b=Hy+l16mecyjyM3mlkRaEoLgBsCWBGsX8E/MSpPlc7T0kB8pi3SvqxQ3dFZb1QXqSyA 5mnjyrzbW4j2VzVkcSi7Fu6krvOaPjGBuZA18tT4UDJCRRWDMQWKfQj3BHv+H2Xh/QAB NwGYcTXq1qZFyoDKVC+fIMZcH5h3vwBlKMbQrFLOnq2XErofzyvyvVGbfUQBWFOwX5Nq PohRzs/XO6AGtyVA7YhXavfTzlEIfBLqXL1uQSelTTX0nicxmmrXJoCdBENH4rmpctSh x5LSNwOv4bqpjyNiHB0Ja81oWM3Lg1h8rT4djVmfHrY4qWjrVmoUZ4cxYkh3YZDr2A5Y wiTw== X-Gm-Message-State: AOAM530VIBlxatZ/2ZPuzRf6cex9bTwIjyIJrS+moojrEQEQXb7mGqYO VJu9ZdvExOQM8J7TdSkAJN8PPHljwQkHAw== X-Google-Smtp-Source: ABdhPJyVK04EKr7pFq0l3qQczUszF+ln+iNUYNkyLlGdTas05FXQL/BmnqnjiRQDIhHluJ1TDk4wnA== X-Received: by 2002:adf:b306:: with SMTP id j6mr9052769wrd.279.1601125210585; Sat, 26 Sep 2020 06:00:10 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id b11sm6462896wrt.38.2020.09.26.06.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:00:10 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] iommu/arm-smmu-qcom: Add QC SMMUv2 VA Size quirk for SDM660 Date: Sat, 26 Sep 2020 14:59:58 +0200 Message-Id: <20200926130004.13528-3-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Some IOMMUs are getting set-up for Shared Virtual Address, but: 1. They are secured by the Hypervisor, so any configuration change will generate a hyp-fault and crash the system 2. This 39-bits Virtual Address size deviates from the ARM System MMU Architecture specification for SMMUv2, hence it is non-standard. In this case, the only way to keep the IOMMU as the firmware did configure it, is to hardcode a maximum VA size of 39 bits (because of point 1). This gives the need to add implementation details bits for at least some of the SoCs having this kind of configuration, which are at least SDM630, SDM636 and SDM660. These implementation details will be enabled on finding the qcom,sdm660-smmu-v2 compatible. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 ++- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 31 +++++++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c index f4ff124a1967..9d753f8af2cc 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -216,7 +216,8 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) if (of_device_is_compatible(np, "nvidia,tegra194-smmu")) return nvidia_smmu_impl_init(smmu); - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || + if (of_device_is_compatible(np, "qcom,sdm660-smmu-v2") || + of_device_is_compatible(np, "qcom,sdm845-smmu-500") || of_device_is_compatible(np, "qcom,sc7180-smmu-500") || of_device_is_compatible(np, "qcom,sm8150-smmu-500") || of_device_is_compatible(np, "qcom,sm8250-smmu-500")) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7859fd0db22a..f5bbfe86ef30 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -65,8 +65,33 @@ static const struct arm_smmu_impl qcom_smmu500_impl = { .reset = qcom_smmu500_reset, }; +static int qcom_smmuv2_cfg_probe(struct arm_smmu_device *smmu) +{ + /* + * Some IOMMUs are getting set-up for Shared Virtual Address, but: + * 1. They are secured by the Hypervisor, so any configuration + * change will generate a hyp-fault and crash the system + * 2. This 39-bits Virtual Address size deviates from the ARM + * System MMU Architecture specification for SMMUv2, hence + * it is non-standard. In this case, the only way to keep the + * IOMMU as the firmware did configure it, is to hardcode a + * maximum VA size of 39 bits (because of point 1). + */ + if (smmu->va_size > 39UL) + dev_notice(smmu->dev, + "\tenabling workaround for QCOM SMMUv2 VA size\n"); + smmu->va_size = min(smmu->va_size, 39UL); + + return 0; +} + +static const struct arm_smmu_impl qcom_smmuv2_impl = { + .cfg_probe = qcom_smmuv2_cfg_probe, +}; + struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) { + const struct device_node *np = smmu->dev->of_node; struct qcom_smmu *qsmmu; qsmmu = devm_kzalloc(smmu->dev, sizeof(*qsmmu), GFP_KERNEL); @@ -75,7 +100,11 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) qsmmu->smmu = *smmu; - qsmmu->smmu.impl = &qcom_smmu500_impl; + if (of_device_is_compatible(np, "qcom,sdm660-smmu-v2")) { + qsmmu->smmu.impl = &qcom_smmuv2_impl; + } else { + qsmmu->smmu.impl = &qcom_smmu500_impl; + } devm_kfree(smmu->dev, smmu); return &qsmmu->smmu; From patchwork Sat Sep 26 12:59:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801371 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A7D58112E for ; Sat, 26 Sep 2020 13:00:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 878BB221ED for ; Sat, 26 Sep 2020 13:00:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A9RNERA5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729336AbgIZNAO (ORCPT ); Sat, 26 Sep 2020 09:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729106AbgIZNAN (ORCPT ); Sat, 26 Sep 2020 09:00:13 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14777C0613D5; Sat, 26 Sep 2020 06:00:13 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id k18so2092313wmj.5; Sat, 26 Sep 2020 06:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lNEOPS5izWVikcRm4bTXQ52QCQiNW36i/3Zouqjok3Q=; b=A9RNERA5Z0JtArtts32dJtxIbwzWJEPmIymAOBcQvNw36j9us40HuxH87DxMW9ooFp 337pjQtkLJCIBUjsCfSfnaIrflUnvxrO+zvLIP14j6VpM0mYNkRFk6jbGZlCif2x6WV4 qrzk3bKDxNallRtDENEe5QE6k3RMtC2X9H9WnPlR/+iyNBpYPaxK4rpnRZ8FTv81Ys97 6vIRumziqpDPcUcc7e/KMPLwk/XvPO8DzvpEQCwa+n7KRHEBWIKabMUjJ2d/DV764q2c PRCjAW/suXDM1gzhcMsGxsv7mD5fYQeNadmrMH9nkb4+pKg/PE6Cf3A81pkfPdz67vkK DQ3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lNEOPS5izWVikcRm4bTXQ52QCQiNW36i/3Zouqjok3Q=; b=m8R5AgzC0fELR8d4bMiexSyOV4Y61N3IAB4UCPbZ/EGRmzkWnEEetVfsTtzDHMMYvn Z5fEFkbHO3Lj/h8K2OKTDp7qTFVW04hr6sxs4qdvGqQUIiffCwV4TNOzadZldBaFkYKU GmSvYZR0z1w41upwYwyorkN0ZodYs5/9glt47H6Anoe2Iw5/VVe0+5mfkJoShWiwEyxf jW0BA14KJt6MHP2cG5xH0DLy24Omc7YygICz5eiOGNQe78m4O26JitFbp8dkDMd3raUU Z3ve1JhBmxKQTSzpER1jHGvN83mF6QuXFgARwKvaJD6CkpHtY9jXnSonAo2sfgskBF0G moBQ== X-Gm-Message-State: AOAM531g0VHobdvHqHw3klTU6FQt8wScRArG5ftRV8g4N4e4Hi9jjjfg eVr85yBhVugM0ojjdDS/ile/uh8doc9B1w== X-Google-Smtp-Source: ABdhPJyTSmYAr3yteHYhVxa0Sbc5g8/MwW/505EpkDKmmFrjOLvZjv2ktKOEVc+l+prgFKJJB7ImHQ== X-Received: by 2002:a05:600c:4108:: with SMTP id j8mr2617471wmi.116.1601125211625; Sat, 26 Sep 2020 06:00:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id b11sm6462896wrt.38.2020.09.26.06.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:00:11 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] dt-bindings: arm-smmu: add binding for SMMUv2 on Qualcomm SDM660 Date: Sat, 26 Sep 2020 14:59:59 +0200 Message-Id: <20200926130004.13528-4-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Add the binding for the SMMUv2 found on Qualcomm SDM660. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..fdad89fbf130 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -26,6 +26,7 @@ properties: - description: Qcom SoCs implementing "arm,smmu-v2" items: - enum: + - qcom,sdm660-smmu-v2 - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 - qcom,sc7180-smmu-v2 From patchwork Sat Sep 26 13:00:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801387 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 827A816BC for ; Sat, 26 Sep 2020 13:00:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E252221ED for ; Sat, 26 Sep 2020 13:00:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LlSED+QC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729726AbgIZNAp (ORCPT ); Sat, 26 Sep 2020 09:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729306AbgIZNAO (ORCPT ); Sat, 26 Sep 2020 09:00:14 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F219C0613CE; Sat, 26 Sep 2020 06:00:14 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id e11so1256074wme.0; Sat, 26 Sep 2020 06:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kfKqlQuYC0e0jDmwMTghnvCFGTLGac0UG8r/BLo/Ke0=; b=LlSED+QC3XXij9wjZJZMy/EDszLM/ISPhWAXpsfhsElXVvFu2qm+Tm6hTEqOppETcC y9uLte3DwjCtXi7qrAWx0gZevpCLoXydl4hYxJ2yl3Sk9crveMwDuUutqM3jNQjBhx8T k6PyThtfts4V1dxE3zcJINMzp0UcxdCky2UIk/1t+4Gagrl3/Ki4WQpBCz+yO2BaHWIt oD5vV8HrF69jOZin82O4P6qIb3mCdJ+k08wNg56Bgsxenp/dofyqomQMTVUhOb5jKcSP fvH6DWRB0tbx9CiPE/LbEepz+HxiO+0hJhZAVcJ0vbgtm/Zu1lT8s0w8LGrgpidUQLrC 9QeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kfKqlQuYC0e0jDmwMTghnvCFGTLGac0UG8r/BLo/Ke0=; b=hySozt6kDjQPUENO78F9I4HfNtrVVmRWQoHHJONE7jgKvt2/X0QrDAw3hoL+0xSs3K ICByGcGv4DTaFyX1dZqXYQ7xDDkF+IUK6aAnovyccJ0yJ572lskFr6KfFuk7Y15xgEw8 JK1k+O+pcMzzqDVLAh9MgXNrjZSPz1J0HyKBRTEtHgqptOudT6+X4AmHCEZ6AFC0f2FZ qnjjEMyvv2j1HrZRANbOBgy6NUcZuMcfFdOwtbnHtBIkd6ZU/olyiv7P3Y86f2/LrhxE j1HvJzW8QlrdCudBZOg25aL38PYHeqJ2EgaeRfGMo4zbuE5Q1Zz9K8j/cx7lbXRfDBB5 GFjw== X-Gm-Message-State: AOAM532GanBbhDJsZRWbDzfd03vNkOHAOd9OFLPwvgN3kA7VZVrjha3l xUbX3W01PnQ30iehK2Qul88= X-Google-Smtp-Source: ABdhPJzMcK+iZK0k6ZZgTjWyhO/xS6/OemqWzbpjQ6TO2WbiVL666VwtCSqyNrAtia99xD1QNxdu7Q== X-Received: by 2002:a1c:6487:: with SMTP id y129mr2668961wmb.90.1601125212771; Sat, 26 Sep 2020 06:00:12 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id b11sm6462896wrt.38.2020.09.26.06.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:00:12 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] iommu/arm-smmu: Support test_smr_masks implementation detail deviation Date: Sat, 26 Sep 2020 15:00:00 +0200 Message-Id: <20200926130004.13528-5-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno At least some Qualcomm SoCs do need to override the function arm_smmu_test_smr_masks entirely: add a test_smr_masks function to the implementation details structure and call it properly. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 6 ++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 09c42af9f31e..446a78dde9cd 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -977,6 +977,12 @@ static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) if (!smmu->smrs) return; + + if (smmu->impl && smmu->impl->test_smr_masks) { + smmu->impl->test_smr_masks(smmu); + return; + } + /* * If we've had to accommodate firmware memory regions, we may * have live SMRs by now; tread carefully... diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index d890a4a968e8..2cd3d126f675 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -387,6 +387,7 @@ struct arm_smmu_impl { int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); int (*init_context)(struct arm_smmu_domain *smmu_domain); + void (*test_smr_masks)(struct arm_smmu_device *smmu); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, int status); int (*def_domain_type)(struct device *dev); From patchwork Sat Sep 26 13:00:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801373 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC2CB16BC for ; Sat, 26 Sep 2020 13:00:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC4F8221ED for ; Sat, 26 Sep 2020 13:00:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GVKvSy0s" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729505AbgIZNA0 (ORCPT ); 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Sat, 26 Sep 2020 06:00:13 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] iommu/arm-smmu-qcom: Add test_smr_masks detail to QCOM SMMUv2 Date: Sat, 26 Sep 2020 15:00:01 +0200 Message-Id: <20200926130004.13528-6-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno On some Qualcomm SoCs with certain hypervisor configurations, writing the streamid masks to the SMRs will trigger a hyp-fault and crash the system. This is seen on at least Qualcomm SDM630, SDM636 and SDM660. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index f5bbfe86ef30..b18e70bddf29 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -85,8 +85,21 @@ static int qcom_smmuv2_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static void qcom_smmuv2_test_smr_masks(struct arm_smmu_device *smmu) +{ + /* + * Broken firmware quirk: + * On some Qualcomm SoCs with certain hypervisor configurations, + * writing the streamid masks to the SMRs will trigger a hyp-fault + * and crash the system. + */ + smmu->streamid_mask = 0x7FFF; + smmu->smr_mask_mask = 0x7FFF; +} + static const struct arm_smmu_impl qcom_smmuv2_impl = { .cfg_probe = qcom_smmuv2_cfg_probe, + .test_smr_masks = qcom_smmuv2_test_smr_masks, }; struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) From patchwork Sat Sep 26 13:00:02 2020 Content-Type: text/plain; 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Sat, 26 Sep 2020 06:00:15 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu ([2.237.20.237]) by smtp.gmail.com with ESMTPSA id b11sm6462896wrt.38.2020.09.26.06.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2020 06:00:14 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] iommu/arm-smmu: Move stream mapping reset to separate function Date: Sat, 26 Sep 2020 15:00:02 +0200 Message-Id: <20200926130004.13528-7-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Move the stream mapping reset logic from arm_smmu_device_reset into a separate arm_smmu_stream_mapping_reset function, in preparation for implementing an implementation detail. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 446a78dde9cd..8c070c493315 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1652,14 +1652,9 @@ static struct iommu_ops arm_smmu_ops = { .pgsize_bitmap = -1UL, /* Restricted during device attach */ }; -static void arm_smmu_device_reset(struct arm_smmu_device *smmu) +static void arm_smmu_stream_mapping_reset(struct arm_smmu_device *smmu) { int i; - u32 reg; - - /* clear global FSR */ - reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); /* * Reset stream mapping groups: Initial values mark all SMRn as @@ -1673,6 +1668,18 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); } +} + +static void arm_smmu_device_reset(struct arm_smmu_device *smmu) +{ + u32 reg; + + /* clear global FSR */ + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); + + /* Reset stream mapping */ + arm_smmu_stream_mapping_reset(smmu); /* Invalidate the TLB, just in case */ arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); From patchwork Sat Sep 26 13:00:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801377 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31DFF112E for ; Sat, 26 Sep 2020 13:00:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14D64221EC for ; Sat, 26 Sep 2020 13:00:40 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 26 Sep 2020 06:00:15 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] iommu/arm-smmu: Support stream_mapping_reset implementation detail Date: Sat, 26 Sep 2020 15:00:03 +0200 Message-Id: <20200926130004.13528-8-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno Some IOMMUs may be in need of overriding the stream mapping reset function and this is seen on at least some Qualcomm SoCs: add a stream_mapping_reset function to the implementation details and call it in the appropriate function. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 8c070c493315..44571873f148 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1656,6 +1656,11 @@ static void arm_smmu_stream_mapping_reset(struct arm_smmu_device *smmu) { int i; + if (smmu->impl && smmu->impl->stream_mapping_reset) { + smmu->impl->stream_mapping_reset(smmu); + return; + } + /* * Reset stream mapping groups: Initial values mark all SMRn as * invalid and all S2CRn as bypass unless overridden. diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 2cd3d126f675..9c045594b8cf 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -387,6 +387,7 @@ struct arm_smmu_impl { int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); int (*init_context)(struct arm_smmu_domain *smmu_domain); + void (*stream_mapping_reset)(struct arm_smmu_device *smmu); void (*test_smr_masks)(struct arm_smmu_device *smmu); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, int status); From patchwork Sat Sep 26 13:00:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 11801375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E29F0112C for ; Sat, 26 Sep 2020 13:00:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6ABD22204 for ; Sat, 26 Sep 2020 13:00:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="n/LlruLX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728861AbgIZNAc (ORCPT ); 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Sat, 26 Sep 2020 06:00:16 -0700 (PDT) From: kholk11@gmail.com To: will@kernel.org Cc: robin.murphy@arm.com, joro@8bytes.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kholk11@gmail.com, marijns95@gmail.com, konradybcio@gmail.com, martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] iommu/arm-smmu-qcom: Add stream_mapping_reset detail to QCOM SMMUv2 Date: Sat, 26 Sep 2020 15:00:04 +0200 Message-Id: <20200926130004.13528-9-kholk11@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200926130004.13528-1-kholk11@gmail.com> References: <20200926130004.13528-1-kholk11@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: AngeloGioacchino Del Regno On some Qualcomm SoCs with certain hypervisor configurations, some context banks are hyp-protected and cannot be disabled, nor the relative S2CRs can be set as bypass, or a hyp-fault will be triggered and the system will hang. This is seen on at least Qualcomm SDM630, SDM636 and SDM660. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b18e70bddf29..364908cc2adf 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -85,6 +85,18 @@ static int qcom_smmuv2_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static void qcom_smmuv2_stream_mapping_reset(struct arm_smmu_device *smmu) +{ + /* + * Broken firmware quirk: + * On some Qualcomm SoCs with certain hypervisor configurations, + * some context banks are hyp-protected and cannot be disabled, + * nor the relative S2CRs can be set as bypass, or a hyp-fault + * will be triggered and the system will hang. + */ + return; +} + static void qcom_smmuv2_test_smr_masks(struct arm_smmu_device *smmu) { /* @@ -99,6 +111,7 @@ static void qcom_smmuv2_test_smr_masks(struct arm_smmu_device *smmu) static const struct arm_smmu_impl qcom_smmuv2_impl = { .cfg_probe = qcom_smmuv2_cfg_probe, + .stream_mapping_reset = qcom_smmuv2_stream_mapping_reset, .test_smr_masks = qcom_smmuv2_test_smr_masks, };