From patchwork Tue Sep 29 00:29:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 11804761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0723D618 for ; Tue, 29 Sep 2020 00:29:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B79BD21531 for ; Tue, 29 Sep 2020 00:29:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B79BD21531 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7E0489F07; Tue, 29 Sep 2020 00:29:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD67D89D63 for ; Tue, 29 Sep 2020 00:29:34 +0000 (UTC) IronPort-SDR: uB3msVuBFR88Ln56/RKqzYk7sBI6j7H703iUZIn7qPnTMmXTtdHJyMjOYsueUVvBWD4qJZVtvU ywUvZbLfkN9A== X-IronPort-AV: E=McAfee;i="6000,8403,9758"; a="180242826" X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="180242826" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:33 -0700 IronPort-SDR: LG8ZPHIdUShbKZyeqjTFQE1zAKiY1Wbd8LarAvmETP28AEFRSsIm4gg6mkj6PaDb1QsytZG2z8 UP+B7d6FsgFw== X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="488817652" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:32 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Sep 2020 03:29:25 +0300 Message-Id: <20200929002929.783620-2-imre.deak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com> References: <20200929002929.783620-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1 WRPLL parameters (assuming PDIV=7 was the intended setting). This corresponds to 262749 PLL frequency/port clock. Later the driver sets the same mode for which it calculates the same dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding). Based on the above, let's assume that PDIV=7 was intended and the HW just ignores bit#0 in the PDIV register field for this setting, treating 100b and 101b encodings the same way. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e08684e34078..095b53fe3a21 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -1602,6 +1602,14 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, case DPLL_CFGCR2_PDIV_3: p0 = 3; break; + case DPLL_CFGCR2_PDIV_7 | (1 << DPLL_CFGCR2_PDIV_SHIFT): + /* + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0, + * handling it the same way as PDIV_7. + */ + drm_err(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); + p0 = 7; + break; case DPLL_CFGCR2_PDIV_7: p0 = 7; break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47730a176698..f70e45bd3810 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10253,6 +10253,7 @@ enum skl_power_gate { #define DPLL_CFGCR2_KDIV_3 (2 << 5) #define DPLL_CFGCR2_KDIV_1 (3 << 5) #define DPLL_CFGCR2_PDIV_MASK (7 << 2) +#define DPLL_CFGCR2_PDIV_SHIFT 2 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) #define DPLL_CFGCR2_PDIV_1 (0 << 2) #define DPLL_CFGCR2_PDIV_2 (1 << 2) From patchwork Tue Sep 29 00:29:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 11804763 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D9AD618 for ; Tue, 29 Sep 2020 00:29:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF3D321531 for ; Tue, 29 Sep 2020 00:29:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF3D321531 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCE2689F19; Tue, 29 Sep 2020 00:29:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FD8C89D63 for ; Tue, 29 Sep 2020 00:29:35 +0000 (UTC) IronPort-SDR: ipgsCM0DOUEFwqm2Xlszqg/pvOo1QO75qGurPM6Rgn3V8L7AuIpk01yUkAN9PgE4j1g3npV2Us A+5vkJxH5+ZA== X-IronPort-AV: E=McAfee;i="6000,8403,9758"; a="180242829" X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="180242829" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:34 -0700 IronPort-SDR: LwMEMejqD3kvUtU0dYCeBxkkimM+r28f01iJQ05DGttOc5Xsx1GcBztIQEwrzoTtTJ+xAKv7Oh 8pniRkbxlioQ== X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="488817653" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Sep 2020 03:29:26 +0300 Message-Id: <20200929002929.783620-3-imre.deak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com> References: <20200929002929.783620-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Factor out skl_wrpll_calc_freq() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The WRPLL parameter -> frequency formula is the same for all platforms starting with SKL. Factor out the helper for this for clarity and so that we can use the same formula when selecting the ICL WRPLL dividers for DP mode in an upcoming patch (to cross-check the frequency calculated using the formula wrt. hard-coded freq values in the ICL DP PLL tables). While at it add the MISSING_CASE() for incorrect divider encodings. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 160 +++++++++++------- drivers/gpu/drm/i915/i915_reg.h | 3 + 2 files changed, 101 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 095b53fe3a21..e3370c8dccc8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -1576,31 +1576,31 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) return true; } -static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, - const struct intel_shared_dpll *pll) +static int skl_wrpll_calc_freq(int ref_clock, + u32 dco_integer, u32 dco_fraction, + u32 pdiv, u32 qdiv, u32 kdiv) { - const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; - int ref_clock = i915->dpll.ref_clks.nssc; - u32 p0, p1, p2, dco_freq; + u32 dco_freq; - p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; - p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; + dco_freq = ref_clock * dco_integer; + dco_freq += dco_fraction * ref_clock / 0x8000; - if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) - p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; - else - p1 = 1; + return dco_freq / (pdiv * qdiv * kdiv * 5); +} - - switch (p0) { +static void skl_wrpll_decode_divs(struct drm_i915_private *i915, + const struct skl_wrpll_params *wrpll_params, + u32 *pdiv, u32 *qdiv, u32 *kdiv) +{ + switch (DPLL_CFGCR2_PDIV(wrpll_params->pdiv)) { case DPLL_CFGCR2_PDIV_1: - p0 = 1; + *pdiv = 1; break; case DPLL_CFGCR2_PDIV_2: - p0 = 2; + *pdiv = 2; break; case DPLL_CFGCR2_PDIV_3: - p0 = 3; + *pdiv = 3; break; case DPLL_CFGCR2_PDIV_7 | (1 << DPLL_CFGCR2_PDIV_SHIFT): /* @@ -1608,38 +1608,63 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, * handling it the same way as PDIV_7. */ drm_err(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); - p0 = 7; + *pdiv = 7; break; + default: + MISSING_CASE(wrpll_params->pdiv); + fallthrough; case DPLL_CFGCR2_PDIV_7: - p0 = 7; + *pdiv = 7; break; } - switch (p2) { + *qdiv = wrpll_params->qdiv_mode ? wrpll_params->qdiv_ratio : 1; + + switch (DPLL_CFGCR2_KDIV(wrpll_params->kdiv)) { + default: + MISSING_CASE(wrpll_params->kdiv); + fallthrough; case DPLL_CFGCR2_KDIV_5: - p2 = 5; + *kdiv = 5; break; case DPLL_CFGCR2_KDIV_2: - p2 = 2; + *kdiv = 2; break; case DPLL_CFGCR2_KDIV_3: - p2 = 3; + *kdiv = 3; break; case DPLL_CFGCR2_KDIV_1: - p2 = 1; + *kdiv = 1; break; } +} - dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * - ref_clock; +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + struct skl_wrpll_params wrpll_params = { }; + int ref_clock = i915->dpll.ref_clks.nssc; + u32 pdiv; + u32 qdiv; + u32 kdiv; + u32 dco_integer; + u32 dco_fraction; - dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * - ref_clock / 0x8000; + wrpll_params.pdiv = (pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK) >> DPLL_CFGCR2_PDIV_SHIFT; + wrpll_params.kdiv = (pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK) >> DPLL_CFGCR2_KDIV_SHIFT; - if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) - return 0; + wrpll_params.qdiv_mode = !!(pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)); + wrpll_params.qdiv_ratio = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> + DPLL_CFGCR2_QDIV_RATIO_SHIFT; - return dco_freq / (p0 * p1 * p2 * 5); + skl_wrpll_decode_divs(i915, &wrpll_params, &pdiv, &qdiv, &kdiv); + + dco_integer = pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK; + dco_fraction = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> + DPLL_CFGCR1_DCO_FRACTION_SHIFT; + + return skl_wrpll_calc_freq(ref_clock, dco_integer, dco_fraction, pdiv, qdiv, kdiv); } static bool @@ -2630,60 +2655,71 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) return true; } -static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, - const struct intel_shared_dpll *pll, - int ref_clock) +static void cnl_wrpll_decode_divs(const struct skl_wrpll_params *wrpll_params, + u32 *pdiv, u32 *qdiv, u32 *kdiv) { - const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; - u32 p0, p1, p2, dco_freq; - - p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; - p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; - - if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) - p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> - DPLL_CFGCR1_QDIV_RATIO_SHIFT; - else - p1 = 1; - - - switch (p0) { + switch (DPLL_CFGCR1_PDIV(wrpll_params->pdiv)) { case DPLL_CFGCR1_PDIV_2: - p0 = 2; + *pdiv = 2; break; case DPLL_CFGCR1_PDIV_3: - p0 = 3; + *pdiv = 3; break; case DPLL_CFGCR1_PDIV_5: - p0 = 5; + *pdiv = 5; break; + default: + MISSING_CASE(wrpll_params->pdiv); + fallthrough; case DPLL_CFGCR1_PDIV_7: - p0 = 7; + *pdiv = 7; break; } - switch (p2) { + *qdiv = wrpll_params->qdiv_mode ? wrpll_params->qdiv_ratio : 1; + + switch (DPLL_CFGCR1_KDIV(wrpll_params->kdiv)) { case DPLL_CFGCR1_KDIV_1: - p2 = 1; + *kdiv = 1; break; case DPLL_CFGCR1_KDIV_2: - p2 = 2; + *kdiv = 2; break; + default: + MISSING_CASE(wrpll_params->kdiv); + fallthrough; case DPLL_CFGCR1_KDIV_3: - p2 = 3; + *kdiv = 3; break; } +} - dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * - ref_clock; +static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, + const struct intel_shared_dpll *pll, + int ref_clock) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + struct skl_wrpll_params wrpll_params = { }; + u32 pdiv; + u32 qdiv; + u32 kdiv; + u32 dco_integer; + u32 dco_fraction; - dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> - DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; + wrpll_params.pdiv = (pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT; + wrpll_params.kdiv = (pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT; - if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0)) - return 0; + wrpll_params.qdiv_mode = !!(pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)); + wrpll_params.qdiv_ratio = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> + DPLL_CFGCR1_QDIV_RATIO_SHIFT; - return dco_freq / (p0 * p1 * p2 * 5); + cnl_wrpll_decode_divs(&wrpll_params, &pdiv, &qdiv, &kdiv); + + dco_integer = pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK; + dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> + DPLL_CFGCR0_DCO_FRACTION_SHIFT; + + return skl_wrpll_calc_freq(ref_clock, dco_integer, dco_fraction, pdiv, qdiv, kdiv); } static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f70e45bd3810..4409c712030c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10237,6 +10237,7 @@ enum skl_power_gate { #define _DPLL3_CFGCR1 0x6C050 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) +#define DPLL_CFGCR1_DCO_FRACTION_SHIFT 9 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) @@ -10244,9 +10245,11 @@ enum skl_power_gate { #define _DPLL2_CFGCR2 0x6C04C #define _DPLL3_CFGCR2 0x6C054 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) +#define DPLL_CFGCR2_QDIV_RATIO_SHIFT 8 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) #define DPLL_CFGCR2_KDIV_MASK (3 << 5) +#define DPLL_CFGCR2_KDIV_SHIFT 5 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) #define DPLL_CFGCR2_KDIV_5 (0 << 5) #define DPLL_CFGCR2_KDIV_2 (1 << 5) From patchwork Tue Sep 29 00:29:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 11804767 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDD7992C for ; Tue, 29 Sep 2020 00:29:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3B4121531 for ; Tue, 29 Sep 2020 00:29:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B3B4121531 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D4846E3F0; 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28 Sep 2020 17:29:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Sep 2020 03:29:27 +0300 Message-Id: <20200929002929.783620-4-imre.deak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com> References: <20200929002929.783620-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When selecting the WRPLL dividers for a given port clock/PLL freq, the hard-coded PLL freq in a table entry can be calculated using the rest of parameters in the same entry. Cross-check if the hard coded values match what we calculate with the formula. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e3370c8dccc8..ded2b2dfe319 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3002,6 +3002,30 @@ static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, }; +static int icl_wrpll_ref_clock(struct drm_i915_private *i915); + +static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int clock, + const struct icl_combo_pll_params *p) +{ + int ref_clock = icl_wrpll_ref_clock(i915); + int pll_freq; + u32 pdiv; + u32 qdiv; + u32 kdiv; + + cnl_wrpll_decode_divs(&p->wrpll, &pdiv, &qdiv, &kdiv); + + pll_freq = skl_wrpll_calc_freq(ref_clock, + p->wrpll.dco_integer, p->wrpll.dco_fraction, + pdiv, qdiv, kdiv); + drm_WARN_ON(&i915->drm, pll_freq != p->clock); + + if (clock == pll_freq) + return true; + + return false; +} + static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { @@ -3014,7 +3038,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, int i; for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) { - if (clock == params[i].clock) { + if (icl_dp_combo_pll_clock_match(dev_priv, clock, ¶ms[i])) { *pll_params = params[i].wrpll; return true; } From patchwork Tue Sep 29 00:29:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 11804759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1C08618 for ; Tue, 29 Sep 2020 00:29:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8081021531 for ; Tue, 29 Sep 2020 00:29:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8081021531 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C130389F06; Tue, 29 Sep 2020 00:29:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1266D89F06 for ; Tue, 29 Sep 2020 00:29:37 +0000 (UTC) IronPort-SDR: ExBWnJQ/t3Z3aXGyrRTa7nJDCmJnYx5PwBXYeLEJbF5BDVlOwzJkEqFZOmoin2Gig8IeEx3y9u Nu7hRtSqIvkQ== X-IronPort-AV: E=McAfee;i="6000,8403,9758"; a="180242841" X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="180242841" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:36 -0700 IronPort-SDR: CJ5h/s1+LtPqv47Vc2CT4ZolNtRA+iElQh4cOG9exouFp058YpDepviocsVdz2803vj7wffmhI YAilbg0qLSkQ== X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="488817664" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:35 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Sep 2020 03:29:28 +0300 Message-Id: <20200929002929.783620-5-imre.deak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com> References: <20200929002929.783620-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a problem where the PLL output frequency is slightly off with the current PLL fractional divider value. I haven't seen an actual case where this causes a problem, but let's follow the spec. It's also needed on some EHL platforms, but for that we also need a way to distinguish the affected EHL SKUs, so I leave that for a follow-up. v2: - Apply the WA at one place when calculating the PLL dividers from the frequency and the frequency from the dividers for all the combo PLL use cases (DP, HDMI, TBT). (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 34 +++++++++++-------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index ded2b2dfe319..e7b058340a1a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2694,6 +2694,16 @@ static void cnl_wrpll_decode_divs(const struct skl_wrpll_params *wrpll_params, } } +/* + * Display WA #22010492432: tgl + * Program half of the nominal DCO divider fraction value. + */ +static bool +tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) +{ + return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400; +} + static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, const struct intel_shared_dpll *pll, int ref_clock) @@ -2719,6 +2729,9 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> DPLL_CFGCR0_DCO_FRACTION_SHIFT; + if (tgl_combo_pll_div_frac_wa_needed(dev_priv)) + dco_fraction *= 2; + return skl_wrpll_calc_freq(ref_clock, dco_integer, dco_fraction, pdiv, qdiv, kdiv); } @@ -2992,16 +3005,6 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { /* the following params are unused */ }; -/* - * Display WA #22010492432: tgl - * Divide the nominal .dco_fraction value by 2. - */ -static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { - .dco_integer = 0x54, .dco_fraction = 0x1800, - /* the following params are unused */ - .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, -}; - static int icl_wrpll_ref_clock(struct drm_i915_private *i915); static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int clock, @@ -3059,14 +3062,12 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, MISSING_CASE(dev_priv->dpll.ref_clks.nssc); fallthrough; case 19200: + case 38400: *pll_params = tgl_tbt_pll_19_2MHz_values; break; case 24000: *pll_params = tgl_tbt_pll_24MHz_values; break; - case 38400: - *pll_params = tgl_tbt_pll_38_4MHz_values; - break; } } else { switch (dev_priv->dpll.ref_clks.nssc) { @@ -3133,9 +3134,14 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915, const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *pll_state) { + u32 dco_fraction = pll_params->dco_fraction; + memset(pll_state, 0, sizeof(*pll_state)); - pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) | + if (tgl_combo_pll_div_frac_wa_needed(i915)) + dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2); + + pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | pll_params->dco_integer; pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | From patchwork Tue Sep 29 00:29:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 11804765 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9304A618 for ; Tue, 29 Sep 2020 00:29:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 759F22184D for ; Tue, 29 Sep 2020 00:29:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 759F22184D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E15A46E422; Tue, 29 Sep 2020 00:29:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3804C89F19 for ; Tue, 29 Sep 2020 00:29:38 +0000 (UTC) IronPort-SDR: NfAMQuDmJap+2g0etbLM+mRWo+v7L9wDiksmVoLVt2puoF5Rpi95uHaP0j6RWsysowPVEtn0xe 5nCf32bMy07Q== X-IronPort-AV: E=McAfee;i="6000,8403,9758"; a="180242845" X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="180242845" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:37 -0700 IronPort-SDR: Bm/R0H7ZF8/w+u3lrgBuLmH2IKu+lDVnvWg0pVs6bbjUqdwRljn0/yI1s0ro++JIfQ9CWOwcGA 9XF2XCr34NJA== X-IronPort-AV: E=Sophos;i="5.77,315,1596524400"; d="scan'208";a="488817668" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2020 17:29:37 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Sep 2020 03:29:29 +0300 Message-Id: <20200929002929.783620-6-imre.deak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com> References: <20200929002929.783620-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The TGL A stepping and some B stepping (display C stepping) BIOSes program the combo PHY DPLL fractional divider value incorrectly, not applying the Display #22010492432 workaround. Add a workaround for such BIOS versions, so that the driver selects the correct WRPLL parameter entry correctly (selecting the same entry from the table whether or not the fractional divider was adjusted or not by BIOS according to #22010492432). Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e7b058340a1a..7968ceb23ab6 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3026,7 +3026,15 @@ static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int cloc if (clock == pll_freq) return true; - return false; + if (!tgl_combo_pll_div_frac_wa_needed(i915) || + !IS_TGL_DISP_REVID(i915, TGL_REVID_A0, TGL_REVID_C0)) + return false; + + pll_freq = skl_wrpll_calc_freq(ref_clock, + p->wrpll.dco_integer, p->wrpll.dco_fraction * 2, + pdiv, qdiv, kdiv); + + return clock == pll_freq; } static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,