From patchwork Tue Sep 29 03:20:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11804887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1A426CB for ; Tue, 29 Sep 2020 03:22:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0B43216C4 for ; Tue, 29 Sep 2020 03:22:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="faeEEExf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727375AbgI2DWw (ORCPT ); Mon, 28 Sep 2020 23:22:52 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54568 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726944AbgI2DWw (ORCPT ); Mon, 28 Sep 2020 23:22:52 -0400 X-UUID: 5873de4f9dde49769f835d3d1aeefb14-20200929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UUXMeFr2hHlJSZLi34HcTDGs0TPXgBJAsi0hvj0UIoM=; b=faeEEExfi/HkXMsHEV7WcCwAEEqxOgY2fn3LnRwlxPkG43SK1ZfofsSX3Yh18YZdy8op+CqGJnG4jGkv+HAwEK0Z5GxKwJ1sH1XiY5+an2BI6DT5xcnzlTWDUtzENbv2PdyHjAK04CdWNZoIPw04h3vbVhmmNmL4Fa73OP+ieds=; X-UUID: 5873de4f9dde49769f835d3d1aeefb14-20200929 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 957987250; Tue, 29 Sep 2020 11:22:49 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 11:22:41 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Sep 2020 11:22:40 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v5,1/4] dt-binding: mediatek: watchdog: fix the description of compatible Date: Tue, 29 Sep 2020 11:20:02 +0800 Message-ID: <20200929032005.15169-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929032005.15169-1-crystal.guo@mediatek.com> References: <20200929032005.15169-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: AEDFD2495232231D73CA3DB330A350D1A49A6FA4DAF699D989BEA3844F8671392000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The watchdog driver for MT2712 and MT8183 relies on DT data, so the fallback compatible MT6589 won't work. Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 4dd36bd3f1ad..45eedc2c3141 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,13 +4,13 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 + "mediatek,mt2712-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 + "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - reg : Specifies base physical address and size of the registers. From patchwork Tue Sep 29 03:20:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11804885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E5166CB for ; Tue, 29 Sep 2020 03:22:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C387D21734 for ; Tue, 29 Sep 2020 03:22:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="B8JCwCQT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727217AbgI2DWv (ORCPT ); Mon, 28 Sep 2020 23:22:51 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:54507 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726944AbgI2DWv (ORCPT ); Mon, 28 Sep 2020 23:22:51 -0400 X-UUID: 297f1e5280614e3e8f2f0965afb039e9-20200929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=V0XHyqq4D13l/tJUvNmzHj4e1uk9k7au8T5F6+FRuGc=; b=B8JCwCQTaqIP94ONHLOrY5Ww+qP77xd76TTWdy8k0mC60EODGY6eHe0Fj1oRgo6qjkF88KA6no1gBacCnVwlo0gowTgKWTJXUrbRAN/js3Fda6YiaewpxgO+fd6kzbFmYfE7nK7HE0NiiRrHHdxgjAbyJHqPtvQO+7CKN82LMHk=; X-UUID: 297f1e5280614e3e8f2f0965afb039e9-20200929 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 89498040; Tue, 29 Sep 2020 11:22:44 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 11:22:44 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Sep 2020 11:22:41 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v5,2/4] dt-binding: mediatek: mt8192: update mtk-wdt document Date: Tue, 29 Sep 2020 11:20:03 +0800 Message-ID: <20200929032005.15169-3-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929032005.15169-1-crystal.guo@mediatek.com> References: <20200929032005.15169-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org update mtk-wdt document for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 45eedc2c3141..e36ba60de829 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 + "mediatek,mt8192-wdt": for MT8192 - reg : Specifies base physical address and size of the registers. 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Tue, 29 Sep 2020 11:22:42 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v5,3/4] dt-binding: mt8192: add toprgu reset-controller head file Date: Tue, 29 Sep 2020 11:20:04 +0800 Message-ID: <20200929032005.15169-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929032005.15169-1-crystal.guo@mediatek.com> References: <20200929032005.15169-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Acked-by: Guenter Roeck --- .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 000000000000..be9a7ca245b9 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8192_TOPRGU_MM_SW_RST 1 +#define MT8192_TOPRGU_MFG_SW_RST 2 +#define MT8192_TOPRGU_VENC_SW_RST 3 +#define MT8192_TOPRGU_VDEC_SW_RST 4 +#define MT8192_TOPRGU_IMG_SW_RST 5 +#define MT8192_TOPRGU_MD_SW_RST 7 +#define MT8192_TOPRGU_CONN_SW_RST 9 +#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8192_TOPRGU_IPU0_SW_RST 14 +#define MT8192_TOPRGU_IPU1_SW_RST 15 +#define MT8192_TOPRGU_AUDIO_SW_RST 17 +#define MT8192_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From patchwork Tue Sep 29 03:20:05 2020 Content-Type: text/plain; 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Tue, 29 Sep 2020 11:22:43 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v5,4/4] watchdog: mt8192: add wdt support Date: Tue, 29 Sep 2020 11:20:05 +0800 Message-ID: <20200929032005.15169-5-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200929032005.15169-1-crystal.guo@mediatek.com> References: <20200929032005.15169-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add support for watchdog device found in MT8192 SoC Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393f609d..aef0c2db6a11 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);