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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:39 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 1/7] dt-bindings: iio: adc: meson-saradc: add temperature sensor support Date: Sun, 28 Oct 2018 13:26:23 +0100 Message-Id: <20181028122629.10144-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052653_732650_CD669721 X-CRM114-Status: GOOD ( 11.93 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The 32-bit Meson SoCs Meson8, Meson8b and Meson8m2 can use the SAR ADC to read the chip temperature. This requires a few new, optional properties: - nvmem-cells and nvmem-cell-names are needed because the temperature sensor requires calibration to work correctly. The calibration data is stored in the eFuse. - amlogic,hhi-sysctrl is needed on Meson8b and Meson8m2 because the 5th bit of the TSC (temperature sensor calibration coefficient) is stored in the HHI register region (in the scratch register HHI_DPLL_TOP_0 at offset 0x318). Signed-off-by: Martin Blumenstingl --- .../bindings/iio/adc/amlogic,meson-saradc.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index 54b823f3a453..75c775954102 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -22,6 +22,16 @@ Required properties: - vref-supply: the regulator supply for the ADC reference voltage - #io-channel-cells: must be 1, see ../iio-bindings.txt +Optional properties: +- amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit + of the TSC (temperature sensor coefficient) on + Meson8b and Meson8m2 (which used to calibrate the + temperature sensor) +- nvmem-cells: phandle to the temperature_calib eFuse cells +- nvmem-cell-names: if present (to enable the temperature sensor + calibration) this must contain "temperature_calib" + + Example: saradc: adc@8680 { compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; 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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:41 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 2/7] iio: adc: meson-saradc: add support for the chip's temperature sensor Date: Sun, 28 Oct 2018 13:26:24 +0100 Message-Id: <20181028122629.10144-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052653_768944_19BD66D8 X-CRM114-Status: GOOD ( 29.76 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Channel 6 of the SAR ADC can be switched between two inputs: SAR_ADC_CH6 input (an actual pad on the SoC) and the signal from the temperature sensor inside the SoC. To get usable results from the temperature sensor we need to read the corresponding calibration data from the eFuse and pass it to the SAR ADC (bits [3:0]) and (on Meson8b and Meson8m2) to a scratch register in the HHI region. If the temperature sensor is not calibrated (the eFuse data contains a bit for this) then the driver will return -ENOTSUPP when trying to read the temperature. This only enables the temperature sensor for the Meson8, Meson8b and Meson8m2 SoCs because on the newer, 64-bit SoCs (GXBB, GXL and GXM) the temperature sensor inside SAR ADC is firmware-controlled (by BL30, we can simply use the SCPI hwmon driver to get the chip temperature). To keep the devicetree interface backwards compatible we simply skip the temperature sensor initialization if no eFuse nvmem cell is passed via devicetree. The public documentation for the SAR ADC IP block does not explain how to use the registers to read the temperature. The logic from this patch is based on reading and understanding Amlogic's GPL kernel sources. Signed-off-by: Martin Blumenstingl --- drivers/iio/adc/meson_saradc.c | 274 +++++++++++++++++++++++++++++---- 1 file changed, 248 insertions(+), 26 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 028ccd218f82..df1e45805c23 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #define MESON_SAR_ADC_REG0 0x00 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) @@ -165,6 +167,17 @@ #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */ +#define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6 +#define MESON_SAR_ADC_TEMP_OFFSET 27 + +/* temperature sensor calibration information in eFuse */ +#define MESON_SAR_ADC_EFUSE_BYTES 4 +#define MESON_SARADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0) +#define MESON_SARADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7) + +#define MESON_HHI_DPLL_TOP_0 0x318 +#define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9) + /* for use with IIO_VAL_INT_PLUS_MICRO */ #define MILLION 1000000 @@ -175,16 +188,27 @@ .address = _chan, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_CALIBSCALE), \ .datasheet_name = "SAR_ADC_CH"#_chan, \ } -/* - * TODO: the hardware supports IIO_TEMP for channel 6 as well which is - * currently not supported by this driver. - */ +#define MESON_SAR_ADC_TEMP_CHAN(_chan) { \ + .type = IIO_TEMP, \ + .indexed = 0, \ + .channel = _chan, \ + .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_ENABLE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_CALIBSCALE), \ + .datasheet_name = "TEMP_SENSOR", \ +} + static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { MESON_SAR_ADC_CHAN(0), MESON_SAR_ADC_CHAN(1), @@ -197,6 +221,19 @@ static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(8), }; +static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { + MESON_SAR_ADC_CHAN(0), + MESON_SAR_ADC_CHAN(1), + MESON_SAR_ADC_CHAN(2), + MESON_SAR_ADC_CHAN(3), + MESON_SAR_ADC_CHAN(4), + MESON_SAR_ADC_CHAN(5), + MESON_SAR_ADC_CHAN(6), + MESON_SAR_ADC_CHAN(7), + MESON_SAR_ADC_TEMP_CHAN(8), + IIO_CHAN_SOFT_TIMESTAMP(9), +}; + enum meson_sar_adc_avg_mode { NO_AVERAGING = 0x0, MEAN_AVERAGING = 0x1, @@ -225,6 +262,11 @@ struct meson_sar_adc_param { u32 bandgap_reg; unsigned int resolution; const struct regmap_config *regmap_config; + u8 temperature_trimming_bits; + unsigned int temperature_multiplier; + unsigned int temperature_divider; + const struct iio_chan_spec *channels; + unsigned int num_channels; }; struct meson_sar_adc_data { @@ -246,6 +288,10 @@ struct meson_sar_adc_priv { struct completion done; int calibbias; int calibscale; + struct regmap *tsc_regmap; + bool temperature_sensor_calibrated; + u8 temperature_sensor_coefficient; + u16 temperature_sensor_adc_val; }; static const struct regmap_config meson_sar_adc_regmap_config_gxbb = { @@ -389,9 +435,17 @@ static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, regval); - if (chan->address == 6) - regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, - MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0); + if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { + if (chan->type == IIO_TEMP) + regmap_update_bits(priv->regmap, + MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TEMP_SEL, + MESON_SAR_ADC_DELTA_10_TEMP_SEL); + else + regmap_update_bits(priv->regmap, + MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0); + } } static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, @@ -506,8 +560,12 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, enum meson_sar_adc_num_samples avg_samples, int *val) { + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); int ret; + if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) + return -ENOTSUPP; + ret = meson_sar_adc_lock(indio_dev); if (ret) return ret; @@ -555,17 +613,31 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, break; case IIO_CHAN_INFO_SCALE: - ret = regulator_get_voltage(priv->vref); - if (ret < 0) { - dev_err(indio_dev->dev.parent, - "failed to get vref voltage: %d\n", ret); - return ret; + if (chan->type == IIO_VOLTAGE) { + ret = regulator_get_voltage(priv->vref); + if (ret < 0) { + dev_err(indio_dev->dev.parent, + "failed to get vref voltage: %d\n", + ret); + return ret; + } + + *val = ret / 1000; + *val2 = priv->param->resolution; + return IIO_VAL_FRACTIONAL_LOG2; + } else if (chan->type == IIO_TEMP) { + /* SoC specific multiplier and divider */ + *val = priv->param->temperature_multiplier; + *val2 = priv->param->temperature_divider; + + /* celsius to millicelsius */ + *val *= 1000; + + return IIO_VAL_FRACTIONAL; + } else { + return -EINVAL; } - *val = ret / 1000; - *val2 = priv->param->resolution; - return IIO_VAL_FRACTIONAL_LOG2; - case IIO_CHAN_INFO_CALIBBIAS: *val = priv->calibbias; return IIO_VAL_INT; @@ -575,6 +647,17 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, *val2 = priv->calibscale % MILLION; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_OFFSET: + *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET * + priv->param->temperature_divider, + priv->param->temperature_multiplier); + *val -= priv->temperature_sensor_adc_val; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_ENABLE: + *val = priv->temperature_sensor_calibrated; + return IIO_VAL_INT; + default: return -EINVAL; } @@ -625,6 +708,77 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, return 0; } +static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) +{ + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + u8 *buf, trimming_bits, trimming_mask, upper_adc_val; + struct nvmem_cell *temperature_calib; + size_t read_len; + int ret; + + temperature_calib = devm_nvmem_cell_get(&indio_dev->dev, + "temperature_calib"); + if (IS_ERR(temperature_calib)) { + ret = PTR_ERR(temperature_calib); + + /* + * leave the temperature sensor disabled if no calibration data + * was passed via nvmem-cells. + */ + if (ret == -ENODEV) + return 0; + + if (ret != -EPROBE_DEFER) + dev_err(indio_dev->dev.parent, + "failed to get temperature_calib cell\n"); + + return ret; + } + + priv->tsc_regmap = syscon_regmap_lookup_by_phandle( + indio_dev->dev.parent->of_node, + "amlogic,hhi-sysctrl"); + if (IS_ERR(priv->tsc_regmap)) { + dev_err(indio_dev->dev.parent, + "failed to get amlogic,hhi-sysctrl regmap\n"); + return PTR_ERR(priv->tsc_regmap); + } + + read_len = MESON_SAR_ADC_EFUSE_BYTES; + buf = nvmem_cell_read(temperature_calib, &read_len); + if (IS_ERR(buf)) { + dev_err(indio_dev->dev.parent, + "failed to read temperature_calib cell\n"); + return PTR_ERR(buf); + } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { + kfree(buf); + dev_err(indio_dev->dev.parent, + "invalid read size of temperature_calib cell\n"); + return -EINVAL; + } + + trimming_bits = priv->param->temperature_trimming_bits; + trimming_mask = BIT(trimming_bits) - 1; + + if (buf[3] & MESON_SARADC_EFUSE_BYTE3_IS_CALIBRATED) + priv->temperature_sensor_calibrated = true; + else + priv->temperature_sensor_calibrated = false; + + priv->temperature_sensor_coefficient = buf[2] & trimming_mask; + + upper_adc_val = FIELD_GET(MESON_SARADC_EFUSE_BYTE3_UPPER_ADC_VAL, + buf[3]); + + priv->temperature_sensor_adc_val = buf[2]; + priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; + priv->temperature_sensor_adc_val >>= trimming_bits; + + kfree(buf); + + return 0; +} + static int meson_sar_adc_init(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); @@ -649,10 +803,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) meson_sar_adc_stop_sample_engine(indio_dev); - /* update the channel 6 MUX to select the temperature sensor */ + /* + * disable this bit as seems to be only relevant for Meson6 (based + * on the vendor driver), which we don't support at the moment. + */ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, - MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, - MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL); + MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0); /* disable all channels by default */ regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); @@ -709,6 +865,45 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW; regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); + if (priv->temperature_sensor_calibrated) { + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_REVE1, + MESON_SAR_ADC_DELTA_10_TS_REVE1); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_REVE0, + MESON_SAR_ADC_DELTA_10_TS_REVE0); + + /* + * set bits [3:0] of the TSC (temperature sensor coefficient) + * to get the correct values when reading the temperature. + */ + regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK, + priv->temperature_sensor_coefficient); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval); + + if (priv->param->temperature_trimming_bits == 5) { + if (priv->temperature_sensor_coefficient & BIT(4)) + regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4; + else + regval = 0; + + /* + * the 5th bit (4th when starting to count at 0) of the + * TSC is located in another register area. + */ + regmap_update_bits(priv->tsc_regmap, + MESON_HHI_DPLL_TOP_0, + MESON_HHI_DPLL_TOP_0_TSC_BIT4, + regval); + } + } else { + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_REVE1, 0); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_REVE0, 0); + } + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); if (ret) { dev_err(indio_dev->dev.parent, @@ -894,6 +1089,24 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { .bandgap_reg = MESON_SAR_ADC_DELTA_10, .regmap_config = &meson_sar_adc_regmap_config_meson8, .resolution = 10, + .temperature_trimming_bits = 4, + .temperature_multiplier = 18 * 10000, + .temperature_divider = 1024 * 10 * 85, + .channels = meson_sar_adc_and_temp_iio_channels, + .num_channels = ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels), +}; + +static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = { + .has_bl30_integration = false, + .clock_rate = 1150000, + .bandgap_reg = MESON_SAR_ADC_DELTA_10, + .regmap_config = &meson_sar_adc_regmap_config_meson8, + .resolution = 10, + .temperature_trimming_bits = 5, + .temperature_multiplier = 10, + .temperature_divider = 32, + .channels = meson_sar_adc_and_temp_iio_channels, + .num_channels = ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels), }; static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { @@ -902,6 +1115,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 10, + .channels = meson_sar_adc_iio_channels, + .num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels), }; static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { @@ -910,6 +1125,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, + .channels = meson_sar_adc_iio_channels, + .num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels), }; static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { @@ -918,12 +1135,12 @@ static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { }; static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { - .param = &meson_sar_adc_meson8_param, + .param = &meson_sar_adc_meson8b_param, .name = "meson-meson8b-saradc", }; static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = { - .param = &meson_sar_adc_meson8_param, + .param = &meson_sar_adc_meson8b_param, .name = "meson-meson8m2-saradc", }; @@ -1008,9 +1225,8 @@ static int meson_sar_adc_probe(struct platform_device *pdev) indio_dev->dev.of_node = pdev->dev.of_node; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &meson_sar_adc_iio_info; - - indio_dev->channels = meson_sar_adc_iio_channels; - indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels); + indio_dev->channels = priv->param->channels; + indio_dev->num_channels = priv->param->num_channels; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); @@ -1078,6 +1294,12 @@ static int meson_sar_adc_probe(struct platform_device *pdev) priv->calibscale = MILLION; + if (priv->param->temperature_trimming_bits) { + ret = meson_sar_adc_temp_sensor_init(indio_dev); + if (ret) + return ret; + } + ret = meson_sar_adc_init(indio_dev); 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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:42 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 3/7] ARM: dts: meson8: add the temperature calibration data for the SAR ADC Date: Sun, 28 Oct 2018 13:26:25 +0100 Message-Id: <20181028122629.10144-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052654_950795_73359E82 X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3e3d9c54cddc..30d4406f63b3 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -304,6 +304,11 @@ compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -364,6 +369,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { From patchwork Sun Oct 28 12:26:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10658561 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3171113BF for ; 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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:43 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 4/7] ARM: dts: meson8b: add the temperature calibration data for the SAR ADC Date: Sun, 28 Oct 2018 13:26:26 +0100 Message-Id: <20181028122629.10144-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052656_504002_64C11BEA X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index f92aab0aa247..dd47af174c4d 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -283,6 +283,11 @@ compatible = "amlogic,meson8b-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -354,6 +359,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { From patchwork Sun Oct 28 12:26:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10658555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5121E13BF for ; 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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:45 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 5/7] ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature Date: Sun, 28 Oct 2018 13:26:27 +0100 Message-Id: <20181028122629.10144-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052657_817512_715F7021 X-CRM114-Status: GOOD ( 10.24 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b-ec100.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..0cebe849a920 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -64,6 +64,11 @@ timeout-ms = <20000>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + leds { compatible = "gpio-leds"; From patchwork Sun Oct 28 12:26:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10658563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 85CC213BF for ; Sun, 28 Oct 2018 12:28:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73CAD29603 for ; Sun, 28 Oct 2018 12:28:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6803B299CB; Sun, 28 Oct 2018 12:28:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EC15729603 for ; Sun, 28 Oct 2018 12:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VhK5aa7bXc0b80PBSiPGcc4C+uMKSM/zd6LUBmDZUi8=; b=igb30zmR/WgFj7 GfEm0aW8d4C/M9Y8309Tw/AR/QcxvmL9sFJzd3AJCG4zyRoiUJiWUaceG3njVkaq8sbW54j5KYbnu pG6x7TacwFZjbCAOvY8o/hwmoxjc19PRyYhVdAOdw+SA6mv+dP48QqnOysWqyUopH7ogMz9Q8AEO/ quFVIit2LCM8d9k60GK+RJ2QQURqyM1EBFHMjA8RuQDjYeePXxNWB66zpwDIgAXLcIij4ORCv5Jzy ifyBnILbF4ASHuYySW4+Dr/LHlBy2/qe/O/gRqb9CwAWJGh4tJvkWj1hVcU4x8kRpcSWewL9LAvWd 87etCci27OPSTYamH4YA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gGkAl-0003P7-OF; Sun, 28 Oct 2018 12:28:03 +0000 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gGk9j-0001gi-9n for linux-amlogic@lists.infradead.org; Sun, 28 Oct 2018 12:27:27 +0000 Received: by mail-wm1-x344.google.com with SMTP id h2-v6so1730013wmb.0 for ; Sun, 28 Oct 2018 05:26:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=prCbsAZYHBZXBMZjnYd8p/ypfm7Aif1a4AOUDd9gnHc=; b=iHWXDPJ+rudq1+59kdSgBW/MNIEPzjU3qSttbp3HhHOK8fbSsLorhlN3c4rZlLOU55 lINOepslnHeo4LnV4Ddox3YiinKCrKcz00BdLCeM9+36lvwpUn2weiwqfpgksZGZ5QX5 Wsg0EdNuoCVpwzrbsMt51kQTjFFkUk5NndVK3A/q8HE3+9m4RRGsXovdOugggDXOmE8h QzEt5VQ/rw3Frv1HS+LCODf4avKgMj5b9wVk6K8RZ5qLdWawkvrf8QXQfVY4m5ZjkO5/ yJuVUg7cdysoU/Hwwz3R3gh/0vZVF4VPBP3WSjVj1LuPET2UDpU0ETB+5/X4qYS+BZmM feXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=prCbsAZYHBZXBMZjnYd8p/ypfm7Aif1a4AOUDd9gnHc=; b=Go4VxRAJZfucwHTv9XajFQse3O8R2gBQs0a+go3W4xo7o18Kxnk1rVoXxZ3qohrz8v oe++b1mTFuZBPq0nTlE/OXw/rKZrEBFZcwHNl+X827+IQl0ZMN0MKUpVpTfTowecU2dU NURYqxIhUzeMGH4z4vLMNhStGjUCoRJL1Nn9EPzPsAzCzUPVpnvPmujrkvXGQnjO9leh Ot01Fc+WSYbeek2Vynb8ohpHe2aRRPij1LbZxYWh3eKnLJBrg5ol6zcUwJGr9fHaIUc/ xNmLqx3010Si0oMRje9Tdlx6hptZ435dRNvITrbYhABoIDam/y486/ijAiN5l4ENSiKr u/TQ== X-Gm-Message-State: AGRZ1gL/MZXJJsfo3gX7TxoNrYoV78DksB3HE+gil99dgNDAa9OOlm52 EuaFN1D2+zZtY3GTQra1/DBqh6V0 X-Google-Smtp-Source: AJdET5eWhAGAAn5jHBSi+NUhERh2sqYVbpsJjMBm6Y0AZSpi2akOgSNwcUm9kaVjP3T46MBSOUTWfA== X-Received: by 2002:a1c:9ca:: with SMTP id 193-v6mr11381558wmj.86.1540729606844; Sun, 28 Oct 2018 05:26:46 -0700 (PDT) Received: from blackbox.darklights.net (p200300DCD7072200691979D1FB980407.dip0.t-ipconnect.de. [2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:46 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 6/7] ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature Date: Sun, 28 Oct 2018 13:26:28 +0100 Message-Id: <20181028122629.10144-7-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052659_377840_2E1DB56B X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b-odroidc1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..9251dc102fcc 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -118,6 +118,11 @@ 1800000 1>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_1v8: regulator-vcc-1v8 { /* * RICHTEK RT9179 configured for a fixed output voltage of From patchwork Sun Oct 28 12:26:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10658553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6738213A4 for ; Sun, 28 Oct 2018 12:27:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 55F6A29603 for ; Sun, 28 Oct 2018 12:27:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A080299CB; Sun, 28 Oct 2018 12:27:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C0A2429603 for ; Sun, 28 Oct 2018 12:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VnpScaNYsRS8zDtiReXWDaAs/WbzvXMtH/K8vWAug0I=; b=s2d+6/THhElNij 6Brh5pxOq1tiAByGUuU05Uk9yhuVCjdM0ktaXXpdRspCQMO9EIcYCSBU7FxKgn6Wf7382TMxr/nsa pYqBrAI6NRyPJFtZdi0zyAooqQtyHDVaQqtLj/XqG4fBFpfNlRxRAKBbWlRSxVDL6+afeH64o6d17 4b9ZaJLX+8BuLY5mXvrwqRzASMjpEdus6mSM2i8FsY0GQ0BXd9S4L5u+pjgAwR5VTPXTbd7YzvaWy uHIX30Yqd3/TYjRhnk9Ebe9HcEZHgnZ/vx8gVbr8GtaE04+GvnCRqGKTcZoZdMS9NUEuN+sgYnuJp wVfhhReZak3YZ3XM1v4w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gGkA3-0002dY-2e; Sun, 28 Oct 2018 12:27:19 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gGk9d-0001jL-Jn for linux-amlogic@lists.infradead.org; Sun, 28 Oct 2018 12:27:03 +0000 Received: by mail-wr1-x441.google.com with SMTP id w5-v6so5720935wrt.2 for ; Sun, 28 Oct 2018 05:26:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3J5GHlWtAlCs+VfsWg4QkmqLnd69uQtdQjrYYdsyxB4=; b=PfcyN/BOGV3BV2HlkQ47S5i9WmknSxc8hLWPK2RnCgMuZvJcsvQfBePWmi8CXka6LY 5hDmjH74u14hFDry0uL62qHXZnk3OXY7xytdNQ3SRvum04hGyYF8YcIqrmr+w/wCSSmF h1DXDOHjIl6X+0Qg0qJDDQ3k/0IMNR5ZazTQG9LHwUgDKvXATpUQycp3RHRfyHYoaJUU UZXLqmdZdck7QK5G+7lHbRrbk+K4MhnF7qbhf47+AUQr5DlVqDRC119rSlkcCzaj3MqM GP4ghlFa9lZIcOdvaqUSCNJoByCk1cPOg1iByoIKMy5Zh8H115p/0qNWKiFgLUzHE+dA PUAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3J5GHlWtAlCs+VfsWg4QkmqLnd69uQtdQjrYYdsyxB4=; b=I88VW8gMKLezk4gHeBqnRPm0P9o/FzdUHRRoi/LV70dXEwRe2qupUX02WOSwCXk1xf Q1zZmBRBvV9ro7YoGhp2f1Hg3kMuS0S1oSzY5mYr/mZ3SY/n//j20acH4G2Q6Zm17b8z Izb7KAUO2jEoO9OrglSsa+WbXlyXChUefktcMmUT4lqAm9CoX+n8jZGa0sB0OrpqU8jj By1wvZBBkKgEGJi63PMjfVWJuCIOwhw+LiTNcoC6f/bF8pHgd/ejhE2tY8cBZIAd0kOy 3a+Vn6gQcEOMqpE2Cmlmfydk4+yxi368IGv7gsDKAyrY9JN2gF24PL6GXiI6tOiNp7eN Wu6g== X-Gm-Message-State: AGRZ1gJVDH4pirItl+YzOVGgAIlZgJJASUwLiWnX9+bRNLCABLcpOV+Y 6mIqfZ/YvQaat1NPpYiHCpKDdqTp X-Google-Smtp-Source: AJdET5chTPzwQ7WDx5/7UYEXfh4zhBaCFjzqcQf2WfY8geykRU/T0qvcVe8TGkbpA+YxrSFo6acFaw== X-Received: by 2002:adf:94a3:: with SMTP id 32-v6mr10587099wrr.98.1540729607918; Sun, 28 Oct 2018 05:26:47 -0700 (PDT) Received: from blackbox.darklights.net (p200300DCD7072200691979D1FB980407.dip0.t-ipconnect.de. [2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id z185-v6sm19334091wmz.47.2018.10.28.05.26.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:26:47 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, robh+dt@kernel.org, pmeerw@pmeerw.net, lars@metafoo.de, knaack.h@gmx.de, jic23@kernel.org Subject: [PATCH 7/7] ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature Date: Sun, 28 Oct 2018 13:26:29 +0100 Message-Id: <20181028122629.10144-8-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> References: <20181028122629.10144-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_052653_683597_40DAA20B X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..d1d3c828c039 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -44,6 +44,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "VCC3V3";