From patchwork Tue Sep 29 14:44:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A37EA174A for ; Tue, 29 Sep 2020 14:40:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82C53207F7 for ; Tue, 29 Sep 2020 14:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731534AbgI2Okj (ORCPT ); Tue, 29 Sep 2020 10:40:39 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:27440 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731494AbgI2Okd (ORCPT ); Tue, 29 Sep 2020 10:40:33 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbSg7004450; Tue, 29 Sep 2020 10:40:19 -0400 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 33t2j4kehc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Sep 2020 10:40:19 -0400 Received: from SCSQMBX11.ad.analog.com (scsqmbx11.ad.analog.com [10.77.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 08TEeHEu041963 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 29 Sep 2020 10:40:18 -0400 Received: from SCSQCASHYB6.ad.analog.com (10.77.17.132) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 07:40:10 -0700 Received: from SCSQMBX11.ad.analog.com (10.77.17.10) by SCSQCASHYB6.ad.analog.com (10.77.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 07:40:02 -0700 Received: from zeus.spd.analog.com (10.66.68.11) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 29 Sep 2020 07:40:07 -0700 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkc2028450; Tue, 29 Sep 2020 10:40:09 -0400 From: Alexandru Ardelean To: , , CC: , , , , Lars-Peter Clausen , "Alexandru Ardelean" Subject: [PATCH v4 1/7] clk: axi-clkgen: Add support for fractional dividers Date: Tue, 29 Sep 2020 17:44:11 +0300 Message-ID: <20200929144417.89816-10-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Lars-Peter Clausen The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen Signed-off-by: Alexandru Ardelean --- drivers/clk/clk-axi-clkgen.c | 180 +++++++++++++++++++++++++---------- 1 file changed, 129 insertions(+), 51 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 96f351785b41..1df03cc6d089 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -27,8 +27,10 @@ #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) +#define MMCM_REG_CLKOUT5_2 0x07 #define MMCM_REG_CLKOUT0_1 0x08 #define MMCM_REG_CLKOUT0_2 0x09 +#define MMCM_REG_CLKOUT6_2 0x13 #define MMCM_REG_CLK_FB1 0x14 #define MMCM_REG_CLK_FB2 0x15 #define MMCM_REG_CLK_DIV 0x16 @@ -40,6 +42,7 @@ #define MMCM_CLKOUT_NOCOUNT BIT(6) +#define MMCM_CLK_DIV_DIVIDE BIT(11) #define MMCM_CLK_DIV_NOCOUNT BIT(12) struct axi_clkgen { @@ -107,6 +110,8 @@ static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout, unsigned long d, d_min, d_max, _d_min, _d_max; unsigned long m, m_min, m_max; unsigned long f, dout, best_f, fvco; + unsigned long fract_shift = 0; + unsigned long fvco_min_fract, fvco_max_fract; fin /= 1000; fout /= 1000; @@ -119,42 +124,89 @@ static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout, d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1); d_max = min_t(unsigned long, fin / fpfd_min, 80); - m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1); - m_max = min_t(unsigned long, fvco_max * d_max / fin, 64); +again: + fvco_min_fract = fvco_min << fract_shift; + fvco_max_fract = fvco_max << fract_shift; + + m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); + m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); for (m = m_min; m <= m_max; m++) { - _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max)); - _d_max = min(d_max, fin * m / fvco_min); + _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract)); + _d_max = min(d_max, fin * m / fvco_min_fract); for (d = _d_min; d <= _d_max; d++) { fvco = fin * m / d; dout = DIV_ROUND_CLOSEST(fvco, fout); - dout = clamp_t(unsigned long, dout, 1, 128); + dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift); f = fvco / dout; if (abs(f - fout) < abs(best_f - fout)) { best_f = f; *best_d = d; - *best_m = m; - *best_dout = dout; + *best_m = m << (3 - fract_shift); + *best_dout = dout << (3 - fract_shift); if (best_f == fout) return; } } } + + /* Lets see if we find a better setting in fractional mode */ + if (fract_shift == 0) { + fract_shift = 3; + goto again; + } } -static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low, - unsigned int *high, unsigned int *edge, unsigned int *nocount) +struct axi_clkgen_div_params { + unsigned int low; + unsigned int high; + unsigned int edge; + unsigned int nocount; + unsigned int frac_en; + unsigned int frac; + unsigned int frac_wf_f; + unsigned int frac_wf_r; + unsigned int frac_phase; +}; + +static void axi_clkgen_calc_clk_params(unsigned int divider, + unsigned int frac_divider, struct axi_clkgen_div_params *params) { - if (divider == 1) - *nocount = 1; - else - *nocount = 0; - *high = divider / 2; - *edge = divider % 2; - *low = divider - *high; + memset(params, 0x0, sizeof(*params)); + + if (divider == 1) { + params->nocount = 1; + return; + } + + if (frac_divider == 0) { + params->high = divider / 2; + params->edge = divider % 2; + params->low = divider - params->high; + } else { + params->frac_en = 1; + params->frac = frac_divider; + + params->high = divider / 2; + params->edge = divider % 2; + params->low = params->high; + + if (params->edge == 0) { + params->high--; + params->frac_wf_r = 1; + } + + if (params->edge == 0 || frac_divider == 1) + params->low--; + if (((params->edge == 0) ^ (frac_divider == 1)) || + (divider == 2 && frac_divider == 1)) + params->frac_wf_f = 1; + + params->frac_phase = params->edge * 4 + frac_divider / 2; + } } static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, @@ -246,15 +298,28 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) return container_of(clk_hw, struct axi_clkgen, clk_hw); } +static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, + unsigned int reg1, unsigned int reg2, unsigned int reg3, + struct axi_clkgen_div_params *params) +{ + axi_clkgen_mmcm_write(axi_clkgen, reg1, + (params->high << 6) | params->low, 0xefff); + axi_clkgen_mmcm_write(axi_clkgen, reg2, + (params->frac << 12) | (params->frac_en << 11) | + (params->frac_wf_r << 10) | (params->edge << 7) | + (params->nocount << 6), 0x7fff); + if (reg3 != 0) { + axi_clkgen_mmcm_write(axi_clkgen, reg3, + (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); + } +} + static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; - unsigned int nocount; - unsigned int high; - unsigned int edge; - unsigned int low; + struct axi_clkgen_div_params params; uint32_t filter; uint32_t lock; @@ -269,21 +334,18 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, filter = axi_clkgen_lookup_filter(m - 1); lock = axi_clkgen_lookup_lock(m - 1); - axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount); - axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1, - (high << 6) | low, 0xefff); - axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2, - (edge << 7) | (nocount << 6), 0x03ff); + axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); + axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, + MMCM_REG_CLKOUT5_2, ¶ms); - axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount); + axi_clkgen_calc_clk_params(d, 0, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, - (edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff); + (params.edge << 13) | (params.nocount << 12) | + (params.high << 6) | params.low, 0x3fff); - axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount); - axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1, - (high << 6) | low, 0xefff); - axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2, - (edge << 7) | (nocount << 6), 0x03ff); + axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); + axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, + MMCM_REG_CLKOUT6_2, ¶ms); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, @@ -313,35 +375,51 @@ static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate, return min_t(unsigned long long, tmp, LONG_MAX); } +static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, + unsigned int reg1, unsigned int reg2) +{ + unsigned int val1, val2; + unsigned int div; + + axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2); + if (val2 & MMCM_CLKOUT_NOCOUNT) + return 8; + + axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1); + + div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f); + div <<= 3; + + if (val2 & MMCM_CLK_DIV_DIVIDE) { + if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000) + div += 8; + else + div += 16; + + div += (val2 >> 12) & 0x7; + } + + return div; +} + static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; - unsigned int reg; unsigned long long tmp; + unsigned int val; - axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, ®); - if (reg & MMCM_CLKOUT_NOCOUNT) { - dout = 1; - } else { - axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®); - dout = (reg & 0x3f) + ((reg >> 6) & 0x3f); - } + dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, + MMCM_REG_CLKOUT0_2); + m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, + MMCM_REG_CLK_FB2); - axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®); - if (reg & MMCM_CLK_DIV_NOCOUNT) + axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); + if (val & MMCM_CLK_DIV_NOCOUNT) d = 1; else - d = (reg & 0x3f) + ((reg >> 6) & 0x3f); - - axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, ®); - if (reg & MMCM_CLKOUT_NOCOUNT) { - m = 1; - } else { - axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®); - m = (reg & 0x3f) + ((reg >> 6) & 0x3f); - } + d = (val & 0x3f) + ((val >> 6) & 0x3f); if (d == 0 || dout == 0) return 0; From patchwork Tue Sep 29 14:44:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30EDC174A for ; Tue, 29 Sep 2020 14:40:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A0E92074F for ; Tue, 29 Sep 2020 14:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731216AbgI2OkN (ORCPT ); Tue, 29 Sep 2020 10:40:13 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:49426 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725786AbgI2OkK (ORCPT ); Tue, 29 Sep 2020 10:40:10 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbPG5004157; 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Tue, 29 Sep 2020 10:39:48 -0400 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkbt028450; Tue, 29 Sep 2020 10:39:51 -0400 From: Alexandru Ardelean To: , , CC: , , , , Lars-Peter Clausen , "Alexandru Ardelean" Subject: [PATCH v4 2/7] clk: axi-clkgen: Set power bits for fractional mode Date: Tue, 29 Sep 2020 17:44:04 +0300 Message-ID: <20200929144417.89816-3-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Lars-Peter Clausen Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen Signed-off-by: Alexandru Ardelean --- drivers/clk/clk-axi-clkgen.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 1df03cc6d089..14d803e6af62 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -37,6 +37,7 @@ #define MMCM_REG_LOCK1 0x18 #define MMCM_REG_LOCK2 0x19 #define MMCM_REG_LOCK3 0x1a +#define MMCM_REG_POWER 0x28 #define MMCM_REG_FILTER1 0x4e #define MMCM_REG_FILTER2 0x4f @@ -320,6 +321,7 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); unsigned int d, m, dout; struct axi_clkgen_div_params params; + uint32_t power = 0; uint32_t filter; uint32_t lock; @@ -331,6 +333,11 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, if (d == 0 || dout == 0 || m == 0) return -EINVAL; + if ((dout & 0x7) != 0 || (m & 0x7) != 0) + power |= 0x9800; + + axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800); + filter = axi_clkgen_lookup_filter(m - 1); lock = axi_clkgen_lookup_lock(m - 1); From patchwork Tue Sep 29 14:44:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 14DD86CB for ; Tue, 29 Sep 2020 14:40:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F090D20756 for ; Tue, 29 Sep 2020 14:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730976AbgI2OkF (ORCPT ); Tue, 29 Sep 2020 10:40:05 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:37022 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728446AbgI2OkE (ORCPT ); Tue, 29 Sep 2020 10:40:04 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbS0A004451; Tue, 29 Sep 2020 10:40:01 -0400 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 33t2j4kegj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Sep 2020 10:40:01 -0400 Received: from SCSQMBX11.ad.analog.com (scsqmbx11.ad.analog.com [10.77.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 08TEdxGe041874 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 29 Sep 2020 10:40:00 -0400 Received: from SCSQMBX10.ad.analog.com (10.77.17.5) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 07:39:52 -0700 Received: from zeus.spd.analog.com (10.66.68.11) by SCSQMBX10.ad.analog.com (10.77.17.5) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 29 Sep 2020 07:39:51 -0700 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkbu028450; Tue, 29 Sep 2020 10:39:54 -0400 From: Alexandru Ardelean To: , , CC: , , , , Dragos Bogdan , Alexandru Ardelean Subject: [PATCH v4 3/7] clk: axi-clkgen: add support for ZynqMP (UltraScale) Date: Tue, 29 Sep 2020 17:44:05 +0300 Message-ID: <20200929144417.89816-4-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=577 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Dragos Bogdan This IP core also works and is supported on the Xilinx ZynqMP (UltraScale) FPGA boards. This patch enables the driver to be available on these platforms as well. Signed-off-by: Dragos Bogdan Signed-off-by: Alexandru Ardelean --- drivers/clk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b41aaed9bd51..6d76591c0bc4 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -239,7 +239,7 @@ config CLK_TWL6040 config COMMON_CLK_AXI_CLKGEN tristate "AXI clkgen driver" - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST + depends on ARCH_ZYNQ || ARCH_ZYNQMP || MICROBLAZE || COMPILE_TEST help Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. From patchwork Tue Sep 29 14:44:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8FD91746 for ; Tue, 29 Sep 2020 14:40:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C105620756 for ; Tue, 29 Sep 2020 14:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731085AbgI2OkF (ORCPT ); Tue, 29 Sep 2020 10:40:05 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:39408 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730884AbgI2OkF (ORCPT ); Tue, 29 Sep 2020 10:40:05 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbPG6004157; Tue, 29 Sep 2020 10:40:03 -0400 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 33t2j4kegm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Sep 2020 10:40:02 -0400 Received: from ASHBMBX9.ad.analog.com (ashbmbx9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 08TEe17v041885 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 29 Sep 2020 10:40:01 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 10:39:54 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 29 Sep 2020 10:39:54 -0400 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkbv028450; Tue, 29 Sep 2020 10:39:56 -0400 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v4 4/7] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Date: Tue, 29 Sep 2020 17:44:06 +0300 Message-ID: <20200929144417.89816-5-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe, and then these limits need to be adjusted for each instance of the AXI clock. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. Signed-off-by: Alexandru Ardelean --- drivers/clk/clk-axi-clkgen.c | 39 ++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 14d803e6af62..4342b7735590 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -46,9 +46,17 @@ #define MMCM_CLK_DIV_DIVIDE BIT(11) #define MMCM_CLK_DIV_NOCOUNT BIT(12) +struct axi_clkgen_limits { + unsigned int fpfd_min; + unsigned int fpfd_max; + unsigned int fvco_min; + unsigned int fvco_max; +}; + struct axi_clkgen { void __iomem *base; struct clk_hw clk_hw; + struct axi_clkgen_limits limits; }; static uint32_t axi_clkgen_lookup_filter(unsigned int m) @@ -100,12 +108,15 @@ static uint32_t axi_clkgen_lookup_lock(unsigned int m) return 0x1f1f00fa; } -static const unsigned int fpfd_min = 10000; -static const unsigned int fpfd_max = 300000; -static const unsigned int fvco_min = 600000; -static const unsigned int fvco_max = 1200000; +static const struct axi_clkgen_limits axi_clkgen_default_limits = { + .fpfd_min = 10000, + .fpfd_max = 300000, + .fvco_min = 600000, + .fvco_max = 1200000, +}; -static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout, +static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, + unsigned long fin, unsigned long fout, unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) { unsigned long d, d_min, d_max, _d_min, _d_max; @@ -122,12 +133,12 @@ static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout, *best_m = 0; *best_dout = 0; - d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1); - d_max = min_t(unsigned long, fin / fpfd_min, 80); + d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); + d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); again: - fvco_min_fract = fvco_min << fract_shift; - fvco_max_fract = fvco_max << fract_shift; + fvco_min_fract = limits->fvco_min << fract_shift; + fvco_max_fract = limits->fvco_max << fract_shift; m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); @@ -319,6 +330,7 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) { struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); + const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; struct axi_clkgen_div_params params; uint32_t power = 0; @@ -328,7 +340,7 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, if (parent_rate == 0 || rate == 0) return -EINVAL; - axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout); + axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout); if (d == 0 || dout == 0 || m == 0) return -EINVAL; @@ -368,10 +380,12 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw, static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw); + const struct axi_clkgen_limits *limits = &axi_clkgen->limits; unsigned int d, m, dout; unsigned long long tmp; - axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout); + axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout); if (d == 0 || dout == 0 || m == 0) return -EINVAL; @@ -527,6 +541,9 @@ static int axi_clkgen_probe(struct platform_device *pdev) return -EINVAL; } + memcpy(&axi_clkgen->limits, &axi_clkgen_default_limits, + sizeof(axi_clkgen->limits)); + clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", &clk_name); From patchwork Tue Sep 29 14:44:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806161 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98DF71746 for ; Tue, 29 Sep 2020 14:40:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F06021941 for ; Tue, 29 Sep 2020 14:40:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731520AbgI2Oki (ORCPT ); Tue, 29 Sep 2020 10:40:38 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:29348 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730303AbgI2Okd (ORCPT ); Tue, 29 Sep 2020 10:40:33 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbcgU004650; Tue, 29 Sep 2020 10:40:25 -0400 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 33t2j4kehp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Sep 2020 10:40:25 -0400 Received: from ASHBMBX9.ad.analog.com (ashbmbx9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 08TEeOMs041994 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 29 Sep 2020 10:40:24 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 10:40:17 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 10:40:16 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 29 Sep 2020 10:40:16 -0400 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkc6028450; Tue, 29 Sep 2020 10:40:19 -0400 From: Alexandru Ardelean To: , , CC: , , , , Mathias Tausen , "Alexandru Ardelean" Subject: [PATCH v4 5/7] clk: axi-clkgen: Respect ZYNQMP PFD/VCO frequency limits Date: Tue, 29 Sep 2020 17:44:15 +0300 Message-ID: <20200929144417.89816-14-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=743 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Mathias Tausen Since axi-clkgen is now supported on ZYNQMP, make sure the max/min frequencies of the PFD and VCO are respected. Signed-off-by: Mathias Tausen Signed-off-by: Alexandru Ardelean --- drivers/clk/clk-axi-clkgen.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 4342b7735590..2319bb1c5c08 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -108,12 +108,21 @@ static uint32_t axi_clkgen_lookup_lock(unsigned int m) return 0x1f1f00fa; } +#ifdef ARCH_ZYNQMP +static const struct axi_clkgen_limits axi_clkgen_default_limits = { + .fpfd_min = 10000, + .fpfd_max = 450000, + .fvco_min = 800000, + .fvco_max = 1600000, +}; +#else static const struct axi_clkgen_limits axi_clkgen_default_limits = { .fpfd_min = 10000, .fpfd_max = 300000, .fvco_min = 600000, .fvco_max = 1200000, }; +#endif static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, unsigned long fin, unsigned long fout, From patchwork Tue Sep 29 14:44:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 70727112C for ; Tue, 29 Sep 2020 14:40:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5605F207F7 for ; Tue, 29 Sep 2020 14:40:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731570AbgI2Okk (ORCPT ); Tue, 29 Sep 2020 10:40:40 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:20952 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731474AbgI2Ok3 (ORCPT ); Tue, 29 Sep 2020 10:40:29 -0400 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEbONO004125; Tue, 29 Sep 2020 10:40:27 -0400 Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com with ESMTP id 33t2j4kehx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Sep 2020 10:40:27 -0400 Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 08TEeQTD053460 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 29 Sep 2020 10:40:26 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 29 Sep 2020 10:40:18 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 29 Sep 2020 10:40:18 -0400 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 08TEdkc7028450; Tue, 29 Sep 2020 10:40:21 -0400 From: Alexandru Ardelean To: , , CC: , , , , Mircea Caprioru , Alexandru Ardelean Subject: [PATCH v4 6/7] include: fpga: adi-axi-common.h: add definitions for supported FPGAs Date: Tue, 29 Sep 2020 17:44:16 +0300 Message-ID: <20200929144417.89816-15-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=808 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Mircea Caprioru All (newer) FPGA IP cores supported by Analog Devices, store information in the synthesized designs. This information describes various parameters, including the family of boards on which this is deployed, speed-grade, and so on. Currently, some of these definitions are deployed mostly on Xilinx boards, but they have been considered also for FPGA boards from other vendors. The register definitions are described at this link: https://wiki.analog.com/resources/fpga/docs/hdl/regmap (the 'Base (common to all cores)' section). Acked-by: Moritz Fischer Signed-off-by: Mircea Caprioru Signed-off-by: Alexandru Ardelean --- include/linux/fpga/adi-axi-common.h | 103 ++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-axi-common.h index 141ac3f251e6..1a7f18e3a384 100644 --- a/include/linux/fpga/adi-axi-common.h +++ b/include/linux/fpga/adi-axi-common.h @@ -13,6 +13,9 @@ #define ADI_AXI_REG_VERSION 0x0000 +#define ADI_AXI_REG_FPGA_INFO 0x001C +#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140 + #define ADI_AXI_PCORE_VER(major, minor, patch) \ (((major) << 16) | ((minor) << 8) | (patch)) @@ -20,4 +23,104 @@ #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) +#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff) + +#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff) +#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff) +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff) +#define ADI_AXI_INFO_FPGA_DEV_PACKAGE(info) ((info) & 0xff) + +/** + * FPGA Technology definitions + */ +#define ADI_AXI_FPGA_TECH_XILINX_UNKNOWN 0 +#define ADI_AXI_FPGA_TECH_XILINS_SERIES7 1 +#define ADI_AXI_FPGA_TECH_XILINX_ULTRASCALE 2 +#define ADI_AXI_FPGA_TECH_XILINX_ULTRASCALE_PLUS 3 + +#define ADI_AXI_FPGA_TECH_INTEL_UNKNOWN 100 +#define ADI_AXI_FPGA_TECH_INTEL_CYCLONE_5 101 +#define ADI_AXI_FPGA_TECH_INTEL_CYCLONE_10 102 +#define ADI_AXI_FPGA_TECH_INTEL_ARRIA_10 103 +#define ADI_AXI_FPGA_TECH_INTEL_STRATIX_10 104 + +/** + * FPGA Family definitions + */ +#define ADI_AXI_FPGA_FAMILY_UNKNOWN 0 + +#define ADI_AXI_FPGA_FAMILY_XILINX_ARTIX 1 +#define ADI_AXI_FPGA_FAMILY_XILINX_KINTEX 2 +#define ADI_AXI_FPGA_FAMILY_XILINX_VIRTEX 3 +#define ADI_AXI_FPGA_FAMILY_XILINX_ZYNQ 4 + +#define ADI_AXI_FPGA_FAMILY_INTEL_SX 1 +#define ADI_AXI_FPGA_FAMILY_INTEL_GX 2 +#define ADI_AXI_FPGA_FAMILY_INTEL_GT 3 +#define ADI_AXI_FPGA_FAMILY_INTEL_GZ 4 + +/** + * FPGA Speed-grade definitions + */ +#define ADI_AXI_FPGA_SPEED_GRADE_UNKNOWN 0 + +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1 10 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1L 11 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1H 12 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1HV 13 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_1LV 14 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2 20 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2L 21 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_2LV 22 +#define ADI_AXI_FPGA_SPEED_GRADE_XILINX_3 30 + +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_1 1 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_2 2 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_3 3 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_4 4 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_5 5 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_6 6 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_7 7 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_8 8 +#define ADI_AXI_FPGA_SPEED_GRADE_INTEL_9 9 + +/** + * FPGA Device Package definitions + */ +#define ADI_AXI_FPGA_DEV_PACKAGE_UNKNOWN 0 + +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RF 1 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FL 2 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FF 3 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FB 4 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_HC 5 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FH 6 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CS 7 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CP 8 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FT 9 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FG 10 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_SB 11 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RB 12 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_RS 13 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_CL 14 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_SF 15 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_BA 16 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FA 17 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FS 18 +#define ADI_AXI_FPGA_DEV_PACKAGE_XILINX_FI 19 + +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_BGA 1 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PGA 2 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_FBGA 3 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_HBGA 4 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PDIP 5 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_EQFP 6 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PLCC 7 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_PQFP 8 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_RQFP 9 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_TQFP 10 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_UBGA 11 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_UFBGA 12 +#define ADI_AXI_FPGA_DEV_PACKAGE_INTEL_MBGA 13 + #endif /* ADI_AXI_COMMON_H_ */ From patchwork Tue Sep 29 14:44:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 11806155 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06B4B1746 for ; Tue, 29 Sep 2020 14:40:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1900207F7 for ; Tue, 29 Sep 2020 14:40:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731373AbgI2OkZ (ORCPT ); Tue, 29 Sep 2020 10:40:25 -0400 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:54538 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731199AbgI2OkN (ORCPT ); Tue, 29 Sep 2020 10:40:13 -0400 Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08TEdGoH008107; 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Tue, 29 Sep 2020 10:40:04 -0400 From: Alexandru Ardelean To: , , CC: , , , , Mircea Caprioru , Alexandru Ardelean Subject: [PATCH v4 7/7] clk: axi-clkgen: Add support for FPGA info Date: Tue, 29 Sep 2020 17:44:09 +0300 Message-ID: <20200929144417.89816-8-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200929144417.89816-1-alexandru.ardelean@analog.com> References: <20200929144417.89816-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-09-29_07:2020-09-29,2020-09-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 mlxscore=0 clxscore=1015 mlxlogscore=856 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009290130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Mircea Caprioru This patch adds support for vco maximum and minimum ranges in accordance with fpga speed grade, voltage, device package, technology and family. This new information is extracted from two new registers implemented in the ip core: ADI_REG_FPGA_INFO and ADI_REG_FPGA_VOLTAGE, which are stored in the 'include/linux/fpga/adi-axi-common.h' file as they are common to all ADI FPGA cores. Signed-off-by: Mircea Caprioru Signed-off-by: Alexandru Ardelean --- drivers/clk/clk-axi-clkgen.c | 52 +++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index 2319bb1c5c08..46fd228b0733 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -242,6 +243,50 @@ static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, *val = readl(axi_clkgen->base + reg); } +static void axi_clkgen_setup_ranges(struct axi_clkgen *axi_clkgen) +{ + struct axi_clkgen_limits *limits = &axi_clkgen->limits; + unsigned int reg_value; + unsigned int tech, family, speed_grade, voltage; + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_INFO, ®_value); + tech = ADI_AXI_INFO_FPGA_TECH(reg_value); + family = ADI_AXI_INFO_FPGA_FAMILY(reg_value); + speed_grade = ADI_AXI_INFO_FPGA_SPEED_GRADE(reg_value); + + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_FPGA_VOLTAGE, ®_value); + voltage = ADI_AXI_INFO_FPGA_VOLTAGE(reg_value); + + switch (speed_grade) { + case ADI_AXI_FPGA_SPEED_GRADE_XILINX_1 ... ADI_AXI_FPGA_SPEED_GRADE_XILINX_1LV: + limits->fvco_max = 1200000; + limits->fpfd_max = 450000; + break; + case ADI_AXI_FPGA_SPEED_GRADE_XILINX_2 ... ADI_AXI_FPGA_SPEED_GRADE_XILINX_2LV: + limits->fvco_max = 1440000; + limits->fpfd_max = 500000; + if ((family == ADI_AXI_FPGA_FAMILY_XILINX_KINTEX) | + (family == ADI_AXI_FPGA_FAMILY_XILINX_ARTIX)) { + if (voltage < 950) { + limits->fvco_max = 1200000; + limits->fpfd_max = 450000; + } + } + break; + case ADI_AXI_FPGA_SPEED_GRADE_XILINX_3: + limits->fvco_max = 1600000; + limits->fpfd_max = 550000; + break; + default: + break; + }; + + if (tech == ADI_AXI_FPGA_TECH_XILINX_ULTRASCALE_PLUS) { + limits->fvco_max = 1600000; + limits->fvco_min = 800000; + } +} + static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) { unsigned int timeout = 10000; @@ -521,7 +566,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) const char *parent_names[2]; const char *clk_name; struct resource *mem; - unsigned int i; + unsigned int i, ver; int ret; if (!pdev->dev.of_node) @@ -553,6 +598,11 @@ static int axi_clkgen_probe(struct platform_device *pdev) memcpy(&axi_clkgen->limits, &axi_clkgen_default_limits, sizeof(axi_clkgen->limits)); + axi_clkgen_read(axi_clkgen, ADI_AXI_REG_VERSION, &ver); + + if (ADI_AXI_PCORE_VER_MAJOR(ver) > 0x04) + axi_clkgen_setup_ranges(axi_clkgen); + clk_name = pdev->dev.of_node->name; of_property_read_string(pdev->dev.of_node, "clock-output-names", &clk_name);