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Tue, 29 Sep 2020 15:33:24 +0000 From: Sagar Kadam To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, aou@eecs.berkeley.edu, yash.shah@sifive.com, Sagar Kadam Subject: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Date: Tue, 29 Sep 2020 21:02:09 +0530 Message-Id: <1601393531-2402-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> References: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) To DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3433.32 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 5ajK3skSfIGikgPF5RQoSGOya3TpQOIwKt4TIXg561V0mVDDTyAGIEa1uv0dCgaiuVWltyOzjofJuUar/b8eBk2Ek4FqvqQ7ZqysVnCRSmDohalMa+IVFThsK2n98hIsCnvTivnoY9mw9BuUd3ymkczjfzv/MbeIxzZVXZ2FAy6uLSIqGP2RPWEPAKq4leXvadnCzs+zuV7ckO2Jf2lNrbNEIFlkzne16RH1KjexxqxJpVo8Czpcd6JNEuZ5bY1FfqKANGrEX0dEs2rW/q39och3GkS9Gup2Uwjeap7+s8KgZf38SPAMgv6+14/zhoX27oWYVV4VHnZIhu4fw6KTql3FUQo/nJ2vpMjt4klwixg0KBdFERlJ+DceMkN6YuZUhD1gR0o8G/qgNofvofi4j33O+Jdd1vbpAzpwVCWx4+Tz93jEZ/beRz2QoTDA2QFz3SyIw5pAxPblYXNpO2rI+Nnuu8NA4NU7kpkTYaPgBt/er/W/Xo/4Gi3FQzmoJp4PfJYcN+4UaMKFKZNh0CoQ2ZmJfHxx3D1L9ZhjKGo0QdhNl0PNS5gzWLsHHSd4zKM3nELOTMGNx7986KpsrpqvScbBM6xUcQ8KXaUNYY98DGwImtgB9SOFs0m1T7Mqj65QCFg75qKnvVn6dPSyAquw9Q== X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: eeafea32-6ad6-4c44-75c0-08d8648d0120 X-MS-Exchange-CrossTenant-AuthSource: DM6PR13MB3451.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2020 15:33:24.7184 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eoR1K6CU8kZCCkzKiF/nHZiF9rOCdbDRr0egfVpBopy+fhcQO6IpgA/bpf6PXsTCldqMG7r6V+84IiTI/n/DyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR13MB2412 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org FU540-C000 SoC from SiFive has a PRCI block, here we convert the device tree bindings from txt to YAML. Signed-off-by: Sagar Kadam --- .../bindings/clock/sifive/fu540-prci.txt | 46 ----------------- .../bindings/clock/sifive/fu540-prci.yaml | 60 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f..0000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 0000000..c3be1b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Sagar Kadam + - Paul Walmsley + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu540-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; From patchwork Tue Sep 29 15:32:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 11806295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C208B112C for ; Tue, 29 Sep 2020 15:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 840982145D for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=sifive.com; Received: from DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) by DM6PR13MB2412.namprd13.prod.outlook.com (2603:10b6:5:c3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.14; Tue, 29 Sep 2020 15:33:33 +0000 Received: from DM6PR13MB3451.namprd13.prod.outlook.com ([fe80::a48a:1f7c:267c:876]) by DM6PR13MB3451.namprd13.prod.outlook.com ([fe80::a48a:1f7c:267c:876%7]) with mapi id 15.20.3433.032; Tue, 29 Sep 2020 15:33:33 +0000 From: Sagar Kadam To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, aou@eecs.berkeley.edu, yash.shah@sifive.com, Sagar Kadam Subject: [PATCH v2 2/3] dt-bindings: riscv: convert plic bindings to json-schema Date: Tue, 29 Sep 2020 21:02:10 +0530 Message-Id: <1601393531-2402-3-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> References: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) To DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3433.32 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: ybG+ME/Jx1lvmG+xSxGUNyUFfJLzUf0bu2mFJ8GfPdm+T1BhlTA1TJkAI+vpItkVBGj3qvHpv7qImJuxnlTgxLjEeCh9T8fVqnB+IfK66aylyBuXD7wpLtDvjFaLmTq1FQ49cWzuNkSvUGrkTVb559dH/GXHGEOLJhkiF9zyJDNUqPEdjjolJKoYT9AYFYGBHoXDKsLh0sX8pAl5WVP07nHOMQVsAD7Ge+6Ri2YZ+JbvtEnzFl47z5NQktr07KDdjYVZ9wiUiaAVZsMF1DoLhbvfakavm4Tvm9vWWl79Qt8d4w27uyDA3yB9Mo5fQrLnVQ0dVGb+StgGidAG2gceixsocMnbNdEpIdObpjCWuGvaZcXRwPXBJ+0aa24I1wEQxnjcR5wXWWOoyXynsEWHZMuRIoOhnYJ0qfbY482CNcPe7iavc3sxdZwvkqJe10k9bRGMw/O4vL6z1MeqHwKpBZIC7k6paplybA/ePzx0/oNnZNWXofOuR/u6B6mi0rRUYvWFw4MTPTMkSTJpbTyn+IKCs1mZtrdAYs2bLlMd04uHMm+IYQsN/wIwbTqe2dhacgOfxfUVJkqWfHNSqpuMd5KTqAay1Utyyziglp7Xqpxei6Q/CKC9AVUzfscVjbmICXwtY1ACmFln7zwACvjL3w== X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4cde846-e206-4cf6-0533-08d8648d062f X-MS-Exchange-CrossTenant-AuthSource: DM6PR13MB3451.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2020 15:33:33.1375 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OWYzfbzJzvgHYqOE1yl/+UP7d6uaA3zDXnboOMyCCFMPewGI8/TB40KMwH2uOs4W9zIH3XvRON3OCFjZBYbx2w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR13MB2412 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert device tree bindings for SiFive's PLIC to YAML format Signed-off-by: Sagar Kadam --- .../interrupt-controller/sifive,plic-1.0.0.txt | 58 ------------- .../interrupt-controller/sifive,plic-1.0.0.yaml | 97 ++++++++++++++++++++++ 2 files changed, 97 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt deleted file mode 100644 index 6adf7a6..0000000 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt +++ /dev/null @@ -1,58 +0,0 @@ -SiFive Platform-Level Interrupt Controller (PLIC) -------------------------------------------------- - -SiFive SOCs include an implementation of the Platform-Level Interrupt Controller -(PLIC) high-level specification in the RISC-V Privileged Architecture -specification. The PLIC connects all external interrupts in the system to all -hart contexts in the system, via the external interrupt source in each hart. - -A hart context is a privilege mode in a hardware execution thread. For example, -in an 4 core system with 2-way SMT, you have 8 harts and probably at least two -privilege modes per hart; machine mode and supervisor mode. - -Each interrupt can be enabled on per-context basis. Any context can claim -a pending enabled interrupt and then release it once it has been handled. - -Each interrupt has a configurable priority. Higher priority interrupts are -serviced first. Each context can specify a priority threshold. Interrupts -with priority below this threshold will not cause the PLIC to raise its -interrupt line leading to the context. - -While the PLIC supports both edge-triggered and level-triggered interrupts, -interrupt handlers are oblivious to this distinction and therefore it is not -specified in the PLIC device-tree binding. - -While the RISC-V ISA doesn't specify a memory layout for the PLIC, the -"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that -contains a specific memory layout, which is documented in chapter 8 of the -SiFive U5 Coreplex Series Manual . - -Required properties: -- compatible : "sifive,plic-1.0.0" and a string identifying the actual - detailed implementation in case that specific bugs need to be worked around. -- #address-cells : should be <0> or more. -- #interrupt-cells : should be <1> or more. -- interrupt-controller : Identifies the node as an interrupt controller. -- reg : Should contain 1 register range (address and length). -- interrupts-extended : Specifies which contexts are connected to the PLIC, - with "-1" specifying that a context is not present. Each node pointed - to should be a riscv,cpu-intc node, which has a riscv node as parent. -- riscv,ndev: Specifies how many external interrupts are supported by - this controller. - -Example: - - plic: interrupt-controller@c000000 { - #address-cells = <0>; - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; - interrupt-controller; - interrupts-extended = < - &cpu0-intc 11 - &cpu1-intc 11 &cpu1-intc 9 - &cpu2-intc 11 &cpu2-intc 9 - &cpu3-intc 11 &cpu3-intc 9 - &cpu4-intc 11 &cpu4-intc 9>; - reg = <0xc000000 0x4000000>; - riscv,ndev = <10>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml new file mode 100644 index 0000000..b9a61c9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Platform-Level Interrupt Controller (PLIC) + +description: + SiFive SOCs include an implementation of the Platform-Level Interrupt Controller + (PLIC) high-level specification in the RISC-V Privileged Architecture + specification. The PLIC connects all external interrupts in the system to all + hart contexts in the system, via the external interrupt source in each hart. + + A hart context is a privilege mode in a hardware execution thread. For example, + in an 4 core system with 2-way SMT, you have 8 harts and probably at least two + privilege modes per hart; machine mode and supervisor mode. + + Each interrupt can be enabled on per-context basis. Any context can claim + a pending enabled interrupt and then release it once it has been handled. + + Each interrupt has a configurable priority. Higher priority interrupts are + serviced first. Each context can specify a priority threshold. Interrupts + with priority below this threshold will not cause the PLIC to raise its + interrupt line leading to the context. + + While the PLIC supports both edge-triggered and level-triggered interrupts, + interrupt handlers are oblivious to this distinction and therefore it is not + specified in the PLIC device-tree binding. + + While the RISC-V ISA doesn't specify a memory layout for the PLIC, the + "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that + contains a specific memory layout, which is documented in chapter 8 of the + SiFive U5 Coreplex Series Manual . + +maintainers: + - Sagar Kadam + - Paul Walmsley + - Palmer Dabbelt + +properties: + compatible: + items: + - const: sifive,fu540-c000-plic + - const: sifive,plic-1.0.0 + + reg: + maxItems: 1 + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + description: + Specifies which contexts are connected to the PLIC, with "-1" specifying + that a context is not present. Each node pointed to should be a + riscv,cpu-intc node, which has a riscv node as parent. + + riscv,ndev: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + Specifies how many external interrupts are supported by this controller. + +required: + - compatible + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + - reg + - interrupts-extended + - riscv,ndev + +additionalProperties: false + +examples: + - | + plic: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + reg = <0xc000000 0x4000000>; + riscv,ndev = <10>; + }; From patchwork Tue Sep 29 15:32:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 11806299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78D4D112C for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=sifive.com; Received: from DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) by DM6PR13MB2412.namprd13.prod.outlook.com (2603:10b6:5:c3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.14; Tue, 29 Sep 2020 15:33:41 +0000 Received: from DM6PR13MB3451.namprd13.prod.outlook.com ([fe80::a48a:1f7c:267c:876]) by DM6PR13MB3451.namprd13.prod.outlook.com ([fe80::a48a:1f7c:267c:876%7]) with mapi id 15.20.3433.032; Tue, 29 Sep 2020 15:33:41 +0000 From: Sagar Kadam To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, aou@eecs.berkeley.edu, yash.shah@sifive.com, Sagar Kadam Subject: [PATCH v2 3/3] dt-bindings: riscv: convert pwm bindings to json-schema Date: Tue, 29 Sep 2020 21:02:11 +0530 Message-Id: <1601393531-2402-4-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> References: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) To DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by SG2PR02CA0101.apcprd02.prod.outlook.com (2603:1096:4:92::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3433.32 via Frontend Transport; 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Signed-off-by: Sagar Kadam --- .../devicetree/bindings/pwm/pwm-sifive.txt | 33 ----------- .../devicetree/bindings/pwm/pwm-sifive.yaml | 69 ++++++++++++++++++++++ 2 files changed, 69 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt deleted file mode 100644 index 3d1dd7b0..0000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt +++ /dev/null @@ -1,33 +0,0 @@ -SiFive PWM controller - -Unlike most other PWM controllers, the SiFive PWM controller currently only -supports one period for all channels in the PWM. All PWMs need to run at -the same period. The period also has significant restrictions on the values -it can achieve, which the driver rounds to the nearest achievable period. -PWM RTL that corresponds to the IP block version numbers can be found -here: - -https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm - -Required properties: -- compatible: Should be "sifive,-pwm" and "sifive,pwm". - Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive - PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the - SiFive PWM v0 IP block with no chip integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details. -- reg: physical base address and length of the controller's registers -- clocks: Should contain a clock identifier for the PWM's parent clock. -- #pwm-cells: Should be 3. See pwm.yaml in this directory - for a description of the cell format. -- interrupts: one interrupt per PWM channel - -Examples: - -pwm: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - clocks = <&tlclk>; - interrupt-parent = <&plic>; - interrupts = <42 43 44 45>; - #pwm-cells = <3>; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml new file mode 100644 index 0000000..5ac2527 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive PWM controller + +maintainers: + - Yash Shah + - Sagar Kadam + - Paul Walmsley + +description: + Unlike most other PWM controllers, the SiFive PWM controller currently + only supports one period for all channels in the PWM. All PWMs need to + run at the same period. The period also has significant restrictions on + the values it can achieve, which the driver rounds to the nearest + achievable period. PWM RTL that corresponds to the IP block version + numbers can be found here - + + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm + +properties: + compatible: + items: + - const: sifive,fu540-c000-pwm + - const: sifive,pwm0 + description: + Should be "sifive,-pwm" and "sifive,pwm". Supported + compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 + as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the + SiFive PWM v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + + interrupts: + maxItems: 4 + description: + Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator. + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + - interrupts + +additionalProperties: false + +examples: + - | + pwm: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x10020000 0x1000>; + clocks = <&tlclk>; + interrupt-parent = <&plic>; + interrupts = <42>, <43>, <44>, <45>; + #pwm-cells = <3>; + };