From patchwork Wed Sep 30 02:21:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11807721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DFA8139F for ; Wed, 30 Sep 2020 02:22:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3CE820773 for ; Wed, 30 Sep 2020 02:22:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="X0DL28XR"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="R1Mi678o" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D3CE820773 Authentication-Results: mail.kernel.org; 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Tue, 29 Sep 2020 18:22:05 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 19:22:02 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Sep 2020 10:21:59 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 10:22:02 +0800 From: Crystal Guo To: , , Subject: [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas Date: Wed, 30 Sep 2020 10:21:57 +0800 Message-ID: <20200930022159.5559-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930022159.5559-1-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200929_222217_449916_7C2F73BE X-CRM114-Status: GOOD ( 13.05 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, Crystal Guo , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, s-anna@ti.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add a YAML documentation for Mediatek, which uses ti reset-controller driver directly. The TI reset controller provides a common reset management, and is suitable for Mediatek SoCs. Signed-off-by: Crystal Guo --- .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml new file mode 100644 index 000000000000..7871550c3c69 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Reset Controller + +maintainers: + - Crystal Guo + +description: + The bindings describe the reset-controller for Mediatek SoCs, + which is based on TI reset controller. For more detail, please + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +properties: + compatible: + const: mediatek,syscon-reset + + '#reset-cells': + const: 1 + + mediatek,reset-bits: + description: > + Contains the reset control register information, please refer to + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +required: + - compatible + - '#reset-cells' + - mediatek,reset-bits + +additionalProperties: false + +examples: + - | + #include + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,syscon-reset"; + #reset-cells = <1>; + mediatek,reset-bits = < + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; From patchwork Wed Sep 30 02:21:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11807737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A9FA112C for ; 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Wed, 30 Sep 2020 10:22:03 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 10:22:03 +0800 From: Crystal Guo To: , , Subject: [v6,2/3] reset-controller: ti: introduce a new reset handler Date: Wed, 30 Sep 2020 10:21:58 +0800 Message-ID: <20200930022159.5559-3-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930022159.5559-1-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200929_223213_411199_2445D02B X-CRM114-Status: GOOD ( 17.03 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, Crystal Guo , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, s-anna@ti.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Such as reset-qcom-aoss.c, it integrates assert and deassert together by 'reset' method. MTK Socs also need this method to perform reset. Signed-off-by: Crystal Guo Reviewed-by: Ikjoon Jang --- drivers/reset/reset-ti-syscon.c | 40 ++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index a2635c21db7f..5d1f8306cd4f 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -15,15 +15,22 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include #include #include #include #include +struct mediatek_reset_data { + unsigned char *reset_bits; + unsigned int reset_duration_us; +}; + /** * struct ti_syscon_reset_control - reset control structure * @assert_offset: reset assert control register offset from syscon base @@ -56,6 +63,7 @@ struct ti_syscon_reset_data { struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + const struct mediatek_reset_data *reset_data; }; #define to_ti_syscon_reset_data(rcdev) \ @@ -158,9 +166,29 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev); + int ret; + + if (data->reset_data) { + ret = ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + usleep_range(data->reset_data->reset_duration_us, + data->reset_data->reset_duration_us * 2); + + return ti_syscon_reset_deassert(rcdev, id); + } else { + return -ENOTSUPP; + } +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, + .reset = ti_syscon_reset, .status = ti_syscon_reset_status, }; @@ -182,7 +210,11 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - list = of_get_property(np, "ti,reset-bits", &size); + data->reset_data = of_device_get_match_data(&pdev->dev); + if (data->reset_data) + list = of_get_property(np, data->reset_data->reset_bits, &size); + else + list = of_get_property(np, "ti,reset-bits", &size); if (!list || (size / sizeof(*list)) % 7 != 0) { dev_err(dev, "invalid DT reset description\n"); return -EINVAL; @@ -217,8 +249,14 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) return devm_reset_controller_register(dev, &data->rcdev); } +static const struct mediatek_reset_data mtk_reset_data = { + .reset_bits = "mediatek,reset-bits", + .reset_duration_us = 10, +}; + static const struct of_device_id ti_syscon_reset_of_match[] = { { .compatible = "ti,syscon-reset", }, + { .compatible = "mediatek,syscon-reset", .data = &mtk_reset_data}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match); From patchwork Wed Sep 30 02:21:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11807719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9043C139F for ; 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Wed, 30 Sep 2020 10:22:00 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 10:22:04 +0800 From: Crystal Guo To: , , Subject: [v6, 3/3] reset-controller: ti: force the write operation when assert or deassert Date: Wed, 30 Sep 2020 10:21:59 +0800 Message-ID: <20200930022159.5559-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930022159.5559-1-crystal.guo@mediatek.com> References: <20200930022159.5559-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: BA75B31640D9C6D0159B7662252A7C2BDC31A2ACBB88105A60464EEC1CA8992A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200929_222216_484927_080F4024 X-CRM114-Status: GOOD ( 11.51 ) X-Spam-Score: 1.1 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines 1.3 RDNS_NONE Delivered to internal network by a host with no rDNS X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, Crystal Guo , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, s-anna@ti.com, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Force the write operation in case the read already happens to return the correct value. Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index 5d1f8306cd4f..c34394f1e9e2 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -97,7 +97,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -128,7 +128,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /**