From patchwork Wed Sep 30 15:27:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809665 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6F47618 for ; Wed, 30 Sep 2020 15:30:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD6E321D7F for ; Wed, 30 Sep 2020 15:30:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731200AbgI3Pag (ORCPT ); Wed, 30 Sep 2020 11:30:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730632AbgI3P3B (ORCPT ); Wed, 30 Sep 2020 11:29:01 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4172C0613D0 for ; Wed, 30 Sep 2020 08:29:00 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 03E5D634C89 for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 001/100] smiapp: Add CCS register definitions and limits Date: Wed, 30 Sep 2020 18:27:19 +0300 Message-Id: <20200930152858.8471-2-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add register definitions of the MIPI CCS 1.1 standard. Also add ccs-os.h header that contains Linux headers to be included. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/Makefile | 3 +- drivers/media/i2c/smiapp/ccs-limits.c | 239 +++++++ drivers/media/i2c/smiapp/ccs-limits.h | 258 +++++++ drivers/media/i2c/smiapp/ccs-os.h | 15 + drivers/media/i2c/smiapp/ccs-regs.h | 953 ++++++++++++++++++++++++++ 5 files changed, 1467 insertions(+), 1 deletion(-) create mode 100644 drivers/media/i2c/smiapp/ccs-limits.c create mode 100644 drivers/media/i2c/smiapp/ccs-limits.h create mode 100644 drivers/media/i2c/smiapp/ccs-os.h create mode 100644 drivers/media/i2c/smiapp/ccs-regs.h diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile index 86f57a43f8e8..b4f0bcc037b8 100644 --- a/drivers/media/i2c/smiapp/Makefile +++ b/drivers/media/i2c/smiapp/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only smiapp-objs += smiapp-core.o smiapp-regs.o \ - smiapp-quirk.o smiapp-limits.o + smiapp-quirk.o smiapp-limits.o \ + ccs-limits.o obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o ccflags-y += -I $(srctree)/drivers/media/i2c diff --git a/drivers/media/i2c/smiapp/ccs-limits.c b/drivers/media/i2c/smiapp/ccs-limits.c new file mode 100644 index 000000000000..f5511789ac83 --- /dev/null +++ b/drivers/media/i2c/smiapp/ccs-limits.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause +/* Copyright (C) 2019--2020 Intel Corporation */ + +#include "ccs-limits.h" +#include "ccs-regs.h" + +const struct ccs_limit ccs_limits[] = { + { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" }, + { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" }, + { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" }, + { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" }, + { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" }, + { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" }, + { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" }, + { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" }, + { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" }, + { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" }, + { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" }, + { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" }, + { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" }, + { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" }, + { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" }, + { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" }, + { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" }, + { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" }, + { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" }, + { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" }, + { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" }, + { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" }, + { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" }, + { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" }, + { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" }, + { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" }, + { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" }, + { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" }, + { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" }, + { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" }, + { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" }, + { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" }, + { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" }, + { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" }, + { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" }, + { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" }, + { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" }, + { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" }, + { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" }, + { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" }, + { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" }, + { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" }, + { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" }, + { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" }, + { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" }, + { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" }, + { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" }, + { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" }, + { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" }, + { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" }, + { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" }, + { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" }, + { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" }, + { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" }, + { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" }, + { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" }, + { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" }, + { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" }, + { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" }, + { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" }, + { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" }, + { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" }, + { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" }, + { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" }, + { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" }, + { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" }, + { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" }, + { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" }, + { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" }, + { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" }, + { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" }, + { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" }, + { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" }, + { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" }, + { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" }, + { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" }, + { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" }, + { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" }, + { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" }, + { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" }, + { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" }, + { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" }, + { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" }, + { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" }, + { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" }, + { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" }, + { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" }, + { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" }, + { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" }, + { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" }, + { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" }, + { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" }, + { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" }, + { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" }, + { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" }, + { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" }, + { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" }, + { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" }, + { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" }, + { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" }, + { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" }, + { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" }, + { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" }, + { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" }, + { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" }, + { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" }, + { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" }, + { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" }, + { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" }, + { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" }, + { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" }, + { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" }, + { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" }, + { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" }, + { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" }, + { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" }, + { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" }, + { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" }, + { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" }, + { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" }, + { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" }, + { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" }, + { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" }, + { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" }, + { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" }, + { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" }, + { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" }, + { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" }, + { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" }, + { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" }, + { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" }, + { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" }, + { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" }, + { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" }, + { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" }, + { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" }, + { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" }, + { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" }, + { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" }, + { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" }, + { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" }, + { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" }, + { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" }, + { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" }, + { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" }, + { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" }, + { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" }, + { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" }, + { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" }, + { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" }, + { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" }, + { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" }, + { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" }, + { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" }, + { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" }, + { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" }, + { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" }, + { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" }, + { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" }, + { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" }, + { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" }, + { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" }, + { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" }, + { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" }, + { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" }, + { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" }, + { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" }, + { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" }, + { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" }, + { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" }, + { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" }, + { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" }, + { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" }, + { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" }, + { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" }, + { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" }, + { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" }, + { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" }, + { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" }, + { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" }, + { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" }, + { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" }, + { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" }, + { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" }, + { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" }, + { CCS_R_DPHY_SF, 1, 0, "dphy_sf" }, + { CCS_R_CPHY_SF, 1, 0, "cphy_sf" }, + { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" }, + { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" }, + { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" }, + { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" }, + { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" }, + { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" }, + { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" }, + { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" }, + { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" }, + { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" }, + { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" }, + { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" }, + { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" }, + { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" }, + { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" }, + { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" }, + { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" }, + { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" }, + { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" }, + { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" }, + { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" }, + { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" }, + { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" }, + { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" }, + { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" }, + { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" }, + { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" }, + { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" }, + { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" }, + { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" }, + { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" }, + { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" }, + { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" }, + { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" }, + { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" }, + { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" }, + { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" }, + { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" }, + { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" }, + { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" }, + { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" }, + { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" }, + { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" }, + { 0 } /* Guardian */ +}; diff --git a/drivers/media/i2c/smiapp/ccs-limits.h b/drivers/media/i2c/smiapp/ccs-limits.h new file mode 100644 index 000000000000..0da422b889a0 --- /dev/null +++ b/drivers/media/i2c/smiapp/ccs-limits.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +/* Copyright (C) 2019--2020 Intel Corporation */ + +#ifndef __CCS_LIMITS_H__ +#define __CCS_LIMITS_H__ + +#include "ccs-os.h" + +struct ccs_limit { + uint32_t reg; + uint16_t size; + uint16_t flags; + const char *name; +}; + +#define CCS_L_FL_SAME_REG (1U << 0) + +extern const struct ccs_limit ccs_limits[]; + +#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0 +#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1 +#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2 +#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2) +#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3 +#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4) +#define CCS_L_ANALOG_GAIN_CAPABILITY 4 +#define CCS_L_ANALOG_GAIN_CODE_MIN 5 +#define CCS_L_ANALOG_GAIN_CODE_MAX 6 +#define CCS_L_ANALOG_GAIN_CODE_STEP 7 +#define CCS_L_ANALOG_GAIN_TYPE 8 +#define CCS_L_ANALOG_GAIN_M0 9 +#define CCS_L_ANALOG_GAIN_C0 10 +#define CCS_L_ANALOG_GAIN_M1 11 +#define CCS_L_ANALOG_GAIN_C1 12 +#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13 +#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14 +#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15 +#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16 +#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17 +#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18 +#define CCS_L_DATA_FORMAT_MODEL_TYPE 19 +#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20 +#define CCS_L_DATA_FORMAT_DESCRIPTOR 21 +#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2) +#define CCS_L_INTEGRATION_TIME_CAPABILITY 22 +#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23 +#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24 +#define CCS_L_FINE_INTEGRATION_TIME_MIN 25 +#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26 +#define CCS_L_DIGITAL_GAIN_CAPABILITY 27 +#define CCS_L_DIGITAL_GAIN_MIN 28 +#define CCS_L_DIGITAL_GAIN_MAX 29 +#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30 +#define CCS_L_PEDESTAL_CAPABILITY 31 +#define CCS_L_ADC_CAPABILITY 32 +#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33 +#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34 +#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35 +#define CCS_L_MIN_PRE_PLL_CLK_DIV 36 +#define CCS_L_MAX_PRE_PLL_CLK_DIV 37 +#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38 +#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39 +#define CCS_L_MIN_PLL_MULTIPLIER 40 +#define CCS_L_MAX_PLL_MULTIPLIER 41 +#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42 +#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43 +#define CCS_L_MIN_VT_SYS_CLK_DIV 44 +#define CCS_L_MAX_VT_SYS_CLK_DIV 45 +#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46 +#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47 +#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48 +#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49 +#define CCS_L_MIN_VT_PIX_CLK_DIV 50 +#define CCS_L_MAX_VT_PIX_CLK_DIV 51 +#define CCS_L_CLOCK_CALCULATION 52 +#define CCS_L_NUM_OF_VT_LANES 53 +#define CCS_L_NUM_OF_OP_LANES 54 +#define CCS_L_OP_BITS_PER_LANE 55 +#define CCS_L_MIN_FRAME_LENGTH_LINES 56 +#define CCS_L_MAX_FRAME_LENGTH_LINES 57 +#define CCS_L_MIN_LINE_LENGTH_PCK 58 +#define CCS_L_MAX_LINE_LENGTH_PCK 59 +#define CCS_L_MIN_LINE_BLANKING_PCK 60 +#define CCS_L_MIN_FRAME_BLANKING_LINES 61 +#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62 +#define CCS_L_TIMING_MODE_CAPABILITY 63 +#define CCS_L_FRAME_MARGIN_MAX_VALUE 64 +#define CCS_L_FRAME_MARGIN_MIN_VALUE 65 +#define CCS_L_GAIN_DELAY_TYPE 66 +#define CCS_L_MIN_OP_SYS_CLK_DIV 67 +#define CCS_L_MAX_OP_SYS_CLK_DIV 68 +#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69 +#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70 +#define CCS_L_MIN_OP_PIX_CLK_DIV 71 +#define CCS_L_MAX_OP_PIX_CLK_DIV 72 +#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73 +#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74 +#define CCS_L_X_ADDR_MIN 75 +#define CCS_L_Y_ADDR_MIN 76 +#define CCS_L_X_ADDR_MAX 77 +#define CCS_L_Y_ADDR_MAX 78 +#define CCS_L_MIN_X_OUTPUT_SIZE 79 +#define CCS_L_MIN_Y_OUTPUT_SIZE 80 +#define CCS_L_MAX_X_OUTPUT_SIZE 81 +#define CCS_L_MAX_Y_OUTPUT_SIZE 82 +#define CCS_L_X_ADDR_START_DIV_CONSTANT 83 +#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84 +#define CCS_L_X_ADDR_END_DIV_CONSTANT 85 +#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86 +#define CCS_L_X_SIZE_DIV 87 +#define CCS_L_Y_SIZE_DIV 88 +#define CCS_L_X_OUTPUT_DIV 89 +#define CCS_L_Y_OUTPUT_DIV 90 +#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91 +#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92 +#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93 +#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94 +#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95 +#define CCS_L_MIN_OP_PLL_MULTIPLIER 96 +#define CCS_L_MAX_OP_PLL_MULTIPLIER 97 +#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98 +#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99 +#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100 +#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101 +#define CCS_L_MIN_EVEN_INC 102 +#define CCS_L_MIN_ODD_INC 103 +#define CCS_L_MAX_EVEN_INC 104 +#define CCS_L_MAX_ODD_INC 105 +#define CCS_L_AUX_SUBSAMP_CAPABILITY 106 +#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107 +#define CCS_L_MONOCHROME_CAPABILITY 108 +#define CCS_L_PIXEL_READOUT_CAPABILITY 109 +#define CCS_L_MIN_EVEN_INC_MONO 110 +#define CCS_L_MAX_EVEN_INC_MONO 111 +#define CCS_L_MIN_ODD_INC_MONO 112 +#define CCS_L_MAX_ODD_INC_MONO 113 +#define CCS_L_MIN_EVEN_INC_BC2 114 +#define CCS_L_MAX_EVEN_INC_BC2 115 +#define CCS_L_MIN_ODD_INC_BC2 116 +#define CCS_L_MAX_ODD_INC_BC2 117 +#define CCS_L_MIN_EVEN_INC_MONO_BC2 118 +#define CCS_L_MAX_EVEN_INC_MONO_BC2 119 +#define CCS_L_MIN_ODD_INC_MONO_BC2 120 +#define CCS_L_MAX_ODD_INC_MONO_BC2 121 +#define CCS_L_SCALING_CAPABILITY 122 +#define CCS_L_SCALER_M_MIN 123 +#define CCS_L_SCALER_M_MAX 124 +#define CCS_L_SCALER_N_MIN 125 +#define CCS_L_SCALER_N_MAX 126 +#define CCS_L_DIGITAL_CROP_CAPABILITY 127 +#define CCS_L_HDR_CAPABILITY_1 128 +#define CCS_L_MIN_HDR_BIT_DEPTH 129 +#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130 +#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131 +#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n) +#define CCS_L_HDR_CAPABILITY_2 132 +#define CCS_L_MAX_HDR_BIT_DEPTH 133 +#define CCS_L_USL_SUPPORT_CAPABILITY 134 +#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135 +#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136 +#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137 +#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138 +#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139 +#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140 +#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141 +#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142 +#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143 +#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144 +#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145 +#define CCS_L_COMPRESSION_CAPABILITY 146 +#define CCS_L_TEST_MODE_CAPABILITY 147 +#define CCS_L_PN9_DATA_FORMAT1 148 +#define CCS_L_PN9_DATA_FORMAT2 149 +#define CCS_L_PN9_DATA_FORMAT3 150 +#define CCS_L_PN9_DATA_FORMAT4 151 +#define CCS_L_PN9_MISC_CAPABILITY 152 +#define CCS_L_TEST_PATTERN_CAPABILITY 153 +#define CCS_L_PATTERN_SIZE_DIV_M1 154 +#define CCS_L_FIFO_SUPPORT_CAPABILITY 155 +#define CCS_L_PHY_CTRL_CAPABILITY 156 +#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157 +#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158 +#define CCS_L_FAST_STANDBY_CAPABILITY 159 +#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160 +#define CCS_L_DATA_TYPE_CAPABILITY 161 +#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162 +#define CCS_L_EMB_DATA_CAPABILITY 163 +#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164 +#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4) +#define CCS_L_TEMP_SENSOR_CAPABILITY 165 +#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166 +#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4) +#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167 +#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168 +#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169 +#define CCS_L_DPHY_SSC_CAPABILITY 170 +#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171 +#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172 +#define CCS_L_PHY_CTRL_CAPABILITY_2 173 +#define CCS_L_LRTE_CPHY_CAPABILITY 174 +#define CCS_L_LRTE_DPHY_CAPABILITY 175 +#define CCS_L_ALPS_CAPABILITY_DPHY 176 +#define CCS_L_ALPS_CAPABILITY_CPHY 177 +#define CCS_L_SCRAMBLING_CAPABILITY 178 +#define CCS_L_DPHY_MANUAL_CONSTANT 179 +#define CCS_L_CPHY_MANUAL_CONSTANT 180 +#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181 +#define CCS_L_PHY_CTRL_CAPABILITY_3 182 +#define CCS_L_DPHY_SF 183 +#define CCS_L_CPHY_SF 184 +#define CCS_L_DPHY_LIMITS_1 185 +#define CCS_L_DPHY_LIMITS_2 186 +#define CCS_L_DPHY_LIMITS_3 187 +#define CCS_L_DPHY_LIMITS_4 188 +#define CCS_L_DPHY_LIMITS_5 189 +#define CCS_L_DPHY_LIMITS_6 190 +#define CCS_L_CPHY_LIMITS_1 191 +#define CCS_L_CPHY_LIMITS_2 192 +#define CCS_L_CPHY_LIMITS_3 193 +#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194 +#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195 +#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196 +#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197 +#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198 +#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199 +#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200 +#define CCS_L_BINNING_CAPABILITY 201 +#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202 +#define CCS_L_BINNING_SUB_TYPES 203 +#define CCS_L_BINNING_SUB_TYPE 204 +#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n) +#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205 +#define CCS_L_BINNING_SUB_TYPES_MONO 206 +#define CCS_L_BINNING_SUB_TYPE_MONO 207 +#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n) +#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208 +#define CCS_L_SHADING_CORRECTION_CAPABILITY 209 +#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210 +#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211 +#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212 +#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213 +#define CCS_L_NF_CAPABILITY 214 +#define CCS_L_OB_READOUT_CAPABILITY 215 +#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216 +#define CCS_L_CFA_PATTERN_CAPABILITY 217 +#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218 +#define CCS_L_FLASH_MODE_CAPABILITY 219 +#define CCS_L_SA_STROBE_MODE_CAPABILITY 220 +#define CCS_L_RESET_MAX_DELAY 221 +#define CCS_L_RESET_MIN_TIME 222 +#define CCS_L_PDAF_CAPABILITY_1 223 +#define CCS_L_PDAF_CAPABILITY_2 224 +#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225 +#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226 +#define CCS_L_BRACKETING_LUT_SIZE 227 +#define CCS_L_LAST 228 + +#endif /* __CCS_LIMITS_H__ */ diff --git a/drivers/media/i2c/smiapp/ccs-os.h b/drivers/media/i2c/smiapp/ccs-os.h new file mode 100644 index 000000000000..f2445733f5d5 --- /dev/null +++ b/drivers/media/i2c/smiapp/ccs-os.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright 2020 Intel Corporation */ + +#include +#include +#include +#include +#include +#include + +typedef struct device * printf_ctx; +#define os_printf dev_dbg +#define os_calloc(size) kvcalloc(1, size, GFP_KERNEL) +#define os_free kvfree +#define align2 ALIGN diff --git a/drivers/media/i2c/smiapp/ccs-regs.h b/drivers/media/i2c/smiapp/ccs-regs.h new file mode 100644 index 000000000000..039d65930319 --- /dev/null +++ b/drivers/media/i2c/smiapp/ccs-regs.h @@ -0,0 +1,953 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +/* Copyright (C) 2019--2020 Intel Corporation */ + +#ifndef __CCS_REGS_H__ +#define __CCS_REGS_H__ + +#define CCS_FL_BASE 16 +#define CCS_FL_16BIT (1U << CCS_FL_BASE) +#define CCS_FL_32BIT (1U << (CCS_FL_BASE + 1)) +#define CCS_FL_FLOAT_IREAL (1U << (CCS_FL_BASE + 2)) +#define CCS_FL_IREAL (1U << (CCS_FL_BASE + 3)) + +#define CCS_R_ADDR(r) ((r) & 0xffff) + +#define CCS_R_MODULE_MODEL_ID (0x0000 | CCS_FL_16BIT) +#define CCS_R_MODULE_REVISION_NUMBER_MAJOR 0x0002 +#define CCS_R_FRAME_COUNT 0x0005 +#define CCS_R_PIXEL_ORDER 0x0006 +#define CCS_PIXEL_ORDER_GRBG 0U +#define CCS_PIXEL_ORDER_RGGB 1U +#define CCS_PIXEL_ORDER_BGGR 2U +#define CCS_PIXEL_ORDER_GBRG 3U +#define CCS_R_MIPI_CCS_VERSION 0x0007 +#define CCS_MIPI_CCS_VERSION_V1_0 0x10 +#define CCS_MIPI_CCS_VERSION_V1_1 0x11 +#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U +#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0 +#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U +#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf +#define CCS_R_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT) +#define CCS_R_MODULE_MANUFACTURER_ID (0x000e | CCS_FL_16BIT) +#define CCS_R_MODULE_REVISION_NUMBER_MINOR 0x0010 +#define CCS_R_MODULE_DATE_YEAR 0x0012 +#define CCS_R_MODULE_DATE_MONTH 0x0013 +#define CCS_R_MODULE_DATE_DAY 0x0014 +#define CCS_R_MODULE_DATE_PHASE 0x0015 +#define CCS_MODULE_DATE_PHASE_SHIFT 0U +#define CCS_MODULE_DATE_PHASE_MASK 0x7 +#define CCS_MODULE_DATE_PHASE_TS 0U +#define CCS_MODULE_DATE_PHASE_ES 1U +#define CCS_MODULE_DATE_PHASE_CS 2U +#define CCS_MODULE_DATE_PHASE_MP 3U +#define CCS_R_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT) +#define CCS_R_SENSOR_REVISION_NUMBER 0x0018 +#define CCS_R_SENSOR_FIRMWARE_VERSION 0x001a +#define CCS_R_SERIAL_NUMBER (0x001c | CCS_FL_32BIT) +#define CCS_R_SENSOR_MANUFACTURER_ID (0x0020 | CCS_FL_16BIT) +#define CCS_R_SENSOR_REVISION_NUMBER_16 (0x0022 | CCS_FL_16BIT) +#define CCS_R_FRAME_FORMAT_MODEL_TYPE 0x0040 +#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U +#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U +#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE 0x0041 +#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U +#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf +#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U +#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0 +#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2) +#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U +#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U +#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4) +#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000 +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U +#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U +#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U +#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000 +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U +#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U +#define CCS_R_ANALOG_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT) +#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U +#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U +#define CCS_R_ANALOG_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_TYPE (0x008a | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_M0 (0x008c | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_C0 (0x008e | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_M1 (0x0090 | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_C1 (0x0092 | CCS_FL_16BIT) +#define CCS_R_ANALOG_LINEAR_GAIN_MIN (0x0094 | CCS_FL_16BIT) +#define CCS_R_ANALOG_LINEAR_GAIN_MAX (0x0096 | CCS_FL_16BIT) +#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE (0x0098 | CCS_FL_16BIT) +#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN (0x009a | CCS_FL_16BIT) +#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX (0x009c | CCS_FL_16BIT) +#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE (0x009e | CCS_FL_16BIT) +#define CCS_R_DATA_FORMAT_MODEL_TYPE 0x00c0 +#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U +#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U +#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE 0x00c1 +#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U +#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf +#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U +#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0 +#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2) +#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U +#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U +#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U +#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff +#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U +#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00 +#define CCS_R_MODE_SELECT 0x0100 +#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U +#define CCS_MODE_SELECT_STREAMING 1U +#define CCS_R_IMAGE_ORIENTATION 0x0101 +#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR (1U << 0) +#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP (1U << 1) +#define CCS_R_SOFTWARE_RESET 0x0103 +#define CCS_SOFTWARE_RESET_OFF 0U +#define CCS_SOFTWARE_RESET_ON 1U +#define CCS_R_GROUPED_PARAMETER_HOLD 0x0104 +#define CCS_R_MASK_CORRUPTED_FRAMES 0x0105 +#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U +#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U +#define CCS_R_FAST_STANDBY_CTRL 0x0106 +#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U +#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U +#define CCS_R_CCI_ADDRESS_CTRL 0x0107 +#define CCS_R_2ND_CCI_IF_CTRL 0x0108 +#define CCS_2ND_CCI_IF_CTRL_ENABLE (1U << 0) +#define CCS_2ND_CCI_IF_CTRL_ACK (1U << 1) +#define CCS_R_2ND_CCI_ADDRESS_CTRL 0x0109 +#define CCS_R_CSI_CHANNEL_IDENTIFIER 0x0110 +#define CCS_R_CSI_SIGNALING_MODE 0x0111 +#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U +#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U +#define CCS_R_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT) +#define CCS_R_CSI_LANE_MODE 0x0114 +#define CCS_R_DPCM_FRAME_DT 0x011d +#define CCS_R_BOTTOM_EMBEDDED_DATA_DT 0x011e +#define CCS_R_BOTTOM_EMBEDDED_DATA_VC 0x011f +#define CCS_R_GAIN_MODE 0x0120 +#define CCS_GAIN_MODE_GLOBAL 0U +#define CCS_GAIN_MODE_ALTERNATE 1U +#define CCS_R_ADC_BIT_DEPTH 0x0121 +#define CCS_R_EMB_DATA_CTRL 0x0122 +#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 (1U << 0) +#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 (1U << 1) +#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 (1U << 2) +#define CCS_R_GPIO_TRIG_MODE 0x0130 +#define CCS_R_EXTCLK_FREQUENCY_MHZ (0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL)) +#define CCS_R_TEMP_SENSOR_CTRL 0x0138 +#define CCS_TEMP_SENSOR_CTRL_ENABLE (1U << 0) +#define CCS_R_TEMP_SENSOR_MODE 0x0139 +#define CCS_R_TEMP_SENSOR_OUTPUT 0x013a +#define CCS_R_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT) +#define CCS_R_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT) +#define CCS_R_ANALOG_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT) +#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL (0x0206 | CCS_FL_16BIT) +#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0208 | CCS_FL_16BIT) +#define CCS_R_DIGITAL_GAIN_GLOBAL (0x020e | CCS_FL_16BIT) +#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL (0x0216 | CCS_FL_16BIT) +#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL (0x0218 | CCS_FL_16BIT) +#define CCS_R_HDR_MODE 0x0220 +#define CCS_HDR_MODE_ENABLED (1U << 0) +#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN (1U << 1) +#define CCS_HDR_MODE_UPSCALING (1U << 2) +#define CCS_HDR_MODE_RESET_SYNC (1U << 3) +#define CCS_HDR_MODE_TIMING_MODE (1U << 4) +#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT (1U << 5) +#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN (1U << 6) +#define CCS_R_HDR_RESOLUTION_REDUCTION 0x0221 +#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U +#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf +#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U +#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0 +#define CCS_R_EXPOSURE_RATIO 0x0222 +#define CCS_R_HDR_INTERNAL_BIT_DEPTH 0x0223 +#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME (0x0224 | CCS_FL_16BIT) +#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL (0x0226 | CCS_FL_16BIT) +#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0228 | CCS_FL_16BIT) +#define CCS_R_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT) +#define CCS_R_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT) +#define CCS_R_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT) +#define CCS_R_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT) +#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT) +#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT) +#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT) +#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT) +#define CCS_R_PLL_MODE 0x0310 +#define CCS_PLL_MODE_SHIFT 0U +#define CCS_PLL_MODE_MASK 0x1 +#define CCS_PLL_MODE_SINGLE 0U +#define CCS_PLL_MODE_DUAL 1U +#define CCS_R_OP_PIX_CLK_DIV_REV (0x0312 | CCS_FL_16BIT) +#define CCS_R_OP_SYS_CLK_DIV_REV (0x0314 | CCS_FL_16BIT) +#define CCS_R_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT) +#define CCS_R_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT) +#define CCS_R_X_ADDR_START (0x0344 | CCS_FL_16BIT) +#define CCS_R_Y_ADDR_START (0x0346 | CCS_FL_16BIT) +#define CCS_R_X_ADDR_END (0x0348 | CCS_FL_16BIT) +#define CCS_R_Y_ADDR_END (0x034a | CCS_FL_16BIT) +#define CCS_R_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT) +#define CCS_R_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT) +#define CCS_R_FRAME_LENGTH_CTRL 0x0350 +#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC (1U << 0) +#define CCS_R_TIMING_MODE_CTRL 0x0352 +#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT (1U << 0) +#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE (1U << 1) +#define CCS_R_START_READOUT_RS 0x0353 +#define CCS_START_READOUT_RS_MANUAL_READOUT_START (1U << 0) +#define CCS_R_FRAME_MARGIN (0x0354 | CCS_FL_16BIT) +#define CCS_R_X_EVEN_INC (0x0380 | CCS_FL_16BIT) +#define CCS_R_X_ODD_INC (0x0382 | CCS_FL_16BIT) +#define CCS_R_Y_EVEN_INC (0x0384 | CCS_FL_16BIT) +#define CCS_R_Y_ODD_INC (0x0386 | CCS_FL_16BIT) +#define CCS_R_MONOCHROME_EN 0x0390 +#define CCS_MONOCHROME_EN_ENABLED 0U +#define CCS_R_SCALING_MODE (0x0400 | CCS_FL_16BIT) +#define CCS_SCALING_MODE_NO_SCALING 0U +#define CCS_SCALING_MODE_HORIZONTAL 1U +#define CCS_R_SCALE_M (0x0404 | CCS_FL_16BIT) +#define CCS_R_SCALE_N (0x0406 | CCS_FL_16BIT) +#define CCS_R_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT) +#define CCS_R_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT) +#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT) +#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT) +#define CCS_R_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT) +#define CCS_COMPRESSION_MODE_NONE 0U +#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U +#define CCS_R_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT) +#define CCS_TEST_PATTERN_MODE_NONE 0U +#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U +#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U +#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U +#define CCS_TEST_PATTERN_MODE_PN9 4U +#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U +#define CCS_R_TEST_DATA_RED (0x0602 | CCS_FL_16BIT) +#define CCS_R_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT) +#define CCS_R_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT) +#define CCS_R_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT) +#define CCS_R_VALUE_STEP_SIZE_SMOOTH 0x060a +#define CCS_R_VALUE_STEP_SIZE_QUANTISED 0x060b +#define CCS_R_TCLK_POST 0x0800 +#define CCS_R_THS_PREPARE 0x0801 +#define CCS_R_THS_ZERO_MIN 0x0802 +#define CCS_R_THS_TRAIL 0x0803 +#define CCS_R_TCLK_TRAIL_MIN 0x0804 +#define CCS_R_TCLK_PREPARE 0x0805 +#define CCS_R_TCLK_ZERO 0x0806 +#define CCS_R_TLPX 0x0807 +#define CCS_R_PHY_CTRL 0x0808 +#define CCS_PHY_CTRL_AUTO 0U +#define CCS_PHY_CTRL_UI 1U +#define CCS_PHY_CTRL_MANUAL 2U +#define CCS_R_TCLK_POST_EX (0x080a | CCS_FL_16BIT) +#define CCS_R_THS_PREPARE_EX (0x080c | CCS_FL_16BIT) +#define CCS_R_THS_ZERO_MIN_EX (0x080e | CCS_FL_16BIT) +#define CCS_R_THS_TRAIL_EX (0x0810 | CCS_FL_16BIT) +#define CCS_R_TCLK_TRAIL_MIN_EX (0x0812 | CCS_FL_16BIT) +#define CCS_R_TCLK_PREPARE_EX (0x0814 | CCS_FL_16BIT) +#define CCS_R_TCLK_ZERO_EX (0x0816 | CCS_FL_16BIT) +#define CCS_R_TLPX_EX (0x0818 | CCS_FL_16BIT) +#define CCS_R_REQUESTED_LINK_RATE (0x0820 | CCS_FL_32BIT) +#define CCS_R_DPHY_EQUALIZATION_MODE 0x0824 +#define CCS_DPHY_EQUALIZATION_MODE_EQ2 (1U << 0) +#define CCS_R_PHY_EQUALIZATION_CTRL 0x0825 +#define CCS_PHY_EQUALIZATION_CTRL_ENABLE (1U << 0) +#define CCS_R_DPHY_PREAMBLE_CTRL 0x0826 +#define CCS_DPHY_PREAMBLE_CTRL_ENABLE (1U << 0) +#define CCS_R_DPHY_PREAMBLE_LENGTH 0x0826 +#define CCS_R_PHY_SSC_CTRL 0x0828 +#define CCS_PHY_SSC_CTRL_ENABLE (1U << 0) +#define CCS_R_MANUAL_LP_CTRL 0x0829 +#define CCS_MANUAL_LP_CTRL_ENABLE (1U << 0) +#define CCS_R_TWAKEUP 0x082a +#define CCS_R_TINIT 0x082b +#define CCS_R_THS_EXIT 0x082c +#define CCS_R_THS_EXIT_EX (0x082e | CCS_FL_16BIT) +#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL 0x0830 +#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING (1U << 0) +#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL 0x0831 +#define CCS_R_PHY_INIT_CALIBRATION_CTRL 0x0832 +#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START (1U << 0) +#define CCS_R_DPHY_CALIBRATION_MODE 0x0833 +#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE (1U << 0) +#define CCS_R_CPHY_CALIBRATION_MODE 0x0834 +#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U +#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U +#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U +#define CCS_R_T3_CALPREAMBLE_LENGTH 0x0835 +#define CCS_R_T3_CALPREAMBLE_LENGTH_PER 0x0836 +#define CCS_R_T3_CALALTSEQ_LENGTH 0x0837 +#define CCS_R_T3_CALALTSEQ_LENGTH_PER 0x0838 +#define CCS_R_FM2_INIT_SEED (0x083a | CCS_FL_16BIT) +#define CCS_R_T3_CALUDEFSEQ_LENGTH (0x083c | CCS_FL_16BIT) +#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER (0x083e | CCS_FL_16BIT) +#define CCS_R_TGR_PREAMBLE_LENGTH 0x0841 +#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ (1U << 7) +#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U +#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f +#define CCS_R_TGR_POST_LENGTH 0x0842 +#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U +#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f +#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) (0x0843 + (n2)) +#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U +#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U +#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U +#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38 +#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U +#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7 +#define CCS_R_T3_PREPARE (0x084e | CCS_FL_16BIT) +#define CCS_R_T3_LPX (0x0850 | CCS_FL_16BIT) +#define CCS_R_ALPS_CTRL 0x085a +#define CCS_ALPS_CTRL_LVLP_DPHY (1U << 0) +#define CCS_ALPS_CTRL_LVLP_CPHY (1U << 1) +#define CCS_ALPS_CTRL_ALP_CPHY (1U << 2) +#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY (0x0860 | CCS_FL_16BIT) +#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY (0x0862 | CCS_FL_16BIT) +#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY (0x0864 | CCS_FL_16BIT) +#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY (0x0866 | CCS_FL_16BIT) +#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY 0x0868 +#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY 0x0869 +#define CCS_R_SCRAMBLING_CTRL 0x0870 +#define CCS_SCRAMBLING_CTRL_ENABLED (1U << 0) +#define CCS_SCRAMBLING_CTRL_SHIFT 2U +#define CCS_SCRAMBLING_CTRL_MASK 0xc +#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U +#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U +#define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2) +#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U +#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U +#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U +#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U +#define CCS_R_TX_USL_REV_ENTRY (0x08c0 | CCS_FL_16BIT) +#define CCS_R_TX_USL_REV_CLOCK_COUNTER (0x08c2 | CCS_FL_16BIT) +#define CCS_R_TX_USL_REV_LP_COUNTER (0x08c4 | CCS_FL_16BIT) +#define CCS_R_TX_USL_REV_FRAME_COUNTER (0x08c6 | CCS_FL_16BIT) +#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER (0x08c8 | CCS_FL_16BIT) +#define CCS_R_TX_USL_FWD_ENTRY (0x08ca | CCS_FL_16BIT) +#define CCS_R_TX_USL_GPIO (0x08cc | CCS_FL_16BIT) +#define CCS_R_TX_USL_OPERATION (0x08ce | CCS_FL_16BIT) +#define CCS_TX_USL_OPERATION_RESET (1U << 0) +#define CCS_R_TX_USL_ALP_CTRL (0x08d0 | CCS_FL_16BIT) +#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE (1U << 0) +#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT) +#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT) +#define CCS_R_USL_CLOCK_MODE_D_CTRL 0x08d2 +#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY (1U << 0) +#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK (1U << 1) +#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK (1U << 2) +#define CCS_R_BINNING_MODE 0x0900 +#define CCS_R_BINNING_TYPE 0x0901 +#define CCS_R_BINNING_WEIGHTING 0x0902 +#define CCS_R_DATA_TRANSFER_IF_1_CTRL 0x0a00 +#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE (1U << 0) +#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE (1U << 1) +#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR (1U << 2) +#define CCS_R_DATA_TRANSFER_IF_1_STATUS 0x0a01 +#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY (1U << 0) +#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY (1U << 1) +#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED (1U << 2) +#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE (1U << 3) +#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02 +#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) (0x0a04 + (p)) +#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U +#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U +#define CCS_R_SHADING_CORRECTION_EN 0x0b00 +#define CCS_SHADING_CORRECTION_EN_ENABLE (1U << 0) +#define CCS_R_LUMINANCE_CORRECTION_LEVEL 0x0b01 +#define CCS_R_GREEN_IMBALANCE_FILTER_EN 0x0b02 +#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE (1U << 0) +#define CCS_R_MAPPED_DEFECT_CORRECT_EN 0x0b05 +#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE (1U << 0) +#define CCS_R_SINGLE_DEFECT_CORRECT_EN 0x0b06 +#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE (1U << 0) +#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN 0x0b08 +#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE (1U << 0) +#define CCS_R_COMBINED_DEFECT_CORRECT_EN 0x0b0a +#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE (1U << 0) +#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN 0x0b0c +#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE (1U << 0) +#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN 0x0b13 +#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE (1U << 0) +#define CCS_R_NF_CTRL 0x0b15 +#define CCS_NF_CTRL_LUMA (1U << 0) +#define CCS_NF_CTRL_CHROMA (1U << 1) +#define CCS_NF_CTRL_COMBINED (1U << 2) +#define CCS_R_OB_READOUT_CONTROL 0x0b30 +#define CCS_OB_READOUT_CONTROL_ENABLE (1U << 0) +#define CCS_OB_READOUT_CONTROL_INTERLEAVING (1U << 1) +#define CCS_R_OB_VIRTUAL_CHANNEL 0x0b31 +#define CCS_R_OB_DT 0x0b32 +#define CCS_R_OB_DATA_FORMAT 0x0b33 +#define CCS_R_COLOR_TEMPERATURE (0x0b8c | CCS_FL_16BIT) +#define CCS_R_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT) +#define CCS_R_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT) +#define CCS_R_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT) +#define CCS_R_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT) +#define CCS_R_CFA_CONVERSION_CTRL 0x0ba0 +#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE (1U << 0) +#define CCS_R_FLASH_STROBE_ADJUSTMENT 0x0c12 +#define CCS_R_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT) +#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT) +#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT) +#define CCS_R_FLASH_MODE_RS 0x0c1a +#define CCS_FLASH_MODE_RS_CONTINUOUS (1U << 0) +#define CCS_FLASH_MODE_RS_TRUNCATE (1U << 1) +#define CCS_FLASH_MODE_RS_ASYNC (1U << 3) +#define CCS_R_FLASH_TRIGGER_RS 0x0c1b +#define CCS_R_FLASH_STATUS 0x0c1c +#define CCS_FLASH_STATUS_RETIMED (1U << 0) +#define CCS_R_SA_STROBE_MODE 0x0c1d +#define CCS_SA_STROBE_MODE_CONTINUOUS (1U << 0) +#define CCS_SA_STROBE_MODE_TRUNCATE (1U << 1) +#define CCS_SA_STROBE_MODE_ASYNC (1U << 3) +#define CCS_SA_STROBE_MODE_ADJUST_EDGE (1U << 4) +#define CCS_R_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT) +#define CCS_R_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT) +#define CCS_R_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT) +#define CCS_R_SA_STROBE_TRIGGER 0x0c24 +#define CCS_R_SA_STROBE_STATUS 0x0c25 +#define CCS_SA_STROBE_STATUS_RETIMED (1U << 0) +#define CCS_R_TSA_STROBE_RE_DELAY_CTRL (0x0c30 | CCS_FL_16BIT) +#define CCS_R_TSA_STROBE_FE_DELAY_CTRL (0x0c32 | CCS_FL_16BIT) +#define CCS_R_PDAF_CTRL (0x0d00 | CCS_FL_16BIT) +#define CCS_PDAF_CTRL_ENABLE (1U << 0) +#define CCS_PDAF_CTRL_PROCESSED (1U << 1) +#define CCS_PDAF_CTRL_INTERLEAVED (1U << 2) +#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION (1U << 3) +#define CCS_R_PDAF_VC 0x0d02 +#define CCS_R_PDAF_DT 0x0d03 +#define CCS_R_PD_X_ADDR_START (0x0d04 | CCS_FL_16BIT) +#define CCS_R_PD_Y_ADDR_START (0x0d06 | CCS_FL_16BIT) +#define CCS_R_PD_X_ADDR_END (0x0d08 | CCS_FL_16BIT) +#define CCS_R_PD_Y_ADDR_END (0x0d0a | CCS_FL_16BIT) +#define CCS_R_BRACKETING_LUT_CTRL 0x0e00 +#define CCS_R_BRACKETING_LUT_MODE 0x0e01 +#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING (1U << 0) +#define CCS_BRACKETING_LUT_MODE_LOOP_MODE (1U << 1) +#define CCS_R_BRACKETING_LUT_ENTRY_CTRL 0x0e02 +#define CCS_R_BRACKETING_LUT_FRAME(n) (0x0e10 + (n)) +#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U +#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U +#define CCS_R_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT) +#define CCS_INTEGRATION_TIME_CAPABILITY_FINE (1U << 0) +#define CCS_R_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT) +#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT) +#define CCS_R_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT) +#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT) +#define CCS_R_DIGITAL_GAIN_CAPABILITY 0x1081 +#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U +#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U +#define CCS_R_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT) +#define CCS_R_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT) +#define CCS_R_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT) +#define CCS_R_PEDESTAL_CAPABILITY 0x10e0 +#define CCS_R_ADC_CAPABILITY 0x10f0 +#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL (1U << 0) +#define CCS_R_ADC_BIT_DEPTH_CAPABILITY (0x10f4 | CCS_FL_32BIT) +#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT) +#define CCS_R_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT) +#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT) +#define CCS_R_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT) +#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT) +#define CCS_R_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT) +#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT) +#define CCS_R_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT) +#define CCS_R_CLOCK_CALCULATION 0x1138 +#define CCS_CLOCK_CALCULATION_LANE_SPEED (1U << 0) +#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED (1U << 1) +#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR (1U << 2) +#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR (1U << 3) +#define CCS_R_NUM_OF_VT_LANES 0x1139 +#define CCS_R_NUM_OF_OP_LANES 0x113a +#define CCS_R_OP_BITS_PER_LANE 0x113b +#define CCS_R_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT) +#define CCS_R_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT) +#define CCS_R_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT) +#define CCS_R_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT) +#define CCS_R_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT) +#define CCS_R_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT) +#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c +#define CCS_R_TIMING_MODE_CAPABILITY 0x114d +#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH (1U << 0) +#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT (1U << 2) +#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START (1U << 3) +#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA (1U << 4) +#define CCS_R_FRAME_MARGIN_MAX_VALUE (0x114e | CCS_FL_16BIT) +#define CCS_R_FRAME_MARGIN_MIN_VALUE 0x1150 +#define CCS_R_GAIN_DELAY_TYPE 0x1151 +#define CCS_GAIN_DELAY_TYPE_FIXED 0U +#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U +#define CCS_R_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT) +#define CCS_R_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT) +#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT) +#define CCS_R_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT) +#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_X_ADDR_MIN (0x1180 | CCS_FL_16BIT) +#define CCS_R_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT) +#define CCS_R_X_ADDR_MAX (0x1184 | CCS_FL_16BIT) +#define CCS_R_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT) +#define CCS_R_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT) +#define CCS_R_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT) +#define CCS_R_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT) +#define CCS_R_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT) +#define CCS_R_X_ADDR_START_DIV_CONSTANT 0x1190 +#define CCS_R_Y_ADDR_START_DIV_CONSTANT 0x1191 +#define CCS_R_X_ADDR_END_DIV_CONSTANT 0x1192 +#define CCS_R_Y_ADDR_END_DIV_CONSTANT 0x1193 +#define CCS_R_X_SIZE_DIV 0x1194 +#define CCS_R_Y_SIZE_DIV 0x1195 +#define CCS_R_X_OUTPUT_DIV 0x1196 +#define CCS_R_Y_OUTPUT_DIV 0x1197 +#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT 0x1198 +#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR (1U << 0) +#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES (1U << 1) +#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD (1U << 2) +#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP (1U << 3) +#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV (0x11a0 | CCS_FL_16BIT) +#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV (0x11a2 | CCS_FL_16BIT) +#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_OP_PLL_MULTIPLIER (0x11ac | CCS_FL_16BIT) +#define CCS_R_MAX_OP_PLL_MULTIPLIER (0x11ae | CCS_FL_16BIT) +#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_CLOCK_TREE_PLL_CAPABILITY 0x11b8 +#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL (1U << 0) +#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL (1U << 1) +#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER (1U << 2) +#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV (1U << 3) +#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY 0x11b9 +#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL (1U << 0) +#define CCS_R_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT) +#define CCS_R_MIN_ODD_INC (0x11c2 | CCS_FL_16BIT) +#define CCS_R_MAX_EVEN_INC (0x11c4 | CCS_FL_16BIT) +#define CCS_R_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT) +#define CCS_R_AUX_SUBSAMP_CAPABILITY 0x11c8 +#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 (1U << 1) +#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY 0x11c9 +#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 (1U << 1) +#define CCS_R_MONOCHROME_CAPABILITY 0x11ca +#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U +#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U +#define CCS_R_PIXEL_READOUT_CAPABILITY 0x11cb +#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U +#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U +#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U +#define CCS_R_MIN_EVEN_INC_MONO (0x11cc | CCS_FL_16BIT) +#define CCS_R_MAX_EVEN_INC_MONO (0x11ce | CCS_FL_16BIT) +#define CCS_R_MIN_ODD_INC_MONO (0x11d0 | CCS_FL_16BIT) +#define CCS_R_MAX_ODD_INC_MONO (0x11d2 | CCS_FL_16BIT) +#define CCS_R_MIN_EVEN_INC_BC2 (0x11d4 | CCS_FL_16BIT) +#define CCS_R_MAX_EVEN_INC_BC2 (0x11d6 | CCS_FL_16BIT) +#define CCS_R_MIN_ODD_INC_BC2 (0x11d8 | CCS_FL_16BIT) +#define CCS_R_MAX_ODD_INC_BC2 (0x11da | CCS_FL_16BIT) +#define CCS_R_MIN_EVEN_INC_MONO_BC2 (0x11dc | CCS_FL_16BIT) +#define CCS_R_MAX_EVEN_INC_MONO_BC2 (0x11de | CCS_FL_16BIT) +#define CCS_R_MIN_ODD_INC_MONO_BC2 (0x11f0 | CCS_FL_16BIT) +#define CCS_R_MAX_ODD_INC_MONO_BC2 (0x11f2 | CCS_FL_16BIT) +#define CCS_R_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT) +#define CCS_SCALING_CAPABILITY_NONE 0U +#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U +#define CCS_SCALING_CAPABILITY_RESERVED 2U +#define CCS_R_SCALER_M_MIN (0x1204 | CCS_FL_16BIT) +#define CCS_R_SCALER_M_MAX (0x1206 | CCS_FL_16BIT) +#define CCS_R_SCALER_N_MIN (0x1208 | CCS_FL_16BIT) +#define CCS_R_SCALER_N_MAX (0x120a | CCS_FL_16BIT) +#define CCS_R_DIGITAL_CROP_CAPABILITY 0x120e +#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U +#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U +#define CCS_R_HDR_CAPABILITY_1 0x1210 +#define CCS_HDR_CAPABILITY_1_2X2_BINNING (1U << 0) +#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN (1U << 1) +#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN (1U << 2) +#define CCS_HDR_CAPABILITY_1_UPSCALING (1U << 3) +#define CCS_HDR_CAPABILITY_1_RESET_SYNC (1U << 4) +#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING (1U << 5) +#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS (1U << 6) +#define CCS_R_MIN_HDR_BIT_DEPTH 0x1211 +#define CCS_R_HDR_RESOLUTION_SUB_TYPES 0x1212 +#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) (0x1213 + (n)) +#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U +#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U +#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U +#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf +#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U +#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0 +#define CCS_R_HDR_CAPABILITY_2 0x121b +#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN (1U << 0) +#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN (1U << 1) +#define CCS_HDR_CAPABILITY_2_TIMING_MODE (1U << 3) +#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE (1U << 4) +#define CCS_R_MAX_HDR_BIT_DEPTH 0x121c +#define CCS_R_USL_SUPPORT_CAPABILITY 0x1230 +#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE (1U << 0) +#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE (1U << 1) +#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC (1U << 2) +#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY 0x1231 +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY (1U << 0) +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK (1U << 1) +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK (1U << 2) +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY (1U << 3) +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK (1U << 4) +#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK (1U << 5) +#define CCS_R_MIN_OP_SYS_CLK_DIV_REV 0x1234 +#define CCS_R_MAX_OP_SYS_CLK_DIV_REV 0x1236 +#define CCS_R_MIN_OP_PIX_CLK_DIV_REV 0x1238 +#define CCS_R_MAX_OP_PIX_CLK_DIV_REV 0x123a +#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL)) +#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (0x124c | (CCS_FL_32BIT | CCS_FL_IREAL)) +#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL)) +#define CCS_R_COMPRESSION_CAPABILITY 0x1300 +#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE (1U << 0) +#define CCS_R_TEST_MODE_CAPABILITY (0x1310 | CCS_FL_16BIT) +#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR (1U << 0) +#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS (1U << 1) +#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY (1U << 2) +#define CCS_TEST_MODE_CAPABILITY_PN9 (1U << 3) +#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE (1U << 5) +#define CCS_R_PN9_DATA_FORMAT1 0x1312 +#define CCS_R_PN9_DATA_FORMAT2 0x1313 +#define CCS_R_PN9_DATA_FORMAT3 0x1314 +#define CCS_R_PN9_DATA_FORMAT4 0x1315 +#define CCS_R_PN9_MISC_CAPABILITY 0x1316 +#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U +#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7 +#define CCS_PN9_MISC_CAPABILITY_COMPRESSION (1U << 3) +#define CCS_R_TEST_PATTERN_CAPABILITY 0x1317 +#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT (1U << 1) +#define CCS_R_PATTERN_SIZE_DIV_M1 0x1318 +#define CCS_R_FIFO_SUPPORT_CAPABILITY 0x1502 +#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U +#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U +#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U +#define CCS_R_PHY_CTRL_CAPABILITY 0x1600 +#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL (1U << 0) +#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL (1U << 1) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL (1U << 2) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL (1U << 3) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL (1U << 4) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL (1U << 5) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL (1U << 6) +#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL (1U << 7) +#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY 0x1601 +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE (1U << 0) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE (1U << 1) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE (1U << 2) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE (1U << 3) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE (1U << 4) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE (1U << 5) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE (1U << 6) +#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE (1U << 7) +#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY 0x1602 +#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY (1U << 2) +#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY (1U << 3) +#define CCS_R_FAST_STANDBY_CAPABILITY 0x1603 +#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U +#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U +#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY 0x1604 +#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE (1U << 0) +#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR (1U << 1) +#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR (1U << 2) +#define CCS_R_DATA_TYPE_CAPABILITY 0x1605 +#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE (1U << 0) +#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE (1U << 1) +#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE (1U << 2) +#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE (1U << 3) +#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY 0x1606 +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE (1U << 0) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE (1U << 1) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE (1U << 2) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE (1U << 3) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE (1U << 4) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE (1U << 5) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE (1U << 6) +#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE (1U << 7) +#define CCS_R_EMB_DATA_CAPABILITY 0x1607 +#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 (1U << 0) +#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 (1U << 1) +#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 (1U << 2) +#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 (1U << 3) +#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 (1U << 4) +#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 (1U << 5) +#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4)) +#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U +#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U +#define CCS_R_TEMP_SENSOR_CAPABILITY 0x1618 +#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED (1U << 0) +#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT (1U << 1) +#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 (1U << 2) +#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4)) +#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U +#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U +#define CCS_R_DPHY_EQUALIZATION_CAPABILITY 0x162b +#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL (1U << 0) +#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 (1U << 1) +#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 (1U << 2) +#define CCS_R_CPHY_EQUALIZATION_CAPABILITY 0x162c +#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL (1U << 0) +#define CCS_R_DPHY_PREAMBLE_CAPABILITY 0x162d +#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL (1U << 0) +#define CCS_R_DPHY_SSC_CAPABILITY 0x162e +#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED (1U << 0) +#define CCS_R_CPHY_CALIBRATION_CAPABILITY 0x162f +#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL (1U << 0) +#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING (1U << 1) +#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL (1U << 2) +#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL (1U << 3) +#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL (1U << 4) +#define CCS_R_DPHY_CALIBRATION_CAPABILITY 0x1630 +#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL (1U << 0) +#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING (1U << 1) +#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ (1U << 2) +#define CCS_R_PHY_CTRL_CAPABILITY_2 0x1631 +#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH (1U << 0) +#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ (1U << 1) +#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING (1U << 2) +#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY (1U << 3) +#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY (1U << 4) +#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY (1U << 5) +#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY (1U << 6) +#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY (1U << 7) +#define CCS_R_LRTE_CPHY_CAPABILITY 0x1632 +#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT (1U << 0) +#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT (1U << 1) +#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG (1U << 2) +#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG (1U << 3) +#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ (1U << 4) +#define CCS_R_LRTE_DPHY_CAPABILITY 0x1633 +#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 (1U << 0) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 (1U << 1) +#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 (1U << 2) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 (1U << 3) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 (1U << 4) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 (1U << 5) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 (1U << 6) +#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 (1U << 7) +#define CCS_R_ALPS_CAPABILITY_DPHY 0x1634 +#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U +#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U +#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U +#define CCS_R_ALPS_CAPABILITY_CPHY 0x1635 +#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U +#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U +#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U +#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc +#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd +#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe +#define CCS_R_SCRAMBLING_CAPABILITY 0x1636 +#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED (1U << 0) +#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U +#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6 +#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U +#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38 +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U +#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE (1U << 6) +#define CCS_R_DPHY_MANUAL_CONSTANT 0x1637 +#define CCS_R_CPHY_MANUAL_CONSTANT 0x1638 +#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC 0x1639 +#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 (1U << 0) +#define CCS_R_PHY_CTRL_CAPABILITY_3 0x165c +#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE (1U << 0) +#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 (1U << 1) +#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED (1U << 2) +#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED (1U << 3) +#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED (1U << 4) +#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE (1U << 5) +#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 (1U << 6) +#define CCS_R_DPHY_SF 0x165d +#define CCS_R_CPHY_SF 0x165e +#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U +#define CCS_CPHY_SF_TWAKEUP_MASK 0xf +#define CCS_CPHY_SF_TINIT_SHIFT 4U +#define CCS_CPHY_SF_TINIT_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_1 0x165f +#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U +#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf +#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U +#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_2 0x1660 +#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U +#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf +#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U +#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_3 0x1661 +#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U +#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf +#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U +#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_4 0x1662 +#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U +#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf +#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U +#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_5 0x1663 +#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U +#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf +#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U +#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0 +#define CCS_R_DPHY_LIMITS_6 0x1664 +#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U +#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf +#define CCS_R_CPHY_LIMITS_1 0x1665 +#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U +#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf +#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U +#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0 +#define CCS_R_CPHY_LIMITS_2 0x1666 +#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U +#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf +#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U +#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0 +#define CCS_R_CPHY_LIMITS_3 0x1667 +#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U +#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf +#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT) +#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT) +#define CCS_R_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT) +#define CCS_R_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT) +#define CCS_R_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT) +#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT) +#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT) +#define CCS_R_BINNING_CAPABILITY 0x1710 +#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U +#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U +#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U +#define CCS_R_BINNING_WEIGHTING_CAPABILITY 0x1711 +#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED (1U << 0) +#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED (1U << 1) +#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED (1U << 2) +#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT (1U << 3) +#define CCS_R_BINNING_SUB_TYPES 0x1712 +#define CCS_R_BINNING_SUB_TYPE(n) (0x1713 + (n)) +#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U +#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U +#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U +#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf +#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U +#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0 +#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY 0x1771 +#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED (1U << 0) +#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED (1U << 1) +#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED (1U << 2) +#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT (1U << 3) +#define CCS_R_BINNING_SUB_TYPES_MONO 0x1772 +#define CCS_R_BINNING_SUB_TYPE_MONO(n) (0x1773 + (n)) +#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U +#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U +#define CCS_R_DATA_TRANSFER_IF_CAPABILITY 0x1800 +#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED (1U << 0) +#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING (1U << 2) +#define CCS_R_SHADING_CORRECTION_CAPABILITY 0x1900 +#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING (1U << 0) +#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION (1U << 1) +#define CCS_R_GREEN_IMBALANCE_CAPABILITY 0x1901 +#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED (1U << 0) +#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903 +#define CCS_R_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT) +#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT (1U << 0) +#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET (1U << 2) +#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE (1U << 5) +#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC (1U << 8) +#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT) +#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET (1U << 3) +#define CCS_R_NF_CAPABILITY 0x1908 +#define CCS_NF_CAPABILITY_LUMA (1U << 0) +#define CCS_NF_CAPABILITY_CHROMA (1U << 1) +#define CCS_NF_CAPABILITY_COMBINED (1U << 2) +#define CCS_R_OB_READOUT_CAPABILITY 0x1980 +#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT (1U << 0) +#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT (1U << 1) +#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT (1U << 2) +#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT (1U << 3) +#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT (1U << 4) +#define CCS_R_COLOR_FEEDBACK_CAPABILITY 0x1987 +#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN (1U << 0) +#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN (1U << 1) +#define CCS_R_CFA_PATTERN_CAPABILITY 0x1990 +#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U +#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U +#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U +#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U +#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY 0x1991 +#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER (1U << 0) +#define CCS_R_FLASH_MODE_CAPABILITY 0x1a02 +#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE (1U << 0) +#define CCS_R_SA_STROBE_MODE_CAPABILITY 0x1a03 +#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH (1U << 0) +#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL (1U << 1) +#define CCS_R_RESET_MAX_DELAY 0x1a10 +#define CCS_R_RESET_MIN_TIME 0x1a11 +#define CCS_R_PDAF_CAPABILITY_1 0x1b80 +#define CCS_PDAF_CAPABILITY_1_SUPPORTED (1U << 0) +#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED (1U << 1) +#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED (1U << 2) +#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED (1U << 3) +#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED (1U << 4) +#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION (1U << 5) +#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING (1U << 6) +#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING (1U << 7) +#define CCS_R_PDAF_CAPABILITY_2 0x1b81 +#define CCS_PDAF_CAPABILITY_2_ROI (1U << 0) +#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP (1U << 1) +#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED (1U << 2) +#define CCS_R_BRACKETING_LUT_CAPABILITY_1 0x1c00 +#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION (1U << 0) +#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN (1U << 1) +#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH (1U << 4) +#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN (1U << 5) +#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN (1U << 6) +#define CCS_R_BRACKETING_LUT_CAPABILITY_2 0x1c01 +#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE (1U << 0) +#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE (1U << 1) +#define CCS_R_BRACKETING_LUT_SIZE 0x1c02 + +#endif /* __CCS_REGS_H__ */ From patchwork Wed Sep 30 15:27:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809673 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26E8F92C for ; Wed, 30 Sep 2020 15:30:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B3A02311A for ; Wed, 30 Sep 2020 15:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731203AbgI3Paj (ORCPT ); Wed, 30 Sep 2020 11:30:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730198AbgI3P3A (ORCPT ); Wed, 30 Sep 2020 11:29:00 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6436C0613D1 for ; Wed, 30 Sep 2020 08:29:00 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 2CA35634C8C for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 002/100] smiapp: Use CCS register flags Date: Wed, 30 Sep 2020 18:27:20 +0300 Message-Id: <20200930152858.8471-3-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the CCS register flags instead of the old smia flags. The new flags include the register width information that was separate from the register flags previously. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-reg-defs.h | 8 ++++---- drivers/media/i2c/smiapp/smiapp-regs.c | 20 +++++++++++++------- drivers/media/i2c/smiapp/smiapp-regs.h | 13 ++++--------- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h index 865488befc09..ec574007908b 100644 --- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h +++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h @@ -7,11 +7,11 @@ * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ -#define SMIAPP_REG_MK_U8(r) ((SMIAPP_REG_8BIT << 16) | (r)) -#define SMIAPP_REG_MK_U16(r) ((SMIAPP_REG_16BIT << 16) | (r)) -#define SMIAPP_REG_MK_U32(r) ((SMIAPP_REG_32BIT << 16) | (r)) +#define SMIAPP_REG_MK_U8(r) (r) +#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r)) +#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r)) -#define SMIAPP_REG_MK_F32(r) (SMIAPP_REG_FLAG_FLOAT | (SMIAPP_REG_32BIT << 16) | (r)) +#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r)) #define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000) #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002) diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c index 1b58b7c6c839..904054d303ba 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.c +++ b/drivers/media/i2c/smiapp/smiapp-regs.c @@ -133,6 +133,16 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, return 0; } +unsigned int ccs_reg_width(u32 reg) +{ + if (reg & CCS_FL_16BIT) + return sizeof(uint16_t); + if (reg & CCS_FL_32BIT) + return sizeof(uint32_t); + + return sizeof(uint8_t); +} + /* * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. @@ -141,13 +151,9 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, bool only8) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - u8 len = SMIAPP_REG_WIDTH(reg); + unsigned int len = ccs_reg_width(reg); int rval; - if (len != SMIAPP_REG_8BIT && len != SMIAPP_REG_16BIT - && len != SMIAPP_REG_32BIT) - return -EINVAL; - if (!only8) rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); else @@ -156,7 +162,7 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, if (rval < 0) return rval; - if (reg & SMIAPP_REG_FLAG_FLOAT) + if (reg & CCS_FL_FLOAT_IREAL) *val = float_to_u32_mul_1000000(client, *val); return 0; @@ -204,7 +210,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) struct i2c_msg msg; unsigned char data[6]; unsigned int retries; - u8 len = SMIAPP_REG_WIDTH(reg); + unsigned int len = ccs_reg_width(reg); int r; if (len > sizeof(data) - 2) diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h index 8fda6ed5668c..7223f5f89109 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.h +++ b/drivers/media/i2c/smiapp/smiapp-regs.h @@ -14,16 +14,9 @@ #include #include -#define SMIAPP_REG_ADDR(reg) ((u16)reg) -#define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16)) -#define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24)) - -/* Use upper 8 bits of the type field for flags */ -#define SMIAPP_REG_FLAG_FLOAT (1 << 24) +#include "ccs-regs.h" -#define SMIAPP_REG_8BIT 1 -#define SMIAPP_REG_16BIT 2 -#define SMIAPP_REG_32BIT 4 +#define SMIAPP_REG_ADDR(reg) ((u16)reg) struct smiapp_sensor; @@ -33,4 +26,6 @@ int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val); +unsigned int ccs_reg_width(u32 reg); + #endif From patchwork Wed Sep 30 15:27:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 840F5139A for ; Wed, 30 Sep 2020 15:30:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FC61221EF for ; Wed, 30 Sep 2020 15:30:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731202AbgI3Pag (ORCPT ); Wed, 30 Sep 2020 11:30:36 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44632 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725892AbgI3P3B (ORCPT ); Wed, 30 Sep 2020 11:29:01 -0400 X-Greylist: delayed 2446 seconds by postgrey-1.27 at vger.kernel.org; Wed, 30 Sep 2020 11:29:00 EDT Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 3E27A634C8D for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 003/100] smiapp: Calculate CCS limit offsets and limit buffer size Date: Wed, 30 Sep 2020 18:27:21 +0300 Message-Id: <20200930152858.8471-4-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Calculate the limit offsets and the size of the limit buffer. CCS limits are read into this buffer, and the offsets are helpful in accessing the information in it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index 105ef29152e8..47e983e9cd87 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -27,6 +27,7 @@ #include #include +#include "ccs-limits.h" #include "smiapp.h" #define SMIAPP_ALIGN_DIM(dim, flags) \ @@ -34,6 +35,11 @@ ? ALIGN((dim), 2) \ : (dim) & ~1) +struct ccs_limit_offset { + u16 lim; + u16 info; +} ccs_limit_offsets[CCS_L_LAST + 1]; + /* * smiapp_module_idents - supported camera modules */ @@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = { .id_table = smiapp_id_table, }; -module_i2c_driver(smiapp_i2c_driver); +static int smiapp_module_init(void) +{ + unsigned int i, l; + + for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) { + if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) { + ccs_limit_offsets[l + 1].lim = + ALIGN(ccs_limit_offsets[l].lim + + ccs_limits[i].size, + ccs_reg_width(ccs_limits[i + 1].reg)); + ccs_limit_offsets[l].info = i; + l++; + } else { + ccs_limit_offsets[l].lim += ccs_limits[i].size; + } + } + + if (WARN_ON(ccs_limits[i].size)) + return -EINVAL; + + if (WARN_ON(l != CCS_L_LAST)) + return -EINVAL; + + return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver); +} + +static void smiapp_module_cleanup(void) +{ + i2c_del_driver(&smiapp_i2c_driver); +} + +module_init(smiapp_module_init); +module_exit(smiapp_module_cleanup); MODULE_AUTHOR("Sakari Ailus "); MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver"); From patchwork Wed Sep 30 15:27:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809663 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4849892C for ; Wed, 30 Sep 2020 15:30:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19B0A21D7F for ; Wed, 30 Sep 2020 15:30:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730800AbgI3Paf (ORCPT ); Wed, 30 Sep 2020 11:30:35 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44634 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728149AbgI3P3B (ORCPT ); Wed, 30 Sep 2020 11:29:01 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 58E55634C8E for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 004/100] smiapp: Remove macros for defining registers, merge definitions Date: Wed, 30 Sep 2020 18:27:22 +0300 Message-Id: <20200930152858.8471-5-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Remove macros for defining new SMIA registers, instead put the register flags to the register definition itself. Also move the register flags to the same file. This is not expected to be updated but rather left there as a reference. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-quirk.c | 2 +- drivers/media/i2c/smiapp/smiapp-reg-defs.h | 1046 +++++++++++--------- drivers/media/i2c/smiapp/smiapp-reg.h | 116 --- drivers/media/i2c/smiapp/smiapp.h | 2 +- 4 files changed, 570 insertions(+), 596 deletions(-) delete mode 100644 drivers/media/i2c/smiapp/smiapp-reg.h diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c index ab96d6067fc3..308ca0b03f5a 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.c +++ b/drivers/media/i2c/smiapp/smiapp-quirk.c @@ -14,7 +14,7 @@ static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val) { - return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val); + return smiapp_write(sensor, reg, val); } static int smiapp_write_8s(struct smiapp_sensor *sensor, diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h index ec574007908b..06b69b1ab55f 100644 --- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h +++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h @@ -7,483 +7,573 @@ * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ -#define SMIAPP_REG_MK_U8(r) (r) -#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r)) -#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r)) -#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r)) +#ifndef __SMIAPP_REG_DEFS_H__ +#define __SMIAPP_REG_DEFS_H__ -#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000) -#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002) -#define SMIAPP_REG_U8_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0003) -#define SMIAPP_REG_U8_SMIA_VERSION SMIAPP_REG_MK_U8(0x0004) -#define SMIAPP_REG_U8_FRAME_COUNT SMIAPP_REG_MK_U8(0x0005) -#define SMIAPP_REG_U8_PIXEL_ORDER SMIAPP_REG_MK_U8(0x0006) -#define SMIAPP_REG_U16_DATA_PEDESTAL SMIAPP_REG_MK_U16(0x0008) -#define SMIAPP_REG_U8_PIXEL_DEPTH SMIAPP_REG_MK_U8(0x000c) -#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR SMIAPP_REG_MK_U8(0x0010) -#define SMIAPP_REG_U8_SMIAPP_VERSION SMIAPP_REG_MK_U8(0x0011) -#define SMIAPP_REG_U8_MODULE_DATE_YEAR SMIAPP_REG_MK_U8(0x0012) -#define SMIAPP_REG_U8_MODULE_DATE_MONTH SMIAPP_REG_MK_U8(0x0013) -#define SMIAPP_REG_U8_MODULE_DATE_DAY SMIAPP_REG_MK_U8(0x0014) -#define SMIAPP_REG_U8_MODULE_DATE_PHASE SMIAPP_REG_MK_U8(0x0015) -#define SMIAPP_REG_U16_SENSOR_MODEL_ID SMIAPP_REG_MK_U16(0x0016) -#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER SMIAPP_REG_MK_U8(0x0018) -#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0019) -#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION SMIAPP_REG_MK_U8(0x001a) -#define SMIAPP_REG_U32_SERIAL_NUMBER SMIAPP_REG_MK_U32(0x001c) -#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x0040) -#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x0041) -#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) SMIAPP_REG_MK_U16(0x0042 + ((n) << 1)) /* 0 <= n <= 14 */ -#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) SMIAPP_REG_MK_U32(0x0060 + ((n) << 2)) /* 0 <= n <= 7 */ -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x0080) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN SMIAPP_REG_MK_U16(0x0084) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX SMIAPP_REG_MK_U16(0x0086) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP SMIAPP_REG_MK_U16(0x0088) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE SMIAPP_REG_MK_U16(0x008a) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 SMIAPP_REG_MK_U16(0x008c) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 SMIAPP_REG_MK_U16(0x008e) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 SMIAPP_REG_MK_U16(0x0090) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 SMIAPP_REG_MK_U16(0x0092) -#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x00c0) -#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x00c1) -#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) SMIAPP_REG_MK_U16(0x00c2 + ((n) << 1)) -#define SMIAPP_REG_U8_MODE_SELECT SMIAPP_REG_MK_U8(0x0100) -#define SMIAPP_REG_U8_IMAGE_ORIENTATION SMIAPP_REG_MK_U8(0x0101) -#define SMIAPP_REG_U8_SOFTWARE_RESET SMIAPP_REG_MK_U8(0x0103) -#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD SMIAPP_REG_MK_U8(0x0104) -#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES SMIAPP_REG_MK_U8(0x0105) -#define SMIAPP_REG_U8_FAST_STANDBY_CTRL SMIAPP_REG_MK_U8(0x0106) -#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0107) -#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL SMIAPP_REG_MK_U8(0x0108) -#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0109) -#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER SMIAPP_REG_MK_U8(0x0110) -#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE SMIAPP_REG_MK_U8(0x0111) -#define SMIAPP_REG_U16_CSI_DATA_FORMAT SMIAPP_REG_MK_U16(0x0112) -#define SMIAPP_REG_U8_CSI_LANE_MODE SMIAPP_REG_MK_U8(0x0114) -#define SMIAPP_REG_U8_CSI2_10_TO_8_DT SMIAPP_REG_MK_U8(0x0115) -#define SMIAPP_REG_U8_CSI2_10_TO_7_DT SMIAPP_REG_MK_U8(0x0116) -#define SMIAPP_REG_U8_CSI2_10_TO_6_DT SMIAPP_REG_MK_U8(0x0117) -#define SMIAPP_REG_U8_CSI2_12_TO_8_DT SMIAPP_REG_MK_U8(0x0118) -#define SMIAPP_REG_U8_CSI2_12_TO_7_DT SMIAPP_REG_MK_U8(0x0119) -#define SMIAPP_REG_U8_CSI2_12_TO_6_DT SMIAPP_REG_MK_U8(0x011a) -#define SMIAPP_REG_U8_CSI2_14_TO_10_DT SMIAPP_REG_MK_U8(0x011b) -#define SMIAPP_REG_U8_CSI2_14_TO_8_DT SMIAPP_REG_MK_U8(0x011c) -#define SMIAPP_REG_U8_CSI2_16_TO_10_DT SMIAPP_REG_MK_U8(0x011d) -#define SMIAPP_REG_U8_CSI2_16_TO_8_DT SMIAPP_REG_MK_U8(0x011e) -#define SMIAPP_REG_U8_GAIN_MODE SMIAPP_REG_MK_U8(0x0120) -#define SMIAPP_REG_U16_VANA_VOLTAGE SMIAPP_REG_MK_U16(0x0130) -#define SMIAPP_REG_U16_VDIG_VOLTAGE SMIAPP_REG_MK_U16(0x0132) -#define SMIAPP_REG_U16_VIO_VOLTAGE SMIAPP_REG_MK_U16(0x0134) -#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ SMIAPP_REG_MK_U16(0x0136) -#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL SMIAPP_REG_MK_U8(0x0138) -#define SMIAPP_REG_U8_TEMP_SENSOR_MODE SMIAPP_REG_MK_U8(0x0139) -#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT SMIAPP_REG_MK_U8(0x013a) -#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0200) -#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0202) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL SMIAPP_REG_MK_U16(0x0204) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR SMIAPP_REG_MK_U16(0x0206) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED SMIAPP_REG_MK_U16(0x0208) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE SMIAPP_REG_MK_U16(0x020a) -#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB SMIAPP_REG_MK_U16(0x020c) -#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR SMIAPP_REG_MK_U16(0x020e) -#define SMIAPP_REG_U16_DIGITAL_GAIN_RED SMIAPP_REG_MK_U16(0x0210) -#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE SMIAPP_REG_MK_U16(0x0212) -#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB SMIAPP_REG_MK_U16(0x0214) -#define SMIAPP_REG_U16_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0300) -#define SMIAPP_REG_U16_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x0302) -#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x0304) -#define SMIAPP_REG_U16_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x0306) -#define SMIAPP_REG_U16_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0308) -#define SMIAPP_REG_U16_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x030a) -#define SMIAPP_REG_U16_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x0340) -#define SMIAPP_REG_U16_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x0342) -#define SMIAPP_REG_U16_X_ADDR_START SMIAPP_REG_MK_U16(0x0344) -#define SMIAPP_REG_U16_Y_ADDR_START SMIAPP_REG_MK_U16(0x0346) -#define SMIAPP_REG_U16_X_ADDR_END SMIAPP_REG_MK_U16(0x0348) -#define SMIAPP_REG_U16_Y_ADDR_END SMIAPP_REG_MK_U16(0x034a) -#define SMIAPP_REG_U16_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034c) -#define SMIAPP_REG_U16_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034e) -#define SMIAPP_REG_U16_X_EVEN_INC SMIAPP_REG_MK_U16(0x0380) -#define SMIAPP_REG_U16_X_ODD_INC SMIAPP_REG_MK_U16(0x0382) -#define SMIAPP_REG_U16_Y_EVEN_INC SMIAPP_REG_MK_U16(0x0384) -#define SMIAPP_REG_U16_Y_ODD_INC SMIAPP_REG_MK_U16(0x0386) -#define SMIAPP_REG_U16_SCALING_MODE SMIAPP_REG_MK_U16(0x0400) -#define SMIAPP_REG_U16_SPATIAL_SAMPLING SMIAPP_REG_MK_U16(0x0402) -#define SMIAPP_REG_U16_SCALE_M SMIAPP_REG_MK_U16(0x0404) -#define SMIAPP_REG_U16_SCALE_N SMIAPP_REG_MK_U16(0x0406) -#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET SMIAPP_REG_MK_U16(0x0408) -#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET SMIAPP_REG_MK_U16(0x040a) -#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH SMIAPP_REG_MK_U16(0x040c) -#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT SMIAPP_REG_MK_U16(0x040e) -#define SMIAPP_REG_U16_COMPRESSION_MODE SMIAPP_REG_MK_U16(0x0500) -#define SMIAPP_REG_U16_TEST_PATTERN_MODE SMIAPP_REG_MK_U16(0x0600) -#define SMIAPP_REG_U16_TEST_DATA_RED SMIAPP_REG_MK_U16(0x0602) -#define SMIAPP_REG_U16_TEST_DATA_GREENR SMIAPP_REG_MK_U16(0x0604) -#define SMIAPP_REG_U16_TEST_DATA_BLUE SMIAPP_REG_MK_U16(0x0606) -#define SMIAPP_REG_U16_TEST_DATA_GREENB SMIAPP_REG_MK_U16(0x0608) -#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060a) -#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x060c) -#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060e) -#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x0610) -#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS SMIAPP_REG_MK_U16(0x0700) -#define SMIAPP_REG_U8_TCLK_POST SMIAPP_REG_MK_U8(0x0800) -#define SMIAPP_REG_U8_THS_PREPARE SMIAPP_REG_MK_U8(0x0801) -#define SMIAPP_REG_U8_THS_ZERO_MIN SMIAPP_REG_MK_U8(0x0802) -#define SMIAPP_REG_U8_THS_TRAIL SMIAPP_REG_MK_U8(0x0803) -#define SMIAPP_REG_U8_TCLK_TRAIL_MIN SMIAPP_REG_MK_U8(0x0804) -#define SMIAPP_REG_U8_TCLK_PREPARE SMIAPP_REG_MK_U8(0x0805) -#define SMIAPP_REG_U8_TCLK_ZERO SMIAPP_REG_MK_U8(0x0806) -#define SMIAPP_REG_U8_TLPX SMIAPP_REG_MK_U8(0x0807) -#define SMIAPP_REG_U8_DPHY_CTRL SMIAPP_REG_MK_U8(0x0808) -#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS SMIAPP_REG_MK_U32(0x0820) -#define SMIAPP_REG_U8_BINNING_MODE SMIAPP_REG_MK_U8(0x0900) -#define SMIAPP_REG_U8_BINNING_TYPE SMIAPP_REG_MK_U8(0x0901) -#define SMIAPP_REG_U8_BINNING_WEIGHTING SMIAPP_REG_MK_U8(0x0902) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL SMIAPP_REG_MK_U8(0x0a00) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS SMIAPP_REG_MK_U8(0x0a01) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a02) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 SMIAPP_REG_MK_U8(0x0a04) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 SMIAPP_REG_MK_U8(0x0a05) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 SMIAPP_REG_MK_U8(0x0a06) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 SMIAPP_REG_MK_U8(0x0a07) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 SMIAPP_REG_MK_U8(0x0a08) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 SMIAPP_REG_MK_U8(0x0a09) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 SMIAPP_REG_MK_U8(0x0a10) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 SMIAPP_REG_MK_U8(0x0a11) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 SMIAPP_REG_MK_U8(0x0a12) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 SMIAPP_REG_MK_U8(0x0a13) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 SMIAPP_REG_MK_U8(0x0a14) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 SMIAPP_REG_MK_U8(0x0a15) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 SMIAPP_REG_MK_U8(0x0a16) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 SMIAPP_REG_MK_U8(0x0a17) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 SMIAPP_REG_MK_U8(0x0a18) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 SMIAPP_REG_MK_U8(0x0a19) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 SMIAPP_REG_MK_U8(0x0a1a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 SMIAPP_REG_MK_U8(0x0a1b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 SMIAPP_REG_MK_U8(0x0a1c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 SMIAPP_REG_MK_U8(0x0a1d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 SMIAPP_REG_MK_U8(0x0a1e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 SMIAPP_REG_MK_U8(0x0a1f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 SMIAPP_REG_MK_U8(0x0a20) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 SMIAPP_REG_MK_U8(0x0a21) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 SMIAPP_REG_MK_U8(0x0a22) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 SMIAPP_REG_MK_U8(0x0a23) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 SMIAPP_REG_MK_U8(0x0a24) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 SMIAPP_REG_MK_U8(0x0a25) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 SMIAPP_REG_MK_U8(0x0a26) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 SMIAPP_REG_MK_U8(0x0a27) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 SMIAPP_REG_MK_U8(0x0a28) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 SMIAPP_REG_MK_U8(0x0a29) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 SMIAPP_REG_MK_U8(0x0a2a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 SMIAPP_REG_MK_U8(0x0a2b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 SMIAPP_REG_MK_U8(0x0a2c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 SMIAPP_REG_MK_U8(0x0a2d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 SMIAPP_REG_MK_U8(0x0a2e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 SMIAPP_REG_MK_U8(0x0a2f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 SMIAPP_REG_MK_U8(0x0a30) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 SMIAPP_REG_MK_U8(0x0a31) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 SMIAPP_REG_MK_U8(0x0a32) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 SMIAPP_REG_MK_U8(0x0a33) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 SMIAPP_REG_MK_U8(0x0a34) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 SMIAPP_REG_MK_U8(0x0a35) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 SMIAPP_REG_MK_U8(0x0a36) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 SMIAPP_REG_MK_U8(0x0a37) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 SMIAPP_REG_MK_U8(0x0a38) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 SMIAPP_REG_MK_U8(0x0a39) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 SMIAPP_REG_MK_U8(0x0a3a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 SMIAPP_REG_MK_U8(0x0a3b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 SMIAPP_REG_MK_U8(0x0a3c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 SMIAPP_REG_MK_U8(0x0a3d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 SMIAPP_REG_MK_U8(0x0a3e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 SMIAPP_REG_MK_U8(0x0a3f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 SMIAPP_REG_MK_U8(0x0a40) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 SMIAPP_REG_MK_U8(0x0a41) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 SMIAPP_REG_MK_U8(0x0a42) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 SMIAPP_REG_MK_U8(0x0a43) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL SMIAPP_REG_MK_U8(0x0a44) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS SMIAPP_REG_MK_U8(0x0a45) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a46) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 SMIAPP_REG_MK_U8(0x0a48) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 SMIAPP_REG_MK_U8(0x0a49) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 SMIAPP_REG_MK_U8(0x0a4a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 SMIAPP_REG_MK_U8(0x0a4b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 SMIAPP_REG_MK_U8(0x0a4c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 SMIAPP_REG_MK_U8(0x0a4d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 SMIAPP_REG_MK_U8(0x0a4e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 SMIAPP_REG_MK_U8(0x0a4f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 SMIAPP_REG_MK_U8(0x0a50) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 SMIAPP_REG_MK_U8(0x0a51) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 SMIAPP_REG_MK_U8(0x0a52) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 SMIAPP_REG_MK_U8(0x0a53) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 SMIAPP_REG_MK_U8(0x0a54) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 SMIAPP_REG_MK_U8(0x0a55) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 SMIAPP_REG_MK_U8(0x0a56) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 SMIAPP_REG_MK_U8(0x0a57) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 SMIAPP_REG_MK_U8(0x0a58) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 SMIAPP_REG_MK_U8(0x0a59) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 SMIAPP_REG_MK_U8(0x0a5a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 SMIAPP_REG_MK_U8(0x0a5b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 SMIAPP_REG_MK_U8(0x0a5c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 SMIAPP_REG_MK_U8(0x0a5d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 SMIAPP_REG_MK_U8(0x0a5e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 SMIAPP_REG_MK_U8(0x0a5f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 SMIAPP_REG_MK_U8(0x0a60) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 SMIAPP_REG_MK_U8(0x0a61) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 SMIAPP_REG_MK_U8(0x0a62) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 SMIAPP_REG_MK_U8(0x0a63) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 SMIAPP_REG_MK_U8(0x0a64) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 SMIAPP_REG_MK_U8(0x0a65) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 SMIAPP_REG_MK_U8(0x0a66) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 SMIAPP_REG_MK_U8(0x0a67) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 SMIAPP_REG_MK_U8(0x0a68) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 SMIAPP_REG_MK_U8(0x0a69) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 SMIAPP_REG_MK_U8(0x0a6a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 SMIAPP_REG_MK_U8(0x0a6b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 SMIAPP_REG_MK_U8(0x0a6c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 SMIAPP_REG_MK_U8(0x0a6d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 SMIAPP_REG_MK_U8(0x0a6e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 SMIAPP_REG_MK_U8(0x0a6f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 SMIAPP_REG_MK_U8(0x0a70) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 SMIAPP_REG_MK_U8(0x0a71) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 SMIAPP_REG_MK_U8(0x0a72) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 SMIAPP_REG_MK_U8(0x0a73) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 SMIAPP_REG_MK_U8(0x0a74) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 SMIAPP_REG_MK_U8(0x0a75) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 SMIAPP_REG_MK_U8(0x0a76) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 SMIAPP_REG_MK_U8(0x0a77) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 SMIAPP_REG_MK_U8(0x0a78) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 SMIAPP_REG_MK_U8(0x0a79) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 SMIAPP_REG_MK_U8(0x0a7a) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 SMIAPP_REG_MK_U8(0x0a7b) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 SMIAPP_REG_MK_U8(0x0a7c) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 SMIAPP_REG_MK_U8(0x0a7d) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 SMIAPP_REG_MK_U8(0x0a7e) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 SMIAPP_REG_MK_U8(0x0a7f) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 SMIAPP_REG_MK_U8(0x0a80) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 SMIAPP_REG_MK_U8(0x0a81) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 SMIAPP_REG_MK_U8(0x0a82) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 SMIAPP_REG_MK_U8(0x0a83) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 SMIAPP_REG_MK_U8(0x0a84) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 SMIAPP_REG_MK_U8(0x0a85) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 SMIAPP_REG_MK_U8(0x0a86) -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 SMIAPP_REG_MK_U8(0x0a87) -#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b00) -#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL SMIAPP_REG_MK_U8(0x0b01) -#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE SMIAPP_REG_MK_U8(0x0b02) -#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT SMIAPP_REG_MK_U8(0x0b03) -#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b04) -#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b05) -#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b06) -#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b07) -#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b08) -#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b09) -#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0a) -#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b0b) -#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b0c) -#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT SMIAPP_REG_MK_U8(0x0b0d) -#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0e) -#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b0f) -#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b10) -#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b11) -#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b12) -#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b13) -#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b14) -#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b15) -#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b16) -#define SMIAPP_REG_U8_EDOF_MODE SMIAPP_REG_MK_U8(0x0b80) -#define SMIAPP_REG_U8_SHARPNESS SMIAPP_REG_MK_U8(0x0b83) -#define SMIAPP_REG_U8_DENOISING SMIAPP_REG_MK_U8(0x0b84) -#define SMIAPP_REG_U8_MODULE_SPECIFIC SMIAPP_REG_MK_U8(0x0b85) -#define SMIAPP_REG_U16_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x0b86) -#define SMIAPP_REG_U16_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x0b88) -#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL SMIAPP_REG_MK_U8(0x0b8a) -#define SMIAPP_REG_U16_COLOUR_TEMPERATURE SMIAPP_REG_MK_U16(0x0b8c) -#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR SMIAPP_REG_MK_U16(0x0b8e) -#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED SMIAPP_REG_MK_U16(0x0b90) -#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE SMIAPP_REG_MK_U16(0x0b92) -#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB SMIAPP_REG_MK_U16(0x0b94) -#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE SMIAPP_REG_MK_U8(0x0bc0) -#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING SMIAPP_REG_MK_U16(0x0bc2) -#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START SMIAPP_REG_MK_U16(0x0bc4) -#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START SMIAPP_REG_MK_U16(0x0bc6) -#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH SMIAPP_REG_MK_U16(0x0bc8) -#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT SMIAPP_REG_MK_U16(0x0bca) -#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 SMIAPP_REG_MK_U8(0x0c00) -#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 SMIAPP_REG_MK_U8(0x0c01) -#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 SMIAPP_REG_MK_U8(0x0c02) -#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 SMIAPP_REG_MK_U8(0x0c03) -#define SMIAPP_REG_U16_TRDY_CTRL SMIAPP_REG_MK_U16(0x0c04) -#define SMIAPP_REG_U16_TRDOUT_CTRL SMIAPP_REG_MK_U16(0x0c06) -#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c08) -#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c0a) -#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c0c) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c0e) -#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL SMIAPP_REG_MK_U16(0x0c10) -#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT SMIAPP_REG_MK_U8(0x0c12) -#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c14) -#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL SMIAPP_REG_MK_U16(0x0c16) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c18) -#define SMIAPP_REG_U8_FLASH_MODE_RS SMIAPP_REG_MK_U8(0x0c1a) -#define SMIAPP_REG_U8_FLASH_TRIGGER_RS SMIAPP_REG_MK_U8(0x0c1b) -#define SMIAPP_REG_U8_FLASH_STATUS SMIAPP_REG_MK_U8(0x0c1c) -#define SMIAPP_REG_U8_SA_STROBE_MODE SMIAPP_REG_MK_U8(0x0c1d) -#define SMIAPP_REG_U16_SA_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c1e) -#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c20) -#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c22) -#define SMIAPP_REG_U8_SA_STROBE_TRIGGER SMIAPP_REG_MK_U8(0x0c24) -#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS SMIAPP_REG_MK_U8(0x0c25) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c26) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL SMIAPP_REG_MK_U16(0x0c28) -#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL SMIAPP_REG_MK_U8(0x0c2a) -#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL SMIAPP_REG_MK_U8(0x0c2b) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c2c) -#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL SMIAPP_REG_MK_U16(0x0c2e) -#define SMIAPP_REG_U8_LOW_LEVEL_CTRL SMIAPP_REG_MK_U8(0x0c80) -#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT SMIAPP_REG_MK_U16(0x0c82) -#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c84) -#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c86) -#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c88) -#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8a) -#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c8c) -#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8e) -#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL SMIAPP_REG_MK_U8(0x0d00) -#define SMIAPP_REG_U8_OPERATION_MODE SMIAPP_REG_MK_U8(0x0d01) -#define SMIAPP_REG_U8_ACT_STATE1 SMIAPP_REG_MK_U8(0x0d02) -#define SMIAPP_REG_U8_ACT_STATE2 SMIAPP_REG_MK_U8(0x0d03) -#define SMIAPP_REG_U16_FOCUS_CHANGE SMIAPP_REG_MK_U16(0x0d80) -#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL SMIAPP_REG_MK_U16(0x0d82) -#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 SMIAPP_REG_MK_U16(0x0d84) -#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 SMIAPP_REG_MK_U16(0x0d86) -#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 SMIAPP_REG_MK_U8(0x0d88) -#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 SMIAPP_REG_MK_U8(0x0d89) -#define SMIAPP_REG_U8_POSITION SMIAPP_REG_MK_U8(0x0d8a) -#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL SMIAPP_REG_MK_U8(0x0e00) -#define SMIAPP_REG_U8_BRACKETING_LUT_MODE SMIAPP_REG_MK_U8(0x0e01) -#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL SMIAPP_REG_MK_U8(0x0e02) -#define SMIAPP_REG_U8_LUT_PARAMETERS_START SMIAPP_REG_MK_U8(0x0e10) -#define SMIAPP_REG_U8_LUT_PARAMETERS_END SMIAPP_REG_MK_U8(0x0eff) -#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY SMIAPP_REG_MK_U16(0x1000) -#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1004) -#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x1006) -#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1008) -#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x100a) -#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x1080) -#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN SMIAPP_REG_MK_U16(0x1084) -#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX SMIAPP_REG_MK_U16(0x1086) -#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE SMIAPP_REG_MK_U16(0x1088) -#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1100) -#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1104) -#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x1108) -#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x110a) -#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x110c) -#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x1110) -#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1114) -#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1116) -#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x1118) -#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x111c) -#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1120) -#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1122) -#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1124) -#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1128) -#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x112c) -#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1130) -#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1134) -#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1136) -#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1140) -#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1142) -#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1144) -#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1146) -#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK SMIAPP_REG_MK_U16(0x1148) -#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES SMIAPP_REG_MK_U16(0x114a) -#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE SMIAPP_REG_MK_U8(0x114c) -#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1160) -#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1162) -#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1164) -#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1168) -#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116c) -#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116e) -#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1170) -#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1174) -#define SMIAPP_REG_U16_X_ADDR_MIN SMIAPP_REG_MK_U16(0x1180) -#define SMIAPP_REG_U16_Y_ADDR_MIN SMIAPP_REG_MK_U16(0x1182) -#define SMIAPP_REG_U16_X_ADDR_MAX SMIAPP_REG_MK_U16(0x1184) -#define SMIAPP_REG_U16_Y_ADDR_MAX SMIAPP_REG_MK_U16(0x1186) -#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x1188) -#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118a) -#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118c) -#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118e) -#define SMIAPP_REG_U16_MIN_EVEN_INC SMIAPP_REG_MK_U16(0x11c0) -#define SMIAPP_REG_U16_MAX_EVEN_INC SMIAPP_REG_MK_U16(0x11c2) -#define SMIAPP_REG_U16_MIN_ODD_INC SMIAPP_REG_MK_U16(0x11c4) -#define SMIAPP_REG_U16_MAX_ODD_INC SMIAPP_REG_MK_U16(0x11c6) -#define SMIAPP_REG_U16_SCALING_CAPABILITY SMIAPP_REG_MK_U16(0x1200) -#define SMIAPP_REG_U16_SCALER_M_MIN SMIAPP_REG_MK_U16(0x1204) -#define SMIAPP_REG_U16_SCALER_M_MAX SMIAPP_REG_MK_U16(0x1206) -#define SMIAPP_REG_U16_SCALER_N_MIN SMIAPP_REG_MK_U16(0x1208) -#define SMIAPP_REG_U16_SCALER_N_MAX SMIAPP_REG_MK_U16(0x120a) -#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY SMIAPP_REG_MK_U16(0x120c) -#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY SMIAPP_REG_MK_U8(0x120e) -#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY SMIAPP_REG_MK_U16(0x1300) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED SMIAPP_REG_MK_U16(0x1400) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED SMIAPP_REG_MK_U16(0x1402) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED SMIAPP_REG_MK_U16(0x1404) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN SMIAPP_REG_MK_U16(0x1406) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN SMIAPP_REG_MK_U16(0x1408) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN SMIAPP_REG_MK_U16(0x140a) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE SMIAPP_REG_MK_U16(0x140c) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE SMIAPP_REG_MK_U16(0x140e) -#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE SMIAPP_REG_MK_U16(0x1410) -#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS SMIAPP_REG_MK_U16(0x1500) -#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY SMIAPP_REG_MK_U8(0x1502) -#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY SMIAPP_REG_MK_U8(0x1600) -#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1601) -#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1602) -#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY SMIAPP_REG_MK_U8(0x1603) -#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY SMIAPP_REG_MK_U8(0x1604) -#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1608) -#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x160c) -#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1610) -#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1614) -#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY SMIAPP_REG_MK_U8(0x1618) -#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1700) -#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1702) -#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1704) -#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1706) -#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN SMIAPP_REG_MK_U16(0x1708) -#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN SMIAPP_REG_MK_U16(0x170a) -#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN SMIAPP_REG_MK_U16(0x170c) -#define SMIAPP_REG_U8_BINNING_CAPABILITY SMIAPP_REG_MK_U8(0x1710) -#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY SMIAPP_REG_MK_U8(0x1711) -#define SMIAPP_REG_U8_BINNING_SUBTYPES SMIAPP_REG_MK_U8(0x1712) -#define SMIAPP_REG_U8_BINNING_TYPE_n(n) SMIAPP_REG_MK_U8(0x1713 + (n)) /* 1 <= n <= 237 */ -#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY SMIAPP_REG_MK_U8(0x1800) -#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1900) -#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY SMIAPP_REG_MK_U8(0x1901) -#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY SMIAPP_REG_MK_U8(0x1902) -#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1903) -#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY SMIAPP_REG_MK_U16(0x1904) -#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 SMIAPP_REG_MK_U16(0x1906) -#define SMIAPP_REG_U8_EDOF_CAPABILITY SMIAPP_REG_MK_U8(0x1980) -#define SMIAPP_REG_U8_ESTIMATION_FRAMES SMIAPP_REG_MK_U8(0x1981) -#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ SMIAPP_REG_MK_U8(0x1982) -#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ SMIAPP_REG_MK_U8(0x1983) -#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ SMIAPP_REG_MK_U8(0x1984) -#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ SMIAPP_REG_MK_U8(0x1985) -#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ SMIAPP_REG_MK_U8(0x1986) -#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY SMIAPP_REG_MK_U8(0x1987) -#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM SMIAPP_REG_MK_U8(0x1988) -#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x19c0) -#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY SMIAPP_REG_MK_U8(0x19c1) -#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x19c2) -#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x19c4) -#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN SMIAPP_REG_MK_U16(0x1a00) -#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1a02) -#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR SMIAPP_REG_MK_U16(0x1b02) -#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY SMIAPP_REG_MK_U8(0x1b04) -#define SMIAPP_REG_U16_ACTUATOR_TYPE SMIAPP_REG_MK_U16(0x1b40) -#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS SMIAPP_REG_MK_U8(0x1b42) -#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS SMIAPP_REG_MK_U16(0x1b44) -#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 SMIAPP_REG_MK_U8(0x1c00) -#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 SMIAPP_REG_MK_U8(0x1c01) -#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE SMIAPP_REG_MK_U8(0x1c02) +/* Register addresses */ +#define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002 +#define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003 +#define SMIAPP_REG_U8_SMIA_VERSION 0x0004 +#define SMIAPP_REG_U8_FRAME_COUNT 0x0005 +#define SMIAPP_REG_U8_PIXEL_ORDER 0x0006 +#define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c +#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010 +#define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011 +#define SMIAPP_REG_U8_MODULE_DATE_YEAR 0x0012 +#define SMIAPP_REG_U8_MODULE_DATE_MONTH 0x0013 +#define SMIAPP_REG_U8_MODULE_DATE_DAY 0x0014 +#define SMIAPP_REG_U8_MODULE_DATE_PHASE 0x0015 +#define SMIAPP_REG_U16_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER 0x0018 +#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID 0x0019 +#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION 0x001a +#define SMIAPP_REG_U32_SERIAL_NUMBER (0x001c | CCS_FL_32BIT) +#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE 0x0040 +#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE 0x0041 +#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) ((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */ +#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */ +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE (0x008a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 (0x008c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 (0x008e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 (0x0090 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 (0x0092 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE 0x00c0 +#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE 0x00c1 +#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 + ((n) << 1)) | CCS_FL_16BIT) +#define SMIAPP_REG_U8_MODE_SELECT 0x0100 +#define SMIAPP_REG_U8_IMAGE_ORIENTATION 0x0101 +#define SMIAPP_REG_U8_SOFTWARE_RESET 0x0103 +#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD 0x0104 +#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES 0x0105 +#define SMIAPP_REG_U8_FAST_STANDBY_CTRL 0x0106 +#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL 0x0107 +#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL 0x0108 +#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL 0x0109 +#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER 0x0110 +#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE 0x0111 +#define SMIAPP_REG_U16_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_CSI_LANE_MODE 0x0114 +#define SMIAPP_REG_U8_CSI2_10_TO_8_DT 0x0115 +#define SMIAPP_REG_U8_CSI2_10_TO_7_DT 0x0116 +#define SMIAPP_REG_U8_CSI2_10_TO_6_DT 0x0117 +#define SMIAPP_REG_U8_CSI2_12_TO_8_DT 0x0118 +#define SMIAPP_REG_U8_CSI2_12_TO_7_DT 0x0119 +#define SMIAPP_REG_U8_CSI2_12_TO_6_DT 0x011a +#define SMIAPP_REG_U8_CSI2_14_TO_10_DT 0x011b +#define SMIAPP_REG_U8_CSI2_14_TO_8_DT 0x011c +#define SMIAPP_REG_U8_CSI2_16_TO_10_DT 0x011d +#define SMIAPP_REG_U8_CSI2_16_TO_8_DT 0x011e +#define SMIAPP_REG_U8_GAIN_MODE 0x0120 +#define SMIAPP_REG_U16_VANA_VOLTAGE (0x0130 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VDIG_VOLTAGE (0x0132 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VIO_VOLTAGE (0x0134 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ (0x0136 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL 0x0138 +#define SMIAPP_REG_U8_TEMP_SENSOR_MODE 0x0139 +#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT 0x013a +#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR (0x0206 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED (0x0208 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE (0x020a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB (0x020c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR (0x020e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_RED (0x0210 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE (0x0212 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB (0x0214 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_ADDR_START (0x0344 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_ADDR_START (0x0346 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_ADDR_END (0x0348 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_ADDR_END (0x034a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_EVEN_INC (0x0380 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_ODD_INC (0x0382 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_EVEN_INC (0x0384 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_ODD_INC (0x0386 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALING_MODE (0x0400 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SPATIAL_SAMPLING (0x0402 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALE_M (0x0404 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALE_N (0x0406 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TEST_DATA_RED (0x0602 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH (0x060a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION (0x060c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH (0x060e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION (0x0610 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS (0x0700 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_TCLK_POST 0x0800 +#define SMIAPP_REG_U8_THS_PREPARE 0x0801 +#define SMIAPP_REG_U8_THS_ZERO_MIN 0x0802 +#define SMIAPP_REG_U8_THS_TRAIL 0x0803 +#define SMIAPP_REG_U8_TCLK_TRAIL_MIN 0x0804 +#define SMIAPP_REG_U8_TCLK_PREPARE 0x0805 +#define SMIAPP_REG_U8_TCLK_ZERO 0x0806 +#define SMIAPP_REG_U8_TLPX 0x0807 +#define SMIAPP_REG_U8_DPHY_CTRL 0x0808 +#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS (0x0820 | CCS_FL_32BIT) +#define SMIAPP_REG_U8_BINNING_MODE 0x0900 +#define SMIAPP_REG_U8_BINNING_TYPE 0x0901 +#define SMIAPP_REG_U8_BINNING_WEIGHTING 0x0902 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL 0x0a00 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS 0x0a01 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 0x0a04 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 0x0a05 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 0x0a06 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 0x0a07 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 0x0a08 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 0x0a09 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 0x0a10 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 0x0a11 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 0x0a12 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 0x0a13 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 0x0a14 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 0x0a15 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 0x0a16 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 0x0a17 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 0x0a18 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 0x0a19 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 0x0a1a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 0x0a1b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 0x0a1c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 0x0a1d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 0x0a1e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 0x0a1f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 0x0a20 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 0x0a21 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 0x0a22 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 0x0a23 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 0x0a24 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 0x0a25 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 0x0a26 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 0x0a27 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 0x0a28 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 0x0a29 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 0x0a2a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 0x0a2b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 0x0a2c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 0x0a2d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 0x0a2e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 0x0a2f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 0x0a30 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 0x0a31 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 0x0a32 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 0x0a33 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 0x0a34 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 0x0a35 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 0x0a36 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 0x0a37 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 0x0a38 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 0x0a39 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 0x0a3a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 0x0a3b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 0x0a3c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 0x0a3d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 0x0a3e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 0x0a3f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 0x0a40 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 0x0a41 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 0x0a42 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 0x0a43 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL 0x0a44 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS 0x0a45 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT 0x0a46 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 0x0a48 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 0x0a49 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 0x0a4a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 0x0a4b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 0x0a4c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 0x0a4d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 0x0a4e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 0x0a4f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 0x0a50 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 0x0a51 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 0x0a52 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 0x0a53 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 0x0a54 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 0x0a55 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 0x0a56 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 0x0a57 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 0x0a58 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 0x0a59 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 0x0a5a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 0x0a5b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 0x0a5c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 0x0a5d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 0x0a5e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 0x0a5f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 0x0a60 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 0x0a61 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 0x0a62 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 0x0a63 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 0x0a64 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 0x0a65 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 0x0a66 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 0x0a67 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 0x0a68 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 0x0a69 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 0x0a6a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 0x0a6b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 0x0a6c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 0x0a6d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 0x0a6e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 0x0a6f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 0x0a70 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 0x0a71 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 0x0a72 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 0x0a73 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 0x0a74 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 0x0a75 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 0x0a76 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 0x0a77 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 0x0a78 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 0x0a79 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 0x0a7a +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 0x0a7b +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 0x0a7c +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 0x0a7d +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 0x0a7e +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 0x0a7f +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 0x0a80 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 0x0a81 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 0x0a82 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 0x0a83 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 0x0a84 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 0x0a85 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 0x0a86 +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 0x0a87 +#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE 0x0b00 +#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL 0x0b01 +#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE 0x0b02 +#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT 0x0b03 +#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE 0x0b04 +#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE 0x0b05 +#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE 0x0b06 +#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT 0x0b07 +#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE 0x0b08 +#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT 0x0b09 +#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE 0x0b0a +#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT 0x0b0b +#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE 0x0b0c +#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT 0x0b0d +#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE 0x0b0e +#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST 0x0b0f +#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST 0x0b10 +#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b11 +#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b12 +#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b13 +#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b14 +#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE 0x0b15 +#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST 0x0b16 +#define SMIAPP_REG_U8_EDOF_MODE 0x0b80 +#define SMIAPP_REG_U8_SHARPNESS 0x0b83 +#define SMIAPP_REG_U8_DENOISING 0x0b84 +#define SMIAPP_REG_U8_MODULE_SPECIFIC 0x0b85 +#define SMIAPP_REG_U16_DEPTH_OF_FIELD (0x0b86 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FOCUS_DISTANCE (0x0b88 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL 0x0b8a +#define SMIAPP_REG_U16_COLOUR_TEMPERATURE (0x0b8c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE 0x0bc0 +#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING (0x0bc2 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START (0x0bc4 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START (0x0bc6 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH (0x0bc8 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT (0x0bca | CCS_FL_16BIT) +#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 0x0c00 +#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 0x0c01 +#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 0x0c02 +#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 0x0c03 +#define SMIAPP_REG_U16_TRDY_CTRL (0x0c04 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TRDOUT_CTRL (0x0c06 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL (0x0c08 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL (0x0c0a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL (0x0c0c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL (0x0c0e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL (0x0c10 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT 0x0c12 +#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_FLASH_MODE_RS 0x0c1a +#define SMIAPP_REG_U8_FLASH_TRIGGER_RS 0x0c1b +#define SMIAPP_REG_U8_FLASH_STATUS 0x0c1c +#define SMIAPP_REG_U8_SA_STROBE_MODE 0x0c1d +#define SMIAPP_REG_U16_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_SA_STROBE_TRIGGER 0x0c24 +#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS 0x0c25 +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL (0x0c26 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL (0x0c28 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL 0x0c2a +#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL 0x0c2b +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL (0x0c2c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL (0x0c2e | CCS_FL_16BIT) +#define SMIAPP_REG_U8_LOW_LEVEL_CTRL 0x0c80 +#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT (0x0c82 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 (0x0c84 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT 0x0c86 +#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 (0x0c88 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT 0x0c8a +#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 (0x0c8c | CCS_FL_16BIT) +#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT 0x0c8e +#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL 0x0d00 +#define SMIAPP_REG_U8_OPERATION_MODE 0x0d01 +#define SMIAPP_REG_U8_ACT_STATE1 0x0d02 +#define SMIAPP_REG_U8_ACT_STATE2 0x0d03 +#define SMIAPP_REG_U16_FOCUS_CHANGE (0x0d80 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL (0x0d82 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 (0x0d84 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 (0x0d86 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 0x0d88 +#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 0x0d89 +#define SMIAPP_REG_U8_POSITION 0x0d8a +#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL 0x0e00 +#define SMIAPP_REG_U8_BRACKETING_LUT_MODE 0x0e01 +#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL 0x0e02 +#define SMIAPP_REG_U8_LUT_PARAMETERS_START 0x0e10 +#define SMIAPP_REG_U8_LUT_PARAMETERS_END 0x0eff +#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY (0x1080 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ (0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ (0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ (0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT) +#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c +#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ (0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ (0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT) +#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ (0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ (0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT) +#define SMIAPP_REG_U16_X_ADDR_MIN (0x1180 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_X_ADDR_MAX (0x1184 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_EVEN_INC (0x11c2 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_ODD_INC (0x11c4 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALER_M_MIN (0x1204 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALER_M_MAX (0x1206 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALER_N_MIN (0x1208 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SCALER_N_MAX (0x120a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY (0x120c | CCS_FL_16BIT) +#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY 0x120e +#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY (0x1300 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED (0x1400 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED (0x1402 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED (0x1404 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN (0x1406 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN (0x1408 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN (0x140a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE (0x140c | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE (0x140e | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE (0x1410 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS (0x1500 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY 0x1502 +#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY 0x1600 +#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY 0x1601 +#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY 0x1602 +#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY 0x1603 +#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY 0x1604 +#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS (0x1608 | CCS_FL_32BIT) +#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS (0x160c | CCS_FL_32BIT) +#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS (0x1610 | CCS_FL_32BIT) +#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS (0x1614 | CCS_FL_32BIT) +#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY 0x1618 +#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT) +#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT) +#define SMIAPP_REG_U8_BINNING_CAPABILITY 0x1710 +#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY 0x1711 +#define SMIAPP_REG_U8_BINNING_SUBTYPES 0x1712 +#define SMIAPP_REG_U8_BINNING_TYPE_n(n) (0x1713 + (n)) /* 1 <= n <= 237 */ +#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY 0x1800 +#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY 0x1900 +#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY 0x1901 +#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY 0x1902 +#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903 +#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_EDOF_CAPABILITY 0x1980 +#define SMIAPP_REG_U8_ESTIMATION_FRAMES 0x1981 +#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ 0x1982 +#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ 0x1983 +#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ 0x1984 +#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ 0x1985 +#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ 0x1986 +#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY 0x1987 +#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM 0x1988 +#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY 0x19c0 +#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY 0x19c1 +#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD (0x19c2 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE (0x19c4 | CCS_FL_16BIT) +#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN (0x1a00 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY 0x1a02 +#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR (0x1b02 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY 0x1b04 +#define SMIAPP_REG_U16_ACTUATOR_TYPE (0x1b40 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS 0x1b42 +#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS (0x1b44 | CCS_FL_16BIT) +#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 0x1c00 +#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 0x1c01 +#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE 0x1c02 + +/* Register bit definitions */ +#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0) +#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1) + +#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0) +#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1) +#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2) +#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0) +#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1) +#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2) +#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3) + +#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0) +#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2) + +#define SMIAPP_SOFTWARE_RESET BIT(0) + +#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0) +#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1) + +#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0 +#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1 +#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2 + +#define SMIAPP_DPHY_CTRL_AUTOMATIC 0 +/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */ +#define SMIAPP_DPHY_CTRL_UI 1 +#define SMIAPP_DPHY_CTRL_REGISTER 2 + +#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1 +#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2 + +#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0 +#define SMIAPP_MODE_SELECT_STREAMING 1 + +#define SMIAPP_SCALING_MODE_NONE 0 +#define SMIAPP_SCALING_MODE_HORIZONTAL 1 +#define SMIAPP_SCALING_MODE_BOTH 2 + +#define SMIAPP_SCALING_CAPABILITY_NONE 0 +#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1 +#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */ + +/* digital crop right before scaler */ +#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0 +#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1 + +#define SMIAPP_BINNING_CAPABILITY_NO 0 +#define SMIAPP_BINNING_CAPABILITY_YES 1 + +/* Maximum number of binning subtypes */ +#define SMIAPP_BINNING_SUBTYPES 253 + +#define SMIAPP_PIXEL_ORDER_GRBG 0 +#define SMIAPP_PIXEL_ORDER_RGGB 1 +#define SMIAPP_PIXEL_ORDER_BGGR 2 +#define SMIAPP_PIXEL_ORDER_GBRG 3 + +#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1 +#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2 +#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8 +#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16 + +#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01 +#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02 +#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f +#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0 +#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4 + +#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000 +#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12 +#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff + +#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000 +#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28 +#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff + +#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1 +#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2 +#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3 +#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4 +#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5 + +#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0 +#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1 + +/* Scaling N factor */ +#define SMIAPP_SCALE_N 16 + +#endif /* __SMIAPP_REG_DEFS_H__ */ diff --git a/drivers/media/i2c/smiapp/smiapp-reg.h b/drivers/media/i2c/smiapp/smiapp-reg.h deleted file mode 100644 index e6f96309786f..000000000000 --- a/drivers/media/i2c/smiapp/smiapp-reg.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * drivers/media/i2c/smiapp/smiapp-reg.h - * - * Generic driver for SMIA/SMIA++ compliant camera modules - * - * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus - */ - -#ifndef __SMIAPP_REG_H_ -#define __SMIAPP_REG_H_ - -#include - -#include "smiapp-reg-defs.h" - -/* Bits for above register */ -#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0) -#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1) - -#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0) -#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1) -#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2) -#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0) -#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1) -#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2) -#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3) - -#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0) -#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2) - -#define SMIAPP_SOFTWARE_RESET BIT(0) - -#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0) -#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1) - -#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0 -#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1 -#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2 - -#define SMIAPP_DPHY_CTRL_AUTOMATIC 0 -/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */ -#define SMIAPP_DPHY_CTRL_UI 1 -#define SMIAPP_DPHY_CTRL_REGISTER 2 - -#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1 -#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2 - -#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0 -#define SMIAPP_MODE_SELECT_STREAMING 1 - -#define SMIAPP_SCALING_MODE_NONE 0 -#define SMIAPP_SCALING_MODE_HORIZONTAL 1 -#define SMIAPP_SCALING_MODE_BOTH 2 - -#define SMIAPP_SCALING_CAPABILITY_NONE 0 -#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1 -#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */ - -/* digital crop right before scaler */ -#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0 -#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1 - -#define SMIAPP_BINNING_CAPABILITY_NO 0 -#define SMIAPP_BINNING_CAPABILITY_YES 1 - -/* Maximum number of binning subtypes */ -#define SMIAPP_BINNING_SUBTYPES 253 - -#define SMIAPP_PIXEL_ORDER_GRBG 0 -#define SMIAPP_PIXEL_ORDER_RGGB 1 -#define SMIAPP_PIXEL_ORDER_BGGR 2 -#define SMIAPP_PIXEL_ORDER_GBRG 3 - -#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1 -#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2 -#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8 -#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16 - -#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01 -#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02 -#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f -#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0 -#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4 - -#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000 -#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12 -#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff - -#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000 -#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28 -#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff - -#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1 -#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2 -#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3 -#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4 -#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5 - -#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0 -#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1 - -/* Scaling N factor */ -#define SMIAPP_SCALE_N 16 - -/* Image statistics registers */ -/* Registers 0x2000 to 0x2fff are reserved for future - * use for statistics features. - */ - -/* Manufacturer Specific Registers: 0x3000 to 0x3fff - * The manufacturer specifies these as a black box. - */ - -#endif /* __SMIAPP_REG_H_ */ diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h index 6f469934f9e3..7cef97db7f47 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/smiapp.h @@ -16,7 +16,7 @@ #include #include "smiapp-pll.h" -#include "smiapp-reg.h" +#include "smiapp-reg-defs.h" #include "smiapp-regs.h" #include "smiapp-quirk.h" From patchwork Wed Sep 30 15:27:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809657 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6223D618 for ; Wed, 30 Sep 2020 15:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 503C422207 for ; Wed, 30 Sep 2020 15:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730722AbgI3Pab (ORCPT ); Wed, 30 Sep 2020 11:30:31 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729351AbgI3P3C (ORCPT ); Wed, 30 Sep 2020 11:29:02 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 7C667634C8F for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 005/100] smiapp: Add macros for accessing CCS registers Date: Wed, 30 Sep 2020 18:27:23 +0300 Message-Id: <20200930152858.8471-6-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add two helper macros for reading and writing the CCS registers as defined in ccs-regs.h. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h index 7223f5f89109..dc946096f368 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.h +++ b/drivers/media/i2c/smiapp/smiapp-regs.h @@ -28,4 +28,10 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val); unsigned int ccs_reg_width(u32 reg); +#define ccs_read(sensor, reg_name, val) \ + smiapp_read(sensor, CCS_R_##reg_name, val) + +#define ccs_write(sensor, reg_name, val) \ + smiapp_write(sensor, CCS_R_##reg_name, val) + #endif From patchwork Wed Sep 30 15:27:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809653 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7428618 for ; Wed, 30 Sep 2020 15:30:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1F0821D7F for ; Wed, 30 Sep 2020 15:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731187AbgI3Pa3 (ORCPT ); Wed, 30 Sep 2020 11:30:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730813AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A788AC0613D0 for ; Wed, 30 Sep 2020 08:29:02 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 8CE8E634C90 for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 006/100] smiapp: Use MIPI CCS version and manufacturer ID information Date: Wed, 30 Sep 2020 18:27:24 +0300 Message-Id: <20200930152858.8471-7-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Read MIPI CCS manufacturer and version information, and use the CCS IDs over SMIA whenever they are set. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 76 +++++++++++++++++++------- drivers/media/i2c/smiapp/smiapp.h | 20 ++++--- 2 files changed, 68 insertions(+), 28 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index 47e983e9cd87..10900ac4aa1a 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -2356,9 +2356,14 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr, struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); struct smiapp_module_info *minfo = &sensor->minfo; - return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n", - minfo->manufacturer_id, minfo->model_id, - minfo->revision_number_major) + 1; + if (minfo->mipi_manufacturer_id) + return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n", + minfo->mipi_manufacturer_id, minfo->model_id, + minfo->revision_number_major) + 1; + else + return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n", + minfo->smia_manufacturer_id, minfo->model_id, + minfo->revision_number_major) + 1; } static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL); @@ -2377,8 +2382,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) minfo->name = SMIAPP_NAME; /* Module info */ - rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID, - &minfo->manufacturer_id); + rval = ccs_read(sensor, MODULE_MANUFACTURER_ID, + &minfo->mipi_manufacturer_id); + if (!rval && !minfo->mipi_manufacturer_id) + rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID, + &minfo->smia_manufacturer_id); if (!rval) rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID, &minfo->model_id); @@ -2404,9 +2412,12 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) /* Sensor info */ if (!rval) + rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID, + &minfo->sensor_mipi_manufacturer_id); + if (!rval && !minfo->sensor_mipi_manufacturer_id) rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID, - &minfo->sensor_manufacturer_id); + &minfo->sensor_smia_manufacturer_id); if (!rval) rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_SENSOR_MODEL_ID, @@ -2422,9 +2433,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) /* SMIA */ if (!rval) + rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version); + if (!rval && !minfo->ccs_version) rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION, &minfo->smia_version); - if (!rval) + if (!rval && !minfo->ccs_version) rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION, &minfo->smiapp_version); @@ -2433,38 +2446,62 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) return -ENODEV; } - dev_dbg(&client->dev, "module 0x%2.2x-0x%4.4x\n", - minfo->manufacturer_id, minfo->model_id); + if (minfo->mipi_manufacturer_id) + dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n", + minfo->mipi_manufacturer_id, minfo->model_id); + else + dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n", + minfo->smia_manufacturer_id, minfo->model_id); dev_dbg(&client->dev, "module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n", minfo->revision_number_major, minfo->revision_number_minor, minfo->module_year, minfo->module_month, minfo->module_day); - dev_dbg(&client->dev, "sensor 0x%2.2x-0x%4.4x\n", - minfo->sensor_manufacturer_id, minfo->sensor_model_id); + if (minfo->sensor_mipi_manufacturer_id) + dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n", + minfo->sensor_mipi_manufacturer_id, + minfo->sensor_model_id); + else + dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n", + minfo->sensor_smia_manufacturer_id, + minfo->sensor_model_id); dev_dbg(&client->dev, "sensor revision 0x%2.2x firmware version 0x%2.2x\n", minfo->sensor_revision_number, minfo->sensor_firmware_version); - dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n", - minfo->smia_version, minfo->smiapp_version); + if (minfo->ccs_version) + dev_dbg(&client->dev, "MIPI CCS version %u.%u", + (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK) + >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT, + (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK)); + else + dev_dbg(&client->dev, + "smia version %2.2d smiapp version %2.2d\n", + minfo->smia_version, minfo->smiapp_version); /* * Some modules have bad data in the lvalues below. Hope the * rvalues have better stuff. The lvalues are module * parameters whereas the rvalues are sensor parameters. */ - if (!minfo->manufacturer_id && !minfo->model_id) { - minfo->manufacturer_id = minfo->sensor_manufacturer_id; + if (minfo->sensor_smia_manufacturer_id && + !minfo->smia_manufacturer_id && !minfo->model_id) { + minfo->smia_manufacturer_id = + minfo->sensor_smia_manufacturer_id; minfo->model_id = minfo->sensor_model_id; minfo->revision_number_major = minfo->sensor_revision_number; } for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) { - if (smiapp_module_idents[i].manufacturer_id - != minfo->manufacturer_id) + if (smiapp_module_idents[i].mipi_manufacturer_id && + smiapp_module_idents[i].mipi_manufacturer_id + != minfo->mipi_manufacturer_id) + continue; + if (smiapp_module_idents[i].smia_manufacturer_id && + smiapp_module_idents[i].smia_manufacturer_id + != minfo->smia_manufacturer_id) continue; if (smiapp_module_idents[i].model_id != minfo->model_id) continue; @@ -2488,9 +2525,8 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) dev_warn(&client->dev, "no quirks for this module; let's hope it's fully compliant\n"); - dev_dbg(&client->dev, "the sensor is called %s, ident %2.2x%4.4x%2.2x\n", - minfo->name, minfo->manufacturer_id, minfo->model_id, - minfo->revision_number_major); + dev_dbg(&client->dev, "the sensor is called %s\n", + minfo->name); return 0; } diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h index 7cef97db7f47..b1d0e3d71630 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/smiapp.h @@ -91,8 +91,9 @@ struct smiapp_quirk; #define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0) struct smiapp_module_ident { - u8 manufacturer_id; + u16 mipi_manufacturer_id; u16 model_id; + u8 smia_manufacturer_id; u8 revision_number_major; u8 flags; @@ -102,7 +103,8 @@ struct smiapp_module_ident { }; struct smiapp_module_info { - u32 manufacturer_id; + u32 smia_manufacturer_id; + u32 mipi_manufacturer_id; u32 model_id; u32 revision_number_major; u32 revision_number_minor; @@ -111,13 +113,15 @@ struct smiapp_module_info { u32 module_month; u32 module_day; - u32 sensor_manufacturer_id; + u32 sensor_smia_manufacturer_id; + u32 sensor_mipi_manufacturer_id; u32 sensor_model_id; u32 sensor_revision_number; u32 sensor_firmware_version; u32 smia_version; u32 smiapp_version; + u32 ccs_version; u32 smiapp_profile; @@ -126,7 +130,7 @@ struct smiapp_module_info { }; #define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \ - { .manufacturer_id = manufacturer, \ + { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = fl, \ @@ -134,7 +138,7 @@ struct smiapp_module_info { .quirk = _quirk, } #define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \ - { .manufacturer_id = manufacturer, \ + { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \ @@ -142,14 +146,14 @@ struct smiapp_module_info { .quirk = _quirk, } #define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \ - { .manufacturer_id = manufacturer, \ + { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \ .name = _name, } #define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \ - { .manufacturer_id = manufacturer, \ + { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = 0, \ @@ -157,7 +161,7 @@ struct smiapp_module_info { .quirk = _quirk, } #define SMIAPP_IDENT(manufacturer, model, rev, _name) \ - { .manufacturer_id = manufacturer, \ + { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = 0, \ From patchwork Wed Sep 30 15:27:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74BBB139A for ; Wed, 30 Sep 2020 15:30:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61C652074A for ; Wed, 30 Sep 2020 15:30:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731195AbgI3Paa (ORCPT ); Wed, 30 Sep 2020 11:30:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730791AbgI3P3C (ORCPT ); Wed, 30 Sep 2020 11:29:02 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0751C061755 for ; Wed, 30 Sep 2020 08:29:02 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A24F3634C91 for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 007/100] smiapp: Read CCS limit values Date: Wed, 30 Sep 2020 18:27:25 +0300 Message-Id: <20200930152858.8471-8-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Read limit and capability values into a driver allocated buffer. This will later replace (most of) the existing SMIA limits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 177 ++++++++++++++++++++++++- drivers/media/i2c/smiapp/smiapp.h | 4 + 2 files changed, 176 insertions(+), 5 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index 10900ac4aa1a..42df98740445 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -28,6 +28,7 @@ #include #include "ccs-limits.h" +#include "ccs-regs.h" #include "smiapp.h" #define SMIAPP_ALIGN_DIM(dim, flags) \ @@ -102,6 +103,164 @@ static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor) return 0; } +static void ccs_assign_limit(void *ptr, unsigned int width, u32 val) +{ + switch (width) { + case sizeof(u8): + *(u8 *)ptr = val; + break; + case sizeof(u16): + *(u16 *)ptr = val; + break; + case sizeof(u32): + *(u32 *)ptr = val; + break; + } +} + +static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit, + unsigned int offset, void **__ptr) +{ + const struct ccs_limit *linfo; + + if (WARN_ON(limit >= CCS_L_LAST)) + return -EINVAL; + + linfo = &ccs_limits[ccs_limit_offsets[limit].info]; + + if (WARN_ON(!sensor->ccs_limits) || + WARN_ON(offset + ccs_reg_width(linfo->reg) > + ccs_limit_offsets[limit + 1].lim)) + return -EINVAL; + + *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset; + + return 0; +} + +void ccs_replace_limit(struct smiapp_sensor *sensor, + unsigned int limit, unsigned int offset, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + const struct ccs_limit *linfo; + void *ptr; + int ret; + + ret = ccs_limit_ptr(sensor, limit, offset, &ptr); + if (ret) + return; + + linfo = &ccs_limits[ccs_limit_offsets[limit].info]; + + dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n", + linfo->reg, linfo->name, offset, val, val); + + ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val); +} + +static u32 ccs_get_limit(struct smiapp_sensor *sensor, + unsigned int limit, unsigned int offset) +{ + void *ptr; + int ret; + + ret = ccs_limit_ptr(sensor, limit, offset, &ptr); + if (ret) + return 0; + + switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) { + case sizeof(u8): + return *(u8 *)ptr; + case sizeof(u16): + return *(u16 *)ptr; + case sizeof(u32): + return *(u32 *)ptr; + } + + WARN_ON(1); + + return 0; +} + +#define CCS_LIM(sensor, limit) \ + ccs_get_limit(sensor, CCS_L_##limit, 0) + +#define CCS_LIM_AT(sensor, limit, offset) \ + ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset)) + +static int ccs_read_all_limits(struct smiapp_sensor *sensor) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + void *ptr, *alloc, *end; + unsigned int i, l; + int ret; + + kfree(sensor->ccs_limits); + sensor->ccs_limits = NULL; + + alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL); + if (!alloc) + return -ENOMEM; + + end = alloc + ccs_limit_offsets[CCS_L_LAST].lim; + + for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) { + u32 reg = ccs_limits[i].reg; + unsigned int width = ccs_reg_width(reg); + unsigned int j; + + if (l == CCS_L_LAST) { + dev_err(&client->dev, + "internal error --- end of limit array\n"); + ret = -EINVAL; + goto out_err; + } + + for (j = 0; j < ccs_limits[i].size / width; + j++, reg += width, ptr += width) { + u32 val; + + ret = smiapp_read(sensor, reg, &val); + if (ret) + goto out_err; + + if (ptr + width > end) { + dev_err(&client->dev, + "internal error --- no room for regs\n"); + ret = -EINVAL; + goto out_err; + } + + ccs_assign_limit(ptr, width, val); + + dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n", + reg, ccs_limits[i].name, val, val); + } + + if (ccs_limits[i].flags & CCS_L_FL_SAME_REG) + continue; + + l++; + ptr = alloc + ccs_limit_offsets[l].lim; + } + + if (l != CCS_L_LAST) { + dev_err(&client->dev, + "internal error --- insufficient limits\n"); + ret = -EINVAL; + goto out_err; + } + + sensor->ccs_limits = alloc; + + return 0; + +out_err: + kfree(alloc); + + return ret; +} + static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -2970,10 +3129,14 @@ static int smiapp_probe(struct i2c_client *client) goto out_power_off; } + rval = ccs_read_all_limits(sensor); + if (rval) + goto out_power_off; + rval = smiapp_read_frame_fmt(sensor); if (rval) { rval = -ENODEV; - goto out_power_off; + goto out_free_ccs_limits; } /* @@ -2997,7 +3160,7 @@ static int smiapp_probe(struct i2c_client *client) rval = smiapp_call_quirk(sensor, limits); if (rval) { dev_err(&client->dev, "limits quirks failed\n"); - goto out_power_off; + goto out_free_ccs_limits; } if (SMIA_LIM(sensor, BINNING_CAPABILITY)) { @@ -3007,7 +3170,7 @@ static int smiapp_probe(struct i2c_client *client) SMIAPP_REG_U8_BINNING_SUBTYPES, &val); if (rval < 0) { rval = -ENODEV; - goto out_power_off; + goto out_free_ccs_limits; } sensor->nbinning_subtypes = min_t(u8, val, SMIAPP_BINNING_SUBTYPES); @@ -3017,7 +3180,7 @@ static int smiapp_probe(struct i2c_client *client) sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val); if (rval < 0) { rval = -ENODEV; - goto out_power_off; + goto out_free_ccs_limits; } sensor->binning_subtypes[i] = *(struct smiapp_binning_subtype *)&val; @@ -3033,7 +3196,7 @@ static int smiapp_probe(struct i2c_client *client) if (device_create_file(&client->dev, &dev_attr_ident) != 0) { dev_err(&client->dev, "sysfs ident entry creation failed\n"); rval = -ENOENT; - goto out_power_off; + goto out_free_ccs_limits; } if (sensor->minfo.smiapp_version && @@ -3150,6 +3313,9 @@ static int smiapp_probe(struct i2c_client *client) out_cleanup: smiapp_cleanup(sensor); +out_free_ccs_limits: + kfree(sensor->ccs_limits); + out_power_off: smiapp_power_off(&client->dev); mutex_destroy(&sensor->mutex); @@ -3176,6 +3342,7 @@ static int smiapp_remove(struct i2c_client *client) } smiapp_cleanup(sensor); mutex_destroy(&sensor->mutex); + kfree(sensor->ccs_limits); return 0; } diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h index b1d0e3d71630..08ca1b3d1b2f 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/smiapp.h @@ -228,6 +228,7 @@ struct smiapp_sensor { struct clk *ext_clk; struct gpio_desc *xshutdown; u32 limits[SMIAPP_LIMIT_LAST]; + void *ccs_limits; u8 nbinning_subtypes; struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES]; u32 mbus_frame_fmts; @@ -281,4 +282,7 @@ struct smiapp_sensor { #define to_smiapp_sensor(_sd) \ (to_smiapp_subdev(_sd)->sensor) +void ccs_replace_limit(struct smiapp_sensor *sensor, + unsigned int limit, unsigned int offset, u32 val); + #endif /* __SMIAPP_PRIV_H_ */ From patchwork Wed Sep 30 15:27:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69BD3139A for ; Wed, 30 Sep 2020 15:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D65C221EF for ; Wed, 30 Sep 2020 15:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730925AbgI3PaZ (ORCPT ); Wed, 30 Sep 2020 11:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730869AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAD23C0613D1 for ; Wed, 30 Sep 2020 08:29:02 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id C0B9C634C92 for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 008/100] smiapp: Switch to CCS limits Date: Wed, 30 Sep 2020 18:27:26 +0300 Message-Id: <20200930152858.8471-9-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the CCS limit definitions instead of the SMIA ones. This allows accessing CCS capabilities where needed as well as dropping the old SMIA limits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/Makefile | 3 +- drivers/media/i2c/smiapp/smiapp-core.c | 255 ++++++++++------------- drivers/media/i2c/smiapp/smiapp-limits.c | 118 ----------- drivers/media/i2c/smiapp/smiapp-limits.h | 114 ---------- drivers/media/i2c/smiapp/smiapp-quirk.c | 25 +-- drivers/media/i2c/smiapp/smiapp-quirk.h | 3 - drivers/media/i2c/smiapp/smiapp.h | 10 - 7 files changed, 113 insertions(+), 415 deletions(-) delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.c delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.h diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile index b4f0bcc037b8..a7bf53dd4a63 100644 --- a/drivers/media/i2c/smiapp/Makefile +++ b/drivers/media/i2c/smiapp/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only smiapp-objs += smiapp-core.o smiapp-regs.o \ - smiapp-quirk.o smiapp-limits.o \ - ccs-limits.o + smiapp-quirk.o ccs-limits.o obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o ccflags-y += -I $(srctree)/drivers/media/i2c diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index 42df98740445..a7cbd9029caa 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -64,45 +64,6 @@ static const struct smiapp_module_ident smiapp_module_idents[] = { * */ -static u32 smiapp_get_limit(struct smiapp_sensor *sensor, - unsigned int limit) -{ - if (WARN_ON(limit >= SMIAPP_LIMIT_LAST)) - return 1; - - return sensor->limits[limit]; -} - -#define SMIA_LIM(sensor, limit) \ - smiapp_get_limit(sensor, SMIAPP_LIMIT_##limit) - -static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor) -{ - struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - unsigned int i; - int rval; - - for (i = 0; i < SMIAPP_LIMIT_LAST; i++) { - u32 val; - - rval = smiapp_read( - sensor, smiapp_reg_limits[i].addr, &val); - if (rval) - return rval; - - sensor->limits[i] = val; - - dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n", - smiapp_reg_limits[i].addr, - smiapp_reg_limits[i].what, val, val); - } - - if (SMIA_LIM(sensor, SCALER_N_MIN) == 0) - smiapp_replace_limit(sensor, SMIAPP_LIMIT_SCALER_N_MIN, 16); - - return 0; -} - static void ccs_assign_limit(void *ptr, unsigned int width, u32 val) { switch (width) { @@ -253,6 +214,9 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor) sensor->ccs_limits = alloc; + if (CCS_LIM(sensor, SCALER_N_MIN) < 16) + ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16); + return 0; out_err: @@ -444,35 +408,35 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor, { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct smiapp_pll_limits lim = { - .min_pre_pll_clk_div = SMIA_LIM(sensor, MIN_PRE_PLL_CLK_DIV), - .max_pre_pll_clk_div = SMIA_LIM(sensor, MAX_PRE_PLL_CLK_DIV), - .min_pll_ip_freq_hz = SMIA_LIM(sensor, MIN_PLL_IP_FREQ_HZ), - .max_pll_ip_freq_hz = SMIA_LIM(sensor, MAX_PLL_IP_FREQ_HZ), - .min_pll_multiplier = SMIA_LIM(sensor, MIN_PLL_MULTIPLIER), - .max_pll_multiplier = SMIA_LIM(sensor, MAX_PLL_MULTIPLIER), - .min_pll_op_freq_hz = SMIA_LIM(sensor, MIN_PLL_OP_FREQ_HZ), - .max_pll_op_freq_hz = SMIA_LIM(sensor, MAX_PLL_OP_FREQ_HZ), - - .op.min_sys_clk_div = SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV), - .op.max_sys_clk_div = SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV), - .op.min_pix_clk_div = SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV), - .op.max_pix_clk_div = SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV), - .op.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_SYS_CLK_FREQ_HZ), - .op.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_SYS_CLK_FREQ_HZ), - .op.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_PIX_CLK_FREQ_HZ), - .op.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_PIX_CLK_FREQ_HZ), - - .vt.min_sys_clk_div = SMIA_LIM(sensor, MIN_VT_SYS_CLK_DIV), - .vt.max_sys_clk_div = SMIA_LIM(sensor, MAX_VT_SYS_CLK_DIV), - .vt.min_pix_clk_div = SMIA_LIM(sensor, MIN_VT_PIX_CLK_DIV), - .vt.max_pix_clk_div = SMIA_LIM(sensor, MAX_VT_PIX_CLK_DIV), - .vt.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_SYS_CLK_FREQ_HZ), - .vt.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_SYS_CLK_FREQ_HZ), - .vt.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_PIX_CLK_FREQ_HZ), - .vt.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_PIX_CLK_FREQ_HZ), - - .min_line_length_pck_bin = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN), - .min_line_length_pck = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK), + .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV), + .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV), + .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ), + .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ), + .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER), + .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER), + .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ), + .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ), + + .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV), + .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV), + .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV), + .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV), + .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ), + .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ), + .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ), + .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ), + + .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV), + .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV), + .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV), + .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV), + .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ), + .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ), + .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ), + .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ), + + .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN), + .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK), }; return smiapp_pll_calculate(&client->dev, &lim, pll); @@ -515,7 +479,7 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor) max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height + sensor->vblank->val - - SMIA_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN); + - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN); __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max); } @@ -770,10 +734,10 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor) sensor->analog_gain = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, - SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN), - SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MAX), - max(SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_STEP), 1U), - SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN)); + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), + max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); /* Exposure limits will be updated soon, use just something here. */ sensor->exposure = v4l2_ctrl_new_std( @@ -1032,21 +996,21 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor) int min, max; if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) { - min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN); - max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN); - min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN); - max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN); - min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN); + min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN); + max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN); + min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN); + max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN); + min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN); } else { - min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES); - max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES); - min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK); - max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK); - min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK); + min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES); + max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES); + min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK); + max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK); + min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK); } min = max_t(int, - SMIA_LIM(sensor, MIN_FRAME_BLANKING_LINES), + CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES), min_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height); max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height; @@ -1124,8 +1088,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, return -ENODATA; } - if (SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) & - SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL) { + if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) & + CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) { for (i = 1000; i > 0; i--) { if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY) break; @@ -1577,8 +1541,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) */ /* Digital crop */ - if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY) - == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { + if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) + == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { rval = smiapp_write( sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET, sensor->scaler->crop[SMIAPP_PAD_SINK].left); @@ -1605,8 +1569,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) } /* Scaling */ - if (SMIA_LIM(sensor, SCALING_CAPABILITY) - != SMIAPP_SCALING_CAPABILITY_NONE) { + if (CCS_LIM(sensor, SCALING_CAPABILITY) + != CCS_SCALING_CAPABILITY_NONE) { rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE, sensor->scaling_mode); if (rval < 0) @@ -1628,9 +1592,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) if (rval < 0) goto out; - if ((SMIA_LIM(sensor, FLASH_MODE_CAPABILITY) & - (SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE | - SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE)) && + if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) & + (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE | + SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) && sensor->hwcfg->strobe_setup != NULL && sensor->hwcfg->strobe_setup->trigger != 0) { rval = smiapp_setup_flash_strobe(sensor); @@ -1876,7 +1840,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev, if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { if (ssd == sensor->scaler) { sensor->scale_m = - SMIA_LIM(sensor, SCALER_N_MIN); + CCS_LIM(sensor, SCALER_N_MIN); sensor->scaling_mode = SMIAPP_SCALING_MODE_NONE; } else if (ssd == sensor->binner) { @@ -1988,12 +1952,12 @@ static int smiapp_set_format(struct v4l2_subdev *subdev, fmt->format.width = clamp(fmt->format.width, - SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE), - SMIA_LIM(sensor, MAX_X_OUTPUT_SIZE)); + CCS_LIM(sensor, MIN_X_OUTPUT_SIZE), + CCS_LIM(sensor, MAX_X_OUTPUT_SIZE)); fmt->format.height = clamp(fmt->format.height, - SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE), - SMIA_LIM(sensor, MAX_Y_OUTPUT_SIZE)); + CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE), + CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE)); smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which); @@ -2046,7 +2010,7 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w, val -= abs(w - ask_w); val -= abs(h - ask_h); - if (w < SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE)) + if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE)) val -= SCALING_GOODNESS_EXTREME; dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n", @@ -2112,7 +2076,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, struct i2c_client *client = v4l2_get_subdevdata(subdev); struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); u32 min, max, a, b, max_m; - u32 scale_m = SMIA_LIM(sensor, SCALER_N_MIN); + u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN); int mode = SMIAPP_SCALING_MODE_HORIZONTAL; u32 try[4]; u32 ntry = 0; @@ -2125,19 +2089,19 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, crops[SMIAPP_PAD_SINK]->height); a = crops[SMIAPP_PAD_SINK]->width - * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.width; + * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width; b = crops[SMIAPP_PAD_SINK]->height - * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.height; + * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height; max_m = crops[SMIAPP_PAD_SINK]->width - * SMIA_LIM(sensor, SCALER_N_MIN) - / SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE); + * CCS_LIM(sensor, SCALER_N_MIN) + / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE); - a = clamp(a, SMIA_LIM(sensor, SCALER_M_MIN), - SMIA_LIM(sensor, SCALER_M_MAX)); - b = clamp(b, SMIA_LIM(sensor, SCALER_M_MIN), - SMIA_LIM(sensor, SCALER_M_MAX)); - max_m = clamp(max_m, SMIA_LIM(sensor, SCALER_M_MIN), - SMIA_LIM(sensor, SCALER_M_MAX)); + a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN), + CCS_LIM(sensor, SCALER_M_MAX)); + b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN), + CCS_LIM(sensor, SCALER_M_MAX)); + max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN), + CCS_LIM(sensor, SCALER_M_MAX)); dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m); @@ -2163,8 +2127,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, int this = scaling_goodness( subdev, crops[SMIAPP_PAD_SINK]->width - / try[i] - * SMIA_LIM(sensor, SCALER_N_MIN), + / try[i] * CCS_LIM(sensor, SCALER_N_MIN), sel->r.width, crops[SMIAPP_PAD_SINK]->height, sel->r.height, @@ -2178,18 +2141,18 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, best = this; } - if (SMIA_LIM(sensor, SCALING_CAPABILITY) - == SMIAPP_SCALING_CAPABILITY_HORIZONTAL) + if (CCS_LIM(sensor, SCALING_CAPABILITY) + == CCS_SCALING_CAPABILITY_HORIZONTAL) continue; this = scaling_goodness( subdev, crops[SMIAPP_PAD_SINK]->width / try[i] - * SMIA_LIM(sensor, SCALER_N_MIN), + * CCS_LIM(sensor, SCALER_N_MIN), sel->r.width, crops[SMIAPP_PAD_SINK]->height / try[i] - * SMIA_LIM(sensor, SCALER_N_MIN), + * CCS_LIM(sensor, SCALER_N_MIN), sel->r.height, sel->flags); @@ -2203,12 +2166,12 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, sel->r.width = (crops[SMIAPP_PAD_SINK]->width / scale_m - * SMIA_LIM(sensor, SCALER_N_MIN)) & ~1; + * CCS_LIM(sensor, SCALER_N_MIN)) & ~1; if (mode == SMIAPP_SCALING_MODE_BOTH) sel->r.height = (crops[SMIAPP_PAD_SINK]->height / scale_m - * SMIA_LIM(sensor, SCALER_N_MIN)) + * CCS_LIM(sensor, SCALER_N_MIN)) & ~1; else sel->r.height = crops[SMIAPP_PAD_SINK]->height; @@ -2262,10 +2225,9 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev, if (ssd == sensor->src && sel->pad == SMIAPP_PAD_SRC) return 0; - if (ssd == sensor->scaler - && sel->pad == SMIAPP_PAD_SINK - && SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY) - == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) + if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK && + CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) + == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) return 0; return -EINVAL; case V4L2_SEL_TGT_NATIVE_SIZE: @@ -2279,9 +2241,8 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev, return -EINVAL; if (ssd == sensor->binner) return 0; - if (ssd == sensor->scaler - && SMIA_LIM(sensor, SCALING_CAPABILITY) - != SMIAPP_SCALING_CAPABILITY_NONE) + if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY) + != CCS_SCALING_CAPABILITY_NONE) return 0; fallthrough; default: @@ -2345,8 +2306,8 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd, { r->top = 0; r->left = 0; - r->width = SMIA_LIM(ssd->sensor, X_ADDR_MAX) + 1; - r->height = SMIA_LIM(ssd->sensor, Y_ADDR_MAX) + 1; + r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1; + r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1; } static int __smiapp_get_selection(struct v4l2_subdev *subdev, @@ -2431,10 +2392,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev, sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags); sel->r.width = max_t(unsigned int, - SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE), + CCS_LIM(sensor, MIN_X_OUTPUT_SIZE), sel->r.width); sel->r.height = max_t(unsigned int, - SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE), + CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE), sel->r.height); switch (sel->target) { @@ -3123,12 +3084,6 @@ static int smiapp_probe(struct i2c_client *client) goto out_power_off; } - rval = smiapp_read_all_smia_limits(sensor); - if (rval) { - rval = -ENODEV; - goto out_power_off; - } - rval = ccs_read_all_limits(sensor); if (rval) goto out_power_off; @@ -3163,7 +3118,7 @@ static int smiapp_probe(struct i2c_client *client) goto out_free_ccs_limits; } - if (SMIA_LIM(sensor, BINNING_CAPABILITY)) { + if (CCS_LIM(sensor, BINNING_CAPABILITY)) { u32 val; rval = smiapp_read(sensor, @@ -3200,8 +3155,8 @@ static int smiapp_probe(struct i2c_client *client) } if (sensor->minfo.smiapp_version && - SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) & - SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) { + CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) & + CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) { if (device_create_file(&client->dev, &dev_attr_nvm) != 0) { dev_err(&client->dev, "sysfs nvm entry failed\n"); rval = -EBUSY; @@ -3210,22 +3165,22 @@ static int smiapp_probe(struct i2c_client *client) } /* We consider this as profile 0 sensor if any of these are zero. */ - if (!SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV) || - !SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV) || - !SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV) || - !SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV)) { + if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) || + !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) || + !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) || + !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) { sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0; - } else if (SMIA_LIM(sensor, SCALING_CAPABILITY) - != SMIAPP_SCALING_CAPABILITY_NONE) { - if (SMIA_LIM(sensor, SCALING_CAPABILITY) - == SMIAPP_SCALING_CAPABILITY_HORIZONTAL) + } else if (CCS_LIM(sensor, SCALING_CAPABILITY) + != CCS_SCALING_CAPABILITY_NONE) { + if (CCS_LIM(sensor, SCALING_CAPABILITY) + == CCS_SCALING_CAPABILITY_HORIZONTAL) sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1; else sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2; sensor->scaler = &sensor->ssds[sensor->ssds_used]; sensor->ssds_used++; - } else if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY) - == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { + } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) + == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { sensor->scaler = &sensor->ssds[sensor->ssds_used]; sensor->ssds_used++; } @@ -3234,13 +3189,13 @@ static int smiapp_probe(struct i2c_client *client) sensor->pixel_array = &sensor->ssds[sensor->ssds_used]; sensor->ssds_used++; - sensor->scale_m = SMIA_LIM(sensor, SCALER_N_MIN); + sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN); /* prepare PLL configuration input values */ sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2; sensor->pll.csi2.lanes = sensor->hwcfg->lanes; sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk; - sensor->pll.scale_n = SMIA_LIM(sensor, SCALER_N_MIN); + sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); /* Profile 0 sensors have no separate OP clock branch. */ if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0) sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; diff --git a/drivers/media/i2c/smiapp/smiapp-limits.c b/drivers/media/i2c/smiapp/smiapp-limits.c deleted file mode 100644 index de5ee5296713..000000000000 --- a/drivers/media/i2c/smiapp/smiapp-limits.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * drivers/media/i2c/smiapp/smiapp-limits.c - * - * Generic driver for SMIA/SMIA++ compliant camera modules - * - * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus - */ - -#include "smiapp.h" - -struct smiapp_reg_limits smiapp_reg_limits[] = { - { SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY, "analogue_gain_capability" }, /* 0 */ - { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN, "analogue_gain_code_min" }, - { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX, "analogue_gain_code_max" }, - { SMIAPP_REG_U8_THS_ZERO_MIN, "ths_zero_min" }, - { SMIAPP_REG_U8_TCLK_TRAIL_MIN, "tclk_trail_min" }, - { SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY, "integration_time_capability" }, /* 5 */ - { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN, "coarse_integration_time_min" }, - { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN, "coarse_integration_time_max_margin" }, - { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN, "fine_integration_time_min" }, - { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN, "fine_integration_time_max_margin" }, - { SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY, "digital_gain_capability" }, /* 10 */ - { SMIAPP_REG_U16_DIGITAL_GAIN_MIN, "digital_gain_min" }, - { SMIAPP_REG_U16_DIGITAL_GAIN_MAX, "digital_gain_max" }, - { SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ, "min_ext_clk_freq_hz" }, - { SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ, "max_ext_clk_freq_hz" }, - { SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV, "min_pre_pll_clk_div" }, /* 15 */ - { SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV, "max_pre_pll_clk_div" }, - { SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ, "min_pll_ip_freq_hz" }, - { SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ, "max_pll_ip_freq_hz" }, - { SMIAPP_REG_U16_MIN_PLL_MULTIPLIER, "min_pll_multiplier" }, - { SMIAPP_REG_U16_MAX_PLL_MULTIPLIER, "max_pll_multiplier" }, /* 20 */ - { SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ, "min_pll_op_freq_hz" }, - { SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ, "max_pll_op_freq_hz" }, - { SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV, "min_vt_sys_clk_div" }, - { SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV, "max_vt_sys_clk_div" }, - { SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ, "min_vt_sys_clk_freq_hz" }, /* 25 */ - { SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ, "max_vt_sys_clk_freq_hz" }, - { SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ, "min_vt_pix_clk_freq_hz" }, - { SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ, "max_vt_pix_clk_freq_hz" }, - { SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV, "min_vt_pix_clk_div" }, - { SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV, "max_vt_pix_clk_div" }, /* 30 */ - { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES, "min_frame_length_lines" }, - { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES, "max_frame_length_lines" }, - { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK, "min_line_length_pck" }, - { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK, "max_line_length_pck" }, - { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK, "min_line_blanking_pck" }, /* 35 */ - { SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES, "min_frame_blanking_lines" }, - { SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE, "min_line_length_pck_step_size" }, - { SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV, "min_op_sys_clk_div" }, - { SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV, "max_op_sys_clk_div" }, - { SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ, "min_op_sys_clk_freq_hz" }, /* 40 */ - { SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ, "max_op_sys_clk_freq_hz" }, - { SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV, "min_op_pix_clk_div" }, - { SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV, "max_op_pix_clk_div" }, - { SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ, "min_op_pix_clk_freq_hz" }, - { SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ, "max_op_pix_clk_freq_hz" }, /* 45 */ - { SMIAPP_REG_U16_X_ADDR_MIN, "x_addr_min" }, - { SMIAPP_REG_U16_Y_ADDR_MIN, "y_addr_min" }, - { SMIAPP_REG_U16_X_ADDR_MAX, "x_addr_max" }, - { SMIAPP_REG_U16_Y_ADDR_MAX, "y_addr_max" }, - { SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE, "min_x_output_size" }, /* 50 */ - { SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE, "min_y_output_size" }, - { SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE, "max_x_output_size" }, - { SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE, "max_y_output_size" }, - { SMIAPP_REG_U16_MIN_EVEN_INC, "min_even_inc" }, - { SMIAPP_REG_U16_MAX_EVEN_INC, "max_even_inc" }, /* 55 */ - { SMIAPP_REG_U16_MIN_ODD_INC, "min_odd_inc" }, - { SMIAPP_REG_U16_MAX_ODD_INC, "max_odd_inc" }, - { SMIAPP_REG_U16_SCALING_CAPABILITY, "scaling_capability" }, - { SMIAPP_REG_U16_SCALER_M_MIN, "scaler_m_min" }, - { SMIAPP_REG_U16_SCALER_M_MAX, "scaler_m_max" }, /* 60 */ - { SMIAPP_REG_U16_SCALER_N_MIN, "scaler_n_min" }, - { SMIAPP_REG_U16_SCALER_N_MAX, "scaler_n_max" }, - { SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY, "spatial_sampling_capability" }, - { SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY, "digital_crop_capability" }, - { SMIAPP_REG_U16_COMPRESSION_CAPABILITY, "compression_capability" }, /* 65 */ - { SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY, "fifo_support_capability" }, - { SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY, "dphy_ctrl_capability" }, - { SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY, "csi_lane_mode_capability" }, - { SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY, "csi_signalling_mode_capability" }, - { SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY, "fast_standby_capability" }, /* 70 */ - { SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY, "cci_address_control_capability" }, - { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS, "max_per_lane_bitrate_1_lane_mode_mbps" }, - { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS, "max_per_lane_bitrate_2_lane_mode_mbps" }, - { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS, "max_per_lane_bitrate_3_lane_mode_mbps" }, - { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS, "max_per_lane_bitrate_4_lane_mode_mbps" }, /* 75 */ - { SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY, "temp_sensor_capability" }, - { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN, "min_frame_length_lines_bin" }, - { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN, "max_frame_length_lines_bin" }, - { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN, "min_line_length_pck_bin" }, - { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN, "max_line_length_pck_bin" }, /* 80 */ - { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN, "min_line_blanking_pck_bin" }, - { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN, "fine_integration_time_min_bin" }, - { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, "fine_integration_time_max_margin_bin" }, - { SMIAPP_REG_U8_BINNING_CAPABILITY, "binning_capability" }, - { SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY, "binning_weighting_capability" }, /* 85 */ - { SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY, "data_transfer_if_capability" }, - { SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY, "shading_correction_capability" }, - { SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY, "green_imbalance_capability" }, - { SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY, "black_level_capability" }, - { SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY, "module_specific_correction_capability" }, /* 90 */ - { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY, "defect_correction_capability" }, - { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2, "defect_correction_capability_2" }, - { SMIAPP_REG_U8_EDOF_CAPABILITY, "edof_capability" }, - { SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY, "colour_feedback_capability" }, - { SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY, "estimation_mode_capability" }, /* 95 */ - { SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY, "estimation_zone_capability" }, - { SMIAPP_REG_U16_CAPABILITY_TRDY_MIN, "capability_trdy_min" }, - { SMIAPP_REG_U8_FLASH_MODE_CAPABILITY, "flash_mode_capability" }, - { SMIAPP_REG_U8_ACTUATOR_CAPABILITY, "actuator_capability" }, - { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1, "bracketing_lut_capability_1" }, /* 100 */ - { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2, "bracketing_lut_capability_2" }, - { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP, "analogue_gain_code_step" }, - { 0, NULL }, -}; diff --git a/drivers/media/i2c/smiapp/smiapp-limits.h b/drivers/media/i2c/smiapp/smiapp-limits.h deleted file mode 100644 index dbac0b4975f9..000000000000 --- a/drivers/media/i2c/smiapp/smiapp-limits.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * drivers/media/i2c/smiapp/smiapp-limits.h - * - * Generic driver for SMIA/SMIA++ compliant camera modules - * - * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus - */ - -#define SMIAPP_LIMIT_ANALOGUE_GAIN_CAPABILITY 0 -#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN 1 -#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX 2 -#define SMIAPP_LIMIT_THS_ZERO_MIN 3 -#define SMIAPP_LIMIT_TCLK_TRAIL_MIN 4 -#define SMIAPP_LIMIT_INTEGRATION_TIME_CAPABILITY 5 -#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MIN 6 -#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MAX_MARGIN 7 -#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN 8 -#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN 9 -#define SMIAPP_LIMIT_DIGITAL_GAIN_CAPABILITY 10 -#define SMIAPP_LIMIT_DIGITAL_GAIN_MIN 11 -#define SMIAPP_LIMIT_DIGITAL_GAIN_MAX 12 -#define SMIAPP_LIMIT_MIN_EXT_CLK_FREQ_HZ 13 -#define SMIAPP_LIMIT_MAX_EXT_CLK_FREQ_HZ 14 -#define SMIAPP_LIMIT_MIN_PRE_PLL_CLK_DIV 15 -#define SMIAPP_LIMIT_MAX_PRE_PLL_CLK_DIV 16 -#define SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ 17 -#define SMIAPP_LIMIT_MAX_PLL_IP_FREQ_HZ 18 -#define SMIAPP_LIMIT_MIN_PLL_MULTIPLIER 19 -#define SMIAPP_LIMIT_MAX_PLL_MULTIPLIER 20 -#define SMIAPP_LIMIT_MIN_PLL_OP_FREQ_HZ 21 -#define SMIAPP_LIMIT_MAX_PLL_OP_FREQ_HZ 22 -#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_DIV 23 -#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_DIV 24 -#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_FREQ_HZ 25 -#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_FREQ_HZ 26 -#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_FREQ_HZ 27 -#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_FREQ_HZ 28 -#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_DIV 29 -#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_DIV 30 -#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES 31 -#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES 32 -#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK 33 -#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK 34 -#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK 35 -#define SMIAPP_LIMIT_MIN_FRAME_BLANKING_LINES 36 -#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_STEP_SIZE 37 -#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_DIV 38 -#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_DIV 39 -#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_FREQ_HZ 40 -#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_FREQ_HZ 41 -#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_DIV 42 -#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_DIV 43 -#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_FREQ_HZ 44 -#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_FREQ_HZ 45 -#define SMIAPP_LIMIT_X_ADDR_MIN 46 -#define SMIAPP_LIMIT_Y_ADDR_MIN 47 -#define SMIAPP_LIMIT_X_ADDR_MAX 48 -#define SMIAPP_LIMIT_Y_ADDR_MAX 49 -#define SMIAPP_LIMIT_MIN_X_OUTPUT_SIZE 50 -#define SMIAPP_LIMIT_MIN_Y_OUTPUT_SIZE 51 -#define SMIAPP_LIMIT_MAX_X_OUTPUT_SIZE 52 -#define SMIAPP_LIMIT_MAX_Y_OUTPUT_SIZE 53 -#define SMIAPP_LIMIT_MIN_EVEN_INC 54 -#define SMIAPP_LIMIT_MAX_EVEN_INC 55 -#define SMIAPP_LIMIT_MIN_ODD_INC 56 -#define SMIAPP_LIMIT_MAX_ODD_INC 57 -#define SMIAPP_LIMIT_SCALING_CAPABILITY 58 -#define SMIAPP_LIMIT_SCALER_M_MIN 59 -#define SMIAPP_LIMIT_SCALER_M_MAX 60 -#define SMIAPP_LIMIT_SCALER_N_MIN 61 -#define SMIAPP_LIMIT_SCALER_N_MAX 62 -#define SMIAPP_LIMIT_SPATIAL_SAMPLING_CAPABILITY 63 -#define SMIAPP_LIMIT_DIGITAL_CROP_CAPABILITY 64 -#define SMIAPP_LIMIT_COMPRESSION_CAPABILITY 65 -#define SMIAPP_LIMIT_FIFO_SUPPORT_CAPABILITY 66 -#define SMIAPP_LIMIT_DPHY_CTRL_CAPABILITY 67 -#define SMIAPP_LIMIT_CSI_LANE_MODE_CAPABILITY 68 -#define SMIAPP_LIMIT_CSI_SIGNALLING_MODE_CAPABILITY 69 -#define SMIAPP_LIMIT_FAST_STANDBY_CAPABILITY 70 -#define SMIAPP_LIMIT_CCI_ADDRESS_CONTROL_CAPABILITY 71 -#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS 72 -#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS 73 -#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS 74 -#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS 75 -#define SMIAPP_LIMIT_TEMP_SENSOR_CAPABILITY 76 -#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES_BIN 77 -#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES_BIN 78 -#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_BIN 79 -#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK_BIN 80 -#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN 81 -#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN_BIN 82 -#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 83 -#define SMIAPP_LIMIT_BINNING_CAPABILITY 84 -#define SMIAPP_LIMIT_BINNING_WEIGHTING_CAPABILITY 85 -#define SMIAPP_LIMIT_DATA_TRANSFER_IF_CAPABILITY 86 -#define SMIAPP_LIMIT_SHADING_CORRECTION_CAPABILITY 87 -#define SMIAPP_LIMIT_GREEN_IMBALANCE_CAPABILITY 88 -#define SMIAPP_LIMIT_BLACK_LEVEL_CAPABILITY 89 -#define SMIAPP_LIMIT_MODULE_SPECIFIC_CORRECTION_CAPABILITY 90 -#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY 91 -#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY_2 92 -#define SMIAPP_LIMIT_EDOF_CAPABILITY 93 -#define SMIAPP_LIMIT_COLOUR_FEEDBACK_CAPABILITY 94 -#define SMIAPP_LIMIT_ESTIMATION_MODE_CAPABILITY 95 -#define SMIAPP_LIMIT_ESTIMATION_ZONE_CAPABILITY 96 -#define SMIAPP_LIMIT_CAPABILITY_TRDY_MIN 97 -#define SMIAPP_LIMIT_FLASH_MODE_CAPABILITY 98 -#define SMIAPP_LIMIT_ACTUATOR_CAPABILITY 99 -#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_1 100 -#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_2 101 -#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_STEP 102 -#define SMIAPP_LIMIT_LAST 103 diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c index 308ca0b03f5a..24630c7650d2 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.c +++ b/drivers/media/i2c/smiapp/smiapp-quirk.c @@ -10,6 +10,8 @@ #include +#include "ccs-limits.h" + #include "smiapp.h" static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val) @@ -36,17 +38,6 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor, return 0; } -void smiapp_replace_limit(struct smiapp_sensor *sensor, - u32 limit, u32 val) -{ - struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - - dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n", - smiapp_reg_limits[limit].addr, - smiapp_reg_limits[limit].what, val, val); - sensor->limits[limit] = val; -} - static int jt8ew9_limits(struct smiapp_sensor *sensor) { if (sensor->minfo.revision_number_major < 0x03) @@ -54,9 +45,8 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor) /* Below 24 gain doesn't have effect at all, */ /* but ~59 is needed for full dynamic range */ - smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59); - smiapp_replace_limit( - sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000); + ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59); + ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000); return 0; } @@ -126,9 +116,8 @@ const struct smiapp_quirk smiapp_imx125es_quirk = { static int jt8ev1_limits(struct smiapp_sensor *sensor) { - smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271); - smiapp_replace_limit(sensor, - SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184); + ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271); + ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184); return 0; } @@ -221,7 +210,7 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = { static int tcm8500md_limits(struct smiapp_sensor *sensor) { - smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000); + ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000); return 0; } diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/smiapp-quirk.h index 17505be60c1d..8a479f17cd19 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.h +++ b/drivers/media/i2c/smiapp/smiapp-quirk.h @@ -55,9 +55,6 @@ struct smiapp_reg_8 { u8 val; }; -void smiapp_replace_limit(struct smiapp_sensor *sensor, - u32 limit, u32 val); - #define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \ { \ .reg = (u16)_reg, \ diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h index 08ca1b3d1b2f..1a67cf485dcc 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/smiapp.h @@ -84,8 +84,6 @@ struct smiapp_hwconfig { struct smiapp_flash_strobe_parms *strobe_setup; }; -#include "smiapp-limits.h" - struct smiapp_quirk; #define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0) @@ -167,13 +165,6 @@ struct smiapp_module_info { .flags = 0, \ .name = _name, } -struct smiapp_reg_limits { - u32 addr; - char *what; -}; - -extern struct smiapp_reg_limits smiapp_reg_limits[]; - struct smiapp_csi_data_format { u32 code; u8 width; @@ -227,7 +218,6 @@ struct smiapp_sensor { struct regulator *vana; struct clk *ext_clk; struct gpio_desc *xshutdown; - u32 limits[SMIAPP_LIMIT_LAST]; void *ccs_limits; u8 nbinning_subtypes; struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES]; From patchwork Wed Sep 30 15:27:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F118D618 for ; Wed, 30 Sep 2020 15:30:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D972522207 for ; Wed, 30 Sep 2020 15:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731198AbgI3Paa (ORCPT ); Wed, 30 Sep 2020 11:30:30 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730722AbgI3P3C (ORCPT ); Wed, 30 Sep 2020 11:29:02 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id E23F9634C93 for ; Wed, 30 Sep 2020 18:28:46 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 009/100] smiapp: Obtain frame descriptor from CCS limits Date: Wed, 30 Sep 2020 18:27:27 +0300 Message-Id: <20200930152858.8471-10-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Obtain the frame descriptor from the CCS limits, instead of reading them directly from the frame descriptor registers. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 70 +++++++++++--------------- 1 file changed, 30 insertions(+), 40 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index a7cbd9029caa..af94df9dbc7d 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -228,34 +228,29 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor) static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - u32 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc; + u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc; unsigned int i; int pixel_count = 0; int line_count = 0; - int rval; - - rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE, - &fmt_model_type); - if (rval) - return rval; - rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE, - &fmt_model_subtype); - if (rval) - return rval; + fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE); + fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE); ncol_desc = (fmt_model_subtype - & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK) - >> SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT; + & CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK) + >> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT; nrow_desc = fmt_model_subtype - & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK; + & CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK; dev_dbg(&client->dev, "format_model_type %s\n", - fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE + fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE ? "2 byte" : - fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE + fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE ? "4 byte" : "is simply bad"); + dev_dbg(&client->dev, "%u column and %u row descriptors\n", + ncol_desc, nrow_desc); + for (i = 0; i < ncol_desc + nrow_desc; i++) { u32 desc; u32 pixelcode; @@ -264,29 +259,24 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) char *what; u32 reg; - if (fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE) { - reg = SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(i); - rval = smiapp_read(sensor, reg, &desc); - if (rval) - return rval; + if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) { + desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i); pixelcode = (desc - & SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK) - >> SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT; - pixels = desc & SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK; + & CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK) + >> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT; + pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK; } else if (fmt_model_type - == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE) { - reg = SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(i); - rval = smiapp_read(sensor, reg, &desc); - if (rval) - return rval; + == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) { + desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i); pixelcode = (desc - & SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK) - >> SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT; - pixels = desc & SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK; + & CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK) + >> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT; + pixels = desc & + CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK; } else { dev_dbg(&client->dev, "invalid frame format model type %d\n", @@ -300,19 +290,19 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) which = "rows"; switch (pixelcode) { - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED: what = "embedded"; break; - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL: what = "dummy"; break; - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL: what = "black"; break; - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL: what = "dark"; break; - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL: what = "visible"; break; default: @@ -326,7 +316,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) if (i < ncol_desc) { if (pixelcode == - SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE) + CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL) sensor->visible_pixel_start = pixel_count; pixel_count += pixels; continue; @@ -334,13 +324,13 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) /* Handle row descriptors */ switch (pixelcode) { - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED: if (sensor->embedded_end) break; sensor->embedded_start = line_count; sensor->embedded_end = line_count + pixels; break; - case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE: + case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL: sensor->image_start = line_count; break; } From patchwork Wed Sep 30 15:27:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BE7D618 for ; Wed, 30 Sep 2020 15:30:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EBF35221EF for ; Wed, 30 Sep 2020 15:30:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731181AbgI3Pa0 (ORCPT ); Wed, 30 Sep 2020 11:30:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730851AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FC84C0613D2 for ; Wed, 30 Sep 2020 08:29:03 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 05014634C94 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 010/100] smiapp: Use CCS limits in reading data format descriptors Date: Wed, 30 Sep 2020 18:27:28 +0300 Message-Id: <20200930152858.8471-11-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CCS limits have the information so use it instead. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index af94df9dbc7d..0f703860af0e 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -842,10 +842,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) unsigned int i, pixel_order; int rval; - rval = smiapp_read( - sensor, SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE, &type); - if (rval) - return rval; + type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE); dev_dbg(&client->dev, "data_format_model_type %d\n", type); @@ -863,11 +860,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) pixel_order_str[pixel_order]); switch (type) { - case SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL: + case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL: n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N; break; - case SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED: - n = SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N; + case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED: + n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1; break; default: return -EINVAL; @@ -879,11 +876,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) for (i = 0; i < n; i++) { unsigned int fmt, j; - rval = smiapp_read( - sensor, - SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(i), &fmt); - if (rval) - return rval; + fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i); dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n", i, fmt >> 8, (u8)fmt); @@ -895,7 +888,10 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG) continue; - if (f->width != fmt >> 8 || f->compressed != (u8)fmt) + if (f->width != fmt >> + CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT || + f->compressed != + (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK)) continue; dev_dbg(&client->dev, "jolly good! %d\n", j); From patchwork Wed Sep 30 15:27:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 931CB92C for ; Wed, 30 Sep 2020 15:30:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E0DA20759 for ; Wed, 30 Sep 2020 15:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730851AbgI3Paf (ORCPT ); Wed, 30 Sep 2020 11:30:35 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730785AbgI3P3C (ORCPT ); Wed, 30 Sep 2020 11:29:02 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 17A57634C95 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 011/100] smiapp: Use CCS limits in reading binning capabilities Date: Wed, 30 Sep 2020 18:27:29 +0300 Message-Id: <20200930152858.8471-12-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use CCS limits for obtaining binning capabilities and subtypes. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 27 +++++++++----------------- 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index 0f703860af0e..a54ceef5c5ea 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -3105,26 +3105,17 @@ static int smiapp_probe(struct i2c_client *client) } if (CCS_LIM(sensor, BINNING_CAPABILITY)) { - u32 val; - - rval = smiapp_read(sensor, - SMIAPP_REG_U8_BINNING_SUBTYPES, &val); - if (rval < 0) { - rval = -ENODEV; - goto out_free_ccs_limits; - } - sensor->nbinning_subtypes = min_t(u8, val, - SMIAPP_BINNING_SUBTYPES); + sensor->nbinning_subtypes = + min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES), + CCS_LIM_BINNING_SUB_TYPE_MAX_N); for (i = 0; i < sensor->nbinning_subtypes; i++) { - rval = smiapp_read( - sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val); - if (rval < 0) { - rval = -ENODEV; - goto out_free_ccs_limits; - } - sensor->binning_subtypes[i] = - *(struct smiapp_binning_subtype *)&val; + sensor->binning_subtypes[i].horizontal = + CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >> + CCS_BINNING_SUB_TYPE_COLUMN_SHIFT; + sensor->binning_subtypes[i].vertical = + CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) & + CCS_BINNING_SUB_TYPE_ROW_MASK; dev_dbg(&client->dev, "binning %xx%x\n", sensor->binning_subtypes[i].horizontal, From patchwork Wed Sep 30 15:27:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809651 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9B2692C for ; Wed, 30 Sep 2020 15:30:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B1EA22207 for ; Wed, 30 Sep 2020 15:30:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731180AbgI3Pa0 (ORCPT ); Wed, 30 Sep 2020 11:30:26 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730653AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 2CC43634C96 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 012/100] smiapp: Use CCS registers Date: Wed, 30 Sep 2020 18:27:30 +0300 Message-Id: <20200930152858.8471-13-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Switch to CCS standard registers where they exist. The still relevant SMIA registers are left as-is and the redundant ones are removed. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 272 +++++++++++-------------- drivers/media/i2c/smiapp/smiapp.h | 4 +- 2 files changed, 118 insertions(+), 158 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index a54ceef5c5ea..b9faf38d4bba 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -28,7 +28,6 @@ #include #include "ccs-limits.h" -#include "ccs-regs.h" #include "smiapp.h" #define SMIAPP_ALIGN_DIM(dim, flags) \ @@ -357,40 +356,34 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor) struct smiapp_pll *pll = &sensor->pll; int rval; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div); + rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div); if (rval < 0) return rval; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div); + rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div); if (rval < 0) return rval; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); + rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); if (rval < 0) return rval; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier); + rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier); if (rval < 0) return rval; /* Lane op clock ratio does not apply here. */ - rval = smiapp_write( - sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS, - DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); + rval = ccs_write(sensor, REQUESTED_LINK_RATE, + DIV_ROUND_UP(pll->op.sys_clk_freq_hz, + 1000000 / 256 / 256)); if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0) return rval; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div); + rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div); if (rval < 0) return rval; - return smiapp_write( - sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div); + return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div); } static int smiapp_pll_try(struct smiapp_sensor *sensor, @@ -522,10 +515,10 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor) if (sensor->hflip) { if (sensor->hflip->val) - flip |= SMIAPP_IMAGE_ORIENTATION_HFLIP; + flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR; if (sensor->vflip->val) - flip |= SMIAPP_IMAGE_ORIENTATION_VFLIP; + flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; } flip ^= sensor->hvflip_inv_mask; @@ -585,10 +578,10 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) return -EBUSY; if (sensor->hflip->val) - orient |= SMIAPP_IMAGE_ORIENTATION_HFLIP; + orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR; if (sensor->vflip->val) - orient |= SMIAPP_IMAGE_ORIENTATION_VFLIP; + orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; orient ^= sensor->hvflip_inv_mask; @@ -633,60 +626,50 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_ANALOGUE_GAIN: - rval = smiapp_write( - sensor, - SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val); + rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val); break; case V4L2_CID_EXPOSURE: - rval = smiapp_write( - sensor, - SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val); + rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val); break; case V4L2_CID_HFLIP: case V4L2_CID_VFLIP: - rval = smiapp_write(sensor, SMIAPP_REG_U8_IMAGE_ORIENTATION, - orient); + rval = ccs_write(sensor, IMAGE_ORIENTATION, orient); break; case V4L2_CID_VBLANK: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_FRAME_LENGTH_LINES, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - + ctrl->val); + rval = ccs_write(sensor, FRAME_LENGTH_LINES, + sensor->pixel_array->crop[ + SMIAPP_PA_PAD_SRC].height + + ctrl->val); break; case V4L2_CID_HBLANK: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_LINE_LENGTH_PCK, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - + ctrl->val); + rval = ccs_write(sensor, LINE_LENGTH_PCK, + sensor->pixel_array->crop[ + SMIAPP_PA_PAD_SRC].width + + ctrl->val); break; case V4L2_CID_TEST_PATTERN: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val); + rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val); break; case V4L2_CID_TEST_PATTERN_RED: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val); + rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val); break; case V4L2_CID_TEST_PATTERN_GREENR: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val); + rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val); break; case V4L2_CID_TEST_PATTERN_BLUE: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val); + rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val); break; case V4L2_CID_TEST_PATTERN_GREENB: - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val); + rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val); break; case V4L2_CID_PIXEL_RATE: @@ -846,8 +829,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) dev_dbg(&client->dev, "data_format_model_type %d\n", type); - rval = smiapp_read(sensor, SMIAPP_REG_U8_PIXEL_ORDER, - &pixel_order); + rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order); if (rval) return rval; @@ -1054,22 +1036,20 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, *status = 0; - rval = smiapp_write(sensor, - SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT, p); + rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p); if (rval) return rval; - rval = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, - SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN); + rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, + CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE); if (rval) return rval; - rval = smiapp_read(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS, - &s); + rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s); if (rval) return rval; - if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) { + if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) { *status = s; return -ENODATA; } @@ -1077,14 +1057,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) & CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) { for (i = 1000; i > 0; i--) { - if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY) + if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY) break; - rval = smiapp_read( - sensor, - SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS, - &s); - + rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s); if (rval) return rval; } @@ -1093,12 +1069,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, return -ETIMEDOUT; } - for (i = 0; i < SMIAPP_NVM_PAGE_SIZE; i++) { + for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) { u32 v; - rval = smiapp_read(sensor, - SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 + i, - &v); + rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v); if (rval) return rval; @@ -1115,20 +1089,21 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm, u32 p; int rval = 0, rval2; - for (p = 0; p < nvm_size / SMIAPP_NVM_PAGE_SIZE && !rval; p++) { + for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1) + && !rval; p++) { rval = smiapp_read_nvm_page(sensor, p, nvm, &status); - nvm += SMIAPP_NVM_PAGE_SIZE; + nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1; } if (rval == -ENODATA && - status & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) + status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) rval = 0; - rval2 = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, 0); + rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0); if (rval < 0) return rval; else - return rval2 ?: p * SMIAPP_NVM_PAGE_SIZE; + return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1); } /* @@ -1144,16 +1119,15 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor) client->addr = sensor->hwcfg->i2c_addr_dfl; - rval = smiapp_write(sensor, - SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, - sensor->hwcfg->i2c_addr_alt << 1); + rval = ccs_write(sensor, CCI_ADDRESS_CTRL, + sensor->hwcfg->i2c_addr_alt << 1); if (rval) return rval; client->addr = sensor->hwcfg->i2c_addr_alt; /* verify addr change went ok */ - rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val); + rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val); if (rval) return rval; @@ -1259,34 +1233,30 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor) strobe_width_high_rs = (tmp + strobe_adjustment - 1) / strobe_adjustment; - rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_MODE_RS, - strobe_setup->mode); + rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT, - strobe_adjustment); + rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment); if (rval < 0) goto out; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL, - strobe_width_high_rs); + rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL, + strobe_width_high_rs); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL, - strobe_setup->strobe_delay); + rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL, + strobe_setup->strobe_delay); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U16_FLASH_STROBE_START_POINT, - strobe_setup->stobe_start_point); + rval = ccs_write(sensor, FLASH_STROBE_START_POINT, + strobe_setup->stobe_start_point); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_TRIGGER_RS, - strobe_setup->trigger); + rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger); out: sensor->hwcfg->strobe_setup->trigger = 0; @@ -1349,8 +1319,7 @@ static int smiapp_power_on(struct device *dev) } } - rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET, - SMIAPP_SOFTWARE_RESET); + rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); if (rval < 0) { dev_err(dev, "software reset failed\n"); goto out_cci_addr_fail; @@ -1364,45 +1333,42 @@ static int smiapp_power_on(struct device *dev) } } - rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE, - SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR); + rval = ccs_write(sensor, COMPRESSION_MODE, + CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE); if (rval) { dev_err(dev, "compression mode set failed\n"); goto out_cci_addr_fail; } - rval = smiapp_write( - sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ, - sensor->hwcfg->ext_clk / (1000000 / (1 << 8))); + rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ, + sensor->hwcfg->ext_clk / (1000000 / (1 << 8))); if (rval) { dev_err(dev, "extclk frequency set failed\n"); goto out_cci_addr_fail; } - rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE, - sensor->hwcfg->lanes - 1); + rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1); if (rval) { dev_err(dev, "csi lane mode set failed\n"); goto out_cci_addr_fail; } - rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL, - SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE); + rval = ccs_write(sensor, FAST_STANDBY_CTRL, + CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION); if (rval) { dev_err(dev, "fast standby set failed\n"); goto out_cci_addr_fail; } - rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE, - sensor->hwcfg->csi_signalling_mode); + rval = ccs_write(sensor, CSI_SIGNALING_MODE, + sensor->hwcfg->csi_signalling_mode); if (rval) { dev_err(dev, "csi signalling mode set failed\n"); goto out_cci_addr_fail; } /* DPHY control done by sensor based on requested link rate */ - rval = smiapp_write(sensor, SMIAPP_REG_U8_DPHY_CTRL, - SMIAPP_DPHY_CTRL_UI); + rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI); if (rval < 0) goto out_cci_addr_fail; @@ -1439,9 +1405,7 @@ static int smiapp_power_off(struct device *dev) * will fail. So do a soft reset explicitly here. */ if (sensor->hwcfg->i2c_addr_alt) - smiapp_write(sensor, - SMIAPP_REG_U8_SOFTWARE_RESET, - SMIAPP_SOFTWARE_RESET); + ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); gpiod_set_value(sensor->xshutdown, 0); clk_disable_unprepare(sensor->ext_clk); @@ -1464,9 +1428,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) mutex_lock(&sensor->mutex); - rval = smiapp_write(sensor, SMIAPP_REG_U16_CSI_DATA_FORMAT, - (sensor->csi_format->width << 8) | - sensor->csi_format->compressed); + rval = ccs_write(sensor, CSI_DATA_FORMAT, + (sensor->csi_format->width << 8) | + sensor->csi_format->compressed); if (rval) goto out; @@ -1479,14 +1443,13 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) (sensor->binning_horizontal << 4) | sensor->binning_vertical; - rval = smiapp_write( - sensor, SMIAPP_REG_U8_BINNING_TYPE, binning_type); + rval = ccs_write(sensor, BINNING_TYPE, binning_type); if (rval < 0) goto out; binning_mode = 1; } - rval = smiapp_write(sensor, SMIAPP_REG_U8_BINNING_MODE, binning_mode); + rval = ccs_write(sensor, BINNING_MODE, binning_mode); if (rval < 0) goto out; @@ -1496,26 +1459,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) goto out; /* Analog crop start coordinates */ - rval = smiapp_write(sensor, SMIAPP_REG_U16_X_ADDR_START, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left); + rval = ccs_write(sensor, X_ADDR_START, + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_ADDR_START, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top); + rval = ccs_write(sensor, Y_ADDR_START, + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top); if (rval < 0) goto out; /* Analog crop end coordinates */ - rval = smiapp_write( - sensor, SMIAPP_REG_U16_X_ADDR_END, + rval = ccs_write( + sensor, X_ADDR_END, sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1); if (rval < 0) goto out; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_Y_ADDR_END, + rval = ccs_write( + sensor, Y_ADDR_END, sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1); if (rval < 0) @@ -1529,26 +1492,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) /* Digital crop */ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { - rval = smiapp_write( - sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET, + rval = ccs_write( + sensor, DIGITAL_CROP_X_OFFSET, sensor->scaler->crop[SMIAPP_PAD_SINK].left); if (rval < 0) goto out; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET, + rval = ccs_write( + sensor, DIGITAL_CROP_Y_OFFSET, sensor->scaler->crop[SMIAPP_PAD_SINK].top); if (rval < 0) goto out; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH, + rval = ccs_write( + sensor, DIGITAL_CROP_IMAGE_WIDTH, sensor->scaler->crop[SMIAPP_PAD_SINK].width); if (rval < 0) goto out; - rval = smiapp_write( - sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT, + rval = ccs_write( + sensor, DIGITAL_CROP_IMAGE_HEIGHT, sensor->scaler->crop[SMIAPP_PAD_SINK].height); if (rval < 0) goto out; @@ -1557,24 +1520,22 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) /* Scaling */ if (CCS_LIM(sensor, SCALING_CAPABILITY) != CCS_SCALING_CAPABILITY_NONE) { - rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE, - sensor->scaling_mode); + rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALE_M, - sensor->scale_m); + rval = ccs_write(sensor, SCALE_M, sensor->scale_m); if (rval < 0) goto out; } /* Output size from sensor */ - rval = smiapp_write(sensor, SMIAPP_REG_U16_X_OUTPUT_SIZE, - sensor->src->crop[SMIAPP_PAD_SRC].width); + rval = ccs_write(sensor, X_OUTPUT_SIZE, + sensor->src->crop[SMIAPP_PAD_SRC].width); if (rval < 0) goto out; - rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_OUTPUT_SIZE, - sensor->src->crop[SMIAPP_PAD_SRC].height); + rval = ccs_write(sensor, Y_OUTPUT_SIZE, + sensor->src->crop[SMIAPP_PAD_SRC].height); if (rval < 0) goto out; @@ -1594,8 +1555,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) goto out; } - rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT, - SMIAPP_MODE_SELECT_STREAMING); + rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING); out: mutex_unlock(&sensor->mutex); @@ -1609,8 +1569,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor) int rval; mutex_lock(&sensor->mutex); - rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT, - SMIAPP_MODE_SELECT_SOFTWARE_STANDBY); + rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY); if (rval) goto out; @@ -1828,7 +1787,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev, sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN); sensor->scaling_mode = - SMIAPP_SCALING_MODE_NONE; + CCS_SCALING_MODE_NO_SCALING; } else if (ssd == sensor->binner) { sensor->binning_horizontal = 1; sensor->binning_vertical = 1; @@ -2063,7 +2022,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); u32 min, max, a, b, max_m; u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN); - int mode = SMIAPP_SCALING_MODE_HORIZONTAL; + int mode = CCS_SCALING_MODE_HORIZONTAL; u32 try[4]; u32 ntry = 0; unsigned int i; @@ -2123,7 +2082,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, if (this > best) { scale_m = try[i]; - mode = SMIAPP_SCALING_MODE_HORIZONTAL; + mode = CCS_SCALING_MODE_HORIZONTAL; best = this; } @@ -2494,26 +2453,24 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID, &minfo->smia_manufacturer_id); if (!rval) - rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID, + rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID, &minfo->model_id); if (!rval) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_REVISION_NUMBER_MAJOR, + CCS_R_MODULE_REVISION_NUMBER_MAJOR, &minfo->revision_number_major); if (!rval) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_REVISION_NUMBER_MINOR, + CCS_R_MODULE_REVISION_NUMBER_MINOR, &minfo->revision_number_minor); if (!rval) - rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_MODULE_DATE_YEAR, + rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR, &minfo->module_year); if (!rval) - rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_MODULE_DATE_MONTH, + rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH, &minfo->module_month); if (!rval) - rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MODULE_DATE_DAY, + rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY, &minfo->module_day); /* Sensor info */ @@ -2522,19 +2479,19 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) &minfo->sensor_mipi_manufacturer_id); if (!rval && !minfo->sensor_mipi_manufacturer_id) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID, + CCS_R_SENSOR_MANUFACTURER_ID, &minfo->sensor_smia_manufacturer_id); if (!rval) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U16_SENSOR_MODEL_ID, + CCS_R_SENSOR_MODEL_ID, &minfo->sensor_model_id); if (!rval) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_SENSOR_REVISION_NUMBER, + CCS_R_SENSOR_REVISION_NUMBER, &minfo->sensor_revision_number); if (!rval) rval = smiapp_read_8only(sensor, - SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION, + CCS_R_SENSOR_FIRMWARE_VERSION, &minfo->sensor_firmware_version); /* SMIA */ @@ -2919,7 +2876,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev) switch (bus_cfg.bus_type) { case V4L2_MBUS_CSI2_DPHY: - hwcfg->csi_signalling_mode = SMIAPP_CSI_SIGNALLING_MODE_CSI2; + hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY; hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; break; case V4L2_MBUS_CCP2: @@ -3095,8 +3052,9 @@ static int smiapp_probe(struct i2c_client *client) */ if (sensor->hwcfg->module_board_orient == SMIAPP_MODULE_BOARD_ORIENT_180) - sensor->hvflip_inv_mask = SMIAPP_IMAGE_ORIENTATION_HFLIP | - SMIAPP_IMAGE_ORIENTATION_VFLIP; + sensor->hvflip_inv_mask = + CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR | + CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; rval = smiapp_call_quirk(sensor, limits); if (rval) { diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h index 1a67cf485dcc..c6e4e05a7522 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/smiapp.h @@ -15,6 +15,8 @@ #include #include +#include "ccs-regs.h" + #include "smiapp-pll.h" #include "smiapp-reg-defs.h" #include "smiapp-regs.h" @@ -220,7 +222,7 @@ struct smiapp_sensor { struct gpio_desc *xshutdown; void *ccs_limits; u8 nbinning_subtypes; - struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES]; + struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1]; u32 mbus_frame_fmts; const struct smiapp_csi_data_format *csi_format; const struct smiapp_csi_data_format *internal_csi_format; From patchwork Wed Sep 30 15:27:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10AA692C for ; Wed, 30 Sep 2020 15:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF3F121D7F for ; Wed, 30 Sep 2020 15:30:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730858AbgI3PaY (ORCPT ); Wed, 30 Sep 2020 11:30:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730872AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5CD9C061755 for ; Wed, 30 Sep 2020 08:29:03 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 4F629634C97 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 013/100] smiapp: Remove quirk function for writing a single 8-bit register Date: Wed, 30 Sep 2020 18:27:31 +0300 Message-Id: <20200930152858.8471-14-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This function is no longer needed as the smiapp_write() function can be used to write 8-bit registers with plain register addresses. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-quirk.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c index 24630c7650d2..9422eb61b424 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.c +++ b/drivers/media/i2c/smiapp/smiapp-quirk.c @@ -14,11 +14,6 @@ #include "smiapp.h" -static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val) -{ - return smiapp_write(sensor, reg, val); -} - static int smiapp_write_8s(struct smiapp_sensor *sensor, const struct smiapp_reg_8 *regs, int len) { @@ -26,7 +21,7 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor, int rval; for (; len > 0; len--, regs++) { - rval = smiapp_write_8(sensor, regs->reg, regs->val); + rval = smiapp_write(sensor, regs->reg, regs->val); if (rval < 0) { dev_err(&client->dev, "error %d writing reg 0x%4.4x, val 0x%2.2x", @@ -170,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor) { - return smiapp_write_8(sensor, 0x3328, 0x00); + return smiapp_write(sensor, 0x3328, 0x00); } static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) @@ -178,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) int rval; /* Workaround: allows fast standby to work properly */ - rval = smiapp_write_8(sensor, 0x3205, 0x04); + rval = smiapp_write(sensor, 0x3205, 0x04); if (rval < 0) return rval; @@ -186,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) usleep_range(2000, 2050); /* Restore it */ - rval = smiapp_write_8(sensor, 0x3205, 0x00); + rval = smiapp_write(sensor, 0x3205, 0x00); if (rval < 0) return rval; - return smiapp_write_8(sensor, 0x3328, 0x80); + return smiapp_write(sensor, 0x3328, 0x80); } static int jt8ev1_init(struct smiapp_sensor *sensor) From patchwork Wed Sep 30 15:27:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809641 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93641618 for ; Wed, 30 Sep 2020 15:30:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 791EE21D7F for ; Wed, 30 Sep 2020 15:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729432AbgI3PaX (ORCPT ); Wed, 30 Sep 2020 11:30:23 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730737AbgI3P3E (ORCPT ); Wed, 30 Sep 2020 11:29:04 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 62CD0634C98 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 014/100] smiapp: Rename register access functions Date: Wed, 30 Sep 2020 18:27:32 +0300 Message-Id: <20200930152858.8471-15-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Rename register access functions by changing smiapp to ccs. The functions operating on register addresses have "addr" appended to the name. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/smiapp-core.c | 67 +++++++++++++------------ drivers/media/i2c/smiapp/smiapp-quirk.c | 22 ++++---- drivers/media/i2c/smiapp/smiapp-regs.c | 47 ++++++++--------- drivers/media/i2c/smiapp/smiapp-regs.h | 14 +++--- 4 files changed, 76 insertions(+), 74 deletions(-) diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c index b9faf38d4bba..5b322194cb4b 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/smiapp-core.c @@ -180,7 +180,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor) j++, reg += width, ptr += width) { u32 val; - ret = smiapp_read(sensor, reg, &val); + ret = ccs_read_addr(sensor, reg, &val); if (ret) goto out_err; @@ -2450,59 +2450,60 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) rval = ccs_read(sensor, MODULE_MANUFACTURER_ID, &minfo->mipi_manufacturer_id); if (!rval && !minfo->mipi_manufacturer_id) - rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID, - &minfo->smia_manufacturer_id); + rval = ccs_read_addr_8only(sensor, + SMIAPP_REG_U8_MANUFACTURER_ID, + &minfo->smia_manufacturer_id); if (!rval) - rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID, - &minfo->model_id); + rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID, + &minfo->model_id); if (!rval) - rval = smiapp_read_8only(sensor, - CCS_R_MODULE_REVISION_NUMBER_MAJOR, - &minfo->revision_number_major); + rval = ccs_read_addr_8only(sensor, + CCS_R_MODULE_REVISION_NUMBER_MAJOR, + &minfo->revision_number_major); if (!rval) - rval = smiapp_read_8only(sensor, - CCS_R_MODULE_REVISION_NUMBER_MINOR, - &minfo->revision_number_minor); + rval = ccs_read_addr_8only(sensor, + CCS_R_MODULE_REVISION_NUMBER_MINOR, + &minfo->revision_number_minor); if (!rval) - rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR, - &minfo->module_year); + rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR, + &minfo->module_year); if (!rval) - rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH, - &minfo->module_month); + rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH, + &minfo->module_month); if (!rval) - rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY, - &minfo->module_day); + rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY, + &minfo->module_day); /* Sensor info */ if (!rval) rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID, &minfo->sensor_mipi_manufacturer_id); if (!rval && !minfo->sensor_mipi_manufacturer_id) - rval = smiapp_read_8only(sensor, - CCS_R_SENSOR_MANUFACTURER_ID, - &minfo->sensor_smia_manufacturer_id); + rval = ccs_read_addr_8only(sensor, + CCS_R_SENSOR_MANUFACTURER_ID, + &minfo->sensor_smia_manufacturer_id); if (!rval) - rval = smiapp_read_8only(sensor, - CCS_R_SENSOR_MODEL_ID, - &minfo->sensor_model_id); + rval = ccs_read_addr_8only(sensor, + CCS_R_SENSOR_MODEL_ID, + &minfo->sensor_model_id); if (!rval) - rval = smiapp_read_8only(sensor, - CCS_R_SENSOR_REVISION_NUMBER, - &minfo->sensor_revision_number); + rval = ccs_read_addr_8only(sensor, + CCS_R_SENSOR_REVISION_NUMBER, + &minfo->sensor_revision_number); if (!rval) - rval = smiapp_read_8only(sensor, - CCS_R_SENSOR_FIRMWARE_VERSION, - &minfo->sensor_firmware_version); + rval = ccs_read_addr_8only(sensor, + CCS_R_SENSOR_FIRMWARE_VERSION, + &minfo->sensor_firmware_version); /* SMIA */ if (!rval) rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version); if (!rval && !minfo->ccs_version) - rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION, - &minfo->smia_version); + rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION, + &minfo->smia_version); if (!rval && !minfo->ccs_version) - rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION, - &minfo->smiapp_version); + rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION, + &minfo->smiapp_version); if (rval) { dev_err(&client->dev, "sensor detection failed\n"); diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c index 9422eb61b424..5db97a16eccf 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.c +++ b/drivers/media/i2c/smiapp/smiapp-quirk.c @@ -14,14 +14,14 @@ #include "smiapp.h" -static int smiapp_write_8s(struct smiapp_sensor *sensor, - const struct smiapp_reg_8 *regs, int len) +static int ccs_write_addr_8s(struct smiapp_sensor *sensor, + const struct smiapp_reg_8 *regs, int len) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; for (; len > 0; len--, regs++) { - rval = smiapp_write(sensor, regs->reg, regs->val); + rval = ccs_write_addr(sensor, regs->reg, regs->val); if (rval < 0) { dev_err(&client->dev, "error %d writing reg 0x%4.4x, val 0x%2.2x", @@ -81,7 +81,7 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor) }; - return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs)); + return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs)); } const struct smiapp_quirk smiapp_jt8ew9_quirk = { @@ -102,7 +102,7 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor) { 0x3b08, 0x8c }, }; - return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs)); + return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs)); } const struct smiapp_quirk smiapp_imx125es_quirk = { @@ -148,13 +148,13 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) { 0x30b0, 0x01 }, }; - rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs)); + rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs)); if (rval < 0) return rval; switch (sensor->hwcfg->ext_clk) { case 9600000: - return smiapp_write_8s(sensor, regs_96, + return ccs_write_addr_8s(sensor, regs_96, ARRAY_SIZE(regs_96)); default: dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n", @@ -165,7 +165,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor) { - return smiapp_write(sensor, 0x3328, 0x00); + return ccs_write_addr(sensor, 0x3328, 0x00); } static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) @@ -173,7 +173,7 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) int rval; /* Workaround: allows fast standby to work properly */ - rval = smiapp_write(sensor, 0x3205, 0x04); + rval = ccs_write_addr(sensor, 0x3205, 0x04); if (rval < 0) return rval; @@ -181,11 +181,11 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) usleep_range(2000, 2050); /* Restore it */ - rval = smiapp_write(sensor, 0x3205, 0x00); + rval = ccs_write_addr(sensor, 0x3205, 0x00); if (rval < 0) return rval; - return smiapp_write(sensor, 0x3328, 0x80); + return ccs_write_addr(sensor, 0x3328, 0x80); } static int jt8ev1_init(struct smiapp_sensor *sensor) diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c index 904054d303ba..173d9f8fe56c 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.c +++ b/drivers/media/i2c/smiapp/smiapp-regs.c @@ -66,8 +66,8 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. */ -static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg, - u16 len, u32 *val) +static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len, + u32 *val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct i2c_msg msg; @@ -113,8 +113,8 @@ static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg, } /* Read a register using 8-bit access only. */ -static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, - u16 len, u32 *val) +static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg, + u16 len, u32 *val) { unsigned int i; int rval; @@ -124,7 +124,7 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, for (i = 0; i < len; i++) { u32 val8; - rval = ____smiapp_read(sensor, reg + i, 1, &val8); + rval = ____ccs_read_addr(sensor, reg + i, 1, &val8); if (rval < 0) return rval; *val |= val8 << ((len - i - 1) << 3); @@ -147,18 +147,19 @@ unsigned int ccs_reg_width(u32 reg) * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. */ -static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, - bool only8) +static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val, + bool only8) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); unsigned int len = ccs_reg_width(reg); int rval; if (!only8) - rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); + rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len, + val); else - rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len, - val); + rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg), + len, val); if (rval < 0) return rval; @@ -168,16 +169,16 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, return 0; } -int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) { - return __smiapp_read( + return __ccs_read_addr( sensor, reg, val, smiapp_needs_quirk(sensor, SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY)); } -static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, - bool force8) +static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, + bool force8) { int rval; @@ -189,22 +190,22 @@ static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, return rval; if (force8) - return __smiapp_read(sensor, reg, val, true); + return __ccs_read_addr(sensor, reg, val, true); - return smiapp_read_no_quirk(sensor, reg, val); + return ccs_read_addr_no_quirk(sensor, reg, val); } -int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val) { - return smiapp_read_quirk(sensor, reg, val, false); + return ccs_read_addr_quirk(sensor, reg, val, false); } -int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) { - return smiapp_read_quirk(sensor, reg, val, true); + return ccs_read_addr_quirk(sensor, reg, val, true); } -int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) +int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct i2c_msg msg; @@ -253,7 +254,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) * Write to a 8/16-bit register. * Returns zero if successful, or non-zero otherwise. */ -int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) +int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val) { int rval; @@ -263,5 +264,5 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) if (rval < 0) return rval; - return smiapp_write_no_quirk(sensor, reg, val); + return ccs_write_addr_no_quirk(sensor, reg, val); } diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h index dc946096f368..5df794f65dfc 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.h +++ b/drivers/media/i2c/smiapp/smiapp-regs.h @@ -20,18 +20,18 @@ struct smiapp_sensor; -int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); -int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val); +int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); +int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val); +int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); +int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); +int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val); unsigned int ccs_reg_width(u32 reg); #define ccs_read(sensor, reg_name, val) \ - smiapp_read(sensor, CCS_R_##reg_name, val) + ccs_read_addr(sensor, CCS_R_##reg_name, val) #define ccs_write(sensor, reg_name, val) \ - smiapp_write(sensor, CCS_R_##reg_name, val) + ccs_write_addr(sensor, CCS_R_##reg_name, val) #endif From patchwork Wed Sep 30 15:27:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4377A139A for ; Wed, 30 Sep 2020 15:30:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0A11621D43 for ; Wed, 30 Sep 2020 15:30:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730626AbgI3PaJ (ORCPT ); Wed, 30 Sep 2020 11:30:09 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730796AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 8B37E634C99 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 015/100] smiapp: Internal rename to CCS Date: Wed, 30 Sep 2020 18:27:33 +0300 Message-Id: <20200930152858.8471-16-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Rename internal names to reflect the driver's new reference. The module name remains the same. Also fix trivial coding style issues on the way related to e.g. alignment changes due to the rename. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/Makefile | 4 +- .../i2c/smiapp/{smiapp-core.c => ccs-core.c} | 888 +++++++++--------- .../smiapp/{smiapp-quirk.c => ccs-quirk.c} | 43 +- .../smiapp/{smiapp-quirk.h => ccs-quirk.h} | 46 +- .../{smiapp-regs.c => ccs-reg-access.c} | 41 +- .../{smiapp-regs.h => ccs-reg-access.h} | 16 +- drivers/media/i2c/smiapp/{smiapp.h => ccs.h} | 124 +-- 7 files changed, 576 insertions(+), 586 deletions(-) rename drivers/media/i2c/smiapp/{smiapp-core.c => ccs-core.c} (75%) rename drivers/media/i2c/smiapp/{smiapp-quirk.c => ccs-quirk.c} (83%) rename drivers/media/i2c/smiapp/{smiapp-quirk.h => ccs-quirk.h} (59%) rename drivers/media/i2c/smiapp/{smiapp-regs.c => ccs-reg-access.c} (79%) rename drivers/media/i2c/smiapp/{smiapp-regs.h => ccs-reg-access.h} (55%) rename drivers/media/i2c/smiapp/{smiapp.h => ccs.h} (65%) diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile index a7bf53dd4a63..c9d300b5d2bc 100644 --- a/drivers/media/i2c/smiapp/Makefile +++ b/drivers/media/i2c/smiapp/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -smiapp-objs += smiapp-core.o smiapp-regs.o \ - smiapp-quirk.o ccs-limits.o +smiapp-objs += ccs-core.o ccs-reg-access.o \ + ccs-quirk.o ccs-limits.o obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o ccflags-y += -I $(srctree)/drivers/media/i2c diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/ccs-core.c similarity index 75% rename from drivers/media/i2c/smiapp/smiapp-core.c rename to drivers/media/i2c/smiapp/ccs-core.c index 5b322194cb4b..dd093a7d2ef4 100644 --- a/drivers/media/i2c/smiapp/smiapp-core.c +++ b/drivers/media/i2c/smiapp/ccs-core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/smiapp-core.c + * drivers/media/i2c/smiapp/ccs-core.c * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -27,10 +27,10 @@ #include #include +#include "ccs.h" #include "ccs-limits.h" -#include "smiapp.h" -#define SMIAPP_ALIGN_DIM(dim, flags) \ +#define CCS_ALIGN_DIM(dim, flags) \ ((flags) & V4L2_SEL_FLAG_GE \ ? ALIGN((dim), 2) \ : (dim) & ~1) @@ -41,20 +41,20 @@ struct ccs_limit_offset { } ccs_limit_offsets[CCS_L_LAST + 1]; /* - * smiapp_module_idents - supported camera modules + * ccs_module_idents - supported camera modules */ -static const struct smiapp_module_ident smiapp_module_idents[] = { - SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"), - SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"), - SMIAPP_IDENT_L(0x07, 0x7698, -1, "ovm7698"), - SMIAPP_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"), - SMIAPP_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"), - SMIAPP_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk), - SMIAPP_IDENT_L(0x0c, 0x213e, -1, "et8en2"), - SMIAPP_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"), - SMIAPP_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk), - SMIAPP_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk), - SMIAPP_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk), +static const struct ccs_module_ident ccs_module_idents[] = { + CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"), + CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"), + CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"), + CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"), + CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"), + CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk), + CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"), + CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"), + CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk), + CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk), + CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk), }; /* @@ -78,7 +78,7 @@ static void ccs_assign_limit(void *ptr, unsigned int width, u32 val) } } -static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit, +static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset, void **__ptr) { const struct ccs_limit *linfo; @@ -98,7 +98,7 @@ static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit, return 0; } -void ccs_replace_limit(struct smiapp_sensor *sensor, +void ccs_replace_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset, u32 val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -118,7 +118,7 @@ void ccs_replace_limit(struct smiapp_sensor *sensor, ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val); } -static u32 ccs_get_limit(struct smiapp_sensor *sensor, +static u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset) { void *ptr; @@ -148,7 +148,7 @@ static u32 ccs_get_limit(struct smiapp_sensor *sensor, #define CCS_LIM_AT(sensor, limit, offset) \ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset)) -static int ccs_read_all_limits(struct smiapp_sensor *sensor) +static int ccs_read_all_limits(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); void *ptr, *alloc, *end; @@ -224,7 +224,7 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor) return ret; } -static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) +static int ccs_read_frame_fmt(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc; @@ -351,7 +351,7 @@ static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor) return 0; } -static int smiapp_pll_configure(struct smiapp_sensor *sensor) +static int ccs_pll_configure(struct ccs_sensor *sensor) { struct smiapp_pll *pll = &sensor->pll; int rval; @@ -386,8 +386,7 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor) return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div); } -static int smiapp_pll_try(struct smiapp_sensor *sensor, - struct smiapp_pll *pll) +static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct smiapp_pll_limits lim = { @@ -425,7 +424,7 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor, return smiapp_pll_calculate(&client->dev, &lim, pll); } -static int smiapp_pll_update(struct smiapp_sensor *sensor) +static int ccs_pll_update(struct ccs_sensor *sensor) { struct smiapp_pll *pll = &sensor->pll; int rval; @@ -437,7 +436,7 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor) pll->scale_m = sensor->scale_m; pll->bits_per_pixel = sensor->csi_format->compressed; - rval = smiapp_pll_try(sensor, pll); + rval = ccs_pll_try(sensor, pll); if (rval < 0) return rval; @@ -455,12 +454,12 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor) * */ -static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor) +static void __ccs_update_exposure_limits(struct ccs_sensor *sensor) { struct v4l2_ctrl *ctrl = sensor->exposure; int max; - max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height + max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height + sensor->vblank->val - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN); @@ -475,40 +474,40 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor) * 3. Pixel order, same as in pixel_order_str. Formats for all four pixel * orders must be defined. */ -static const struct smiapp_csi_data_format smiapp_csi_data_formats[] = { - { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GBRG, }, - { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GBRG, }, - { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GBRG, }, - { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GBRG, }, - { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GBRG, }, - { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GRBG, }, - { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_RGGB, }, - { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_BGGR, }, - { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GBRG, }, +static const struct ccs_csi_data_format ccs_csi_data_formats[] = { + { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, }, + { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, }, + { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, }, + { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, }, + { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, }, + { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, }, + { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, }, + { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, }, + { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, }, }; static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" }; #define to_csi_format_idx(fmt) (((unsigned long)(fmt) \ - - (unsigned long)smiapp_csi_data_formats) \ - / sizeof(*smiapp_csi_data_formats)) + - (unsigned long)ccs_csi_data_formats) \ + / sizeof(*ccs_csi_data_formats)) -static u32 smiapp_pixel_order(struct smiapp_sensor *sensor) +static u32 ccs_pixel_order(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int flip = 0; @@ -527,31 +526,31 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor) return sensor->default_pixel_order ^ flip; } -static void smiapp_update_mbus_formats(struct smiapp_sensor *sensor) +static void ccs_update_mbus_formats(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); unsigned int csi_format_idx = to_csi_format_idx(sensor->csi_format) & ~3; unsigned int internal_csi_format_idx = to_csi_format_idx(sensor->internal_csi_format) & ~3; - unsigned int pixel_order = smiapp_pixel_order(sensor); + unsigned int pixel_order = ccs_pixel_order(sensor); sensor->mbus_frame_fmts = sensor->default_mbus_frame_fmts << pixel_order; sensor->csi_format = - &smiapp_csi_data_formats[csi_format_idx + pixel_order]; + &ccs_csi_data_formats[csi_format_idx + pixel_order]; sensor->internal_csi_format = - &smiapp_csi_data_formats[internal_csi_format_idx + &ccs_csi_data_formats[internal_csi_format_idx + pixel_order]; BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order - >= ARRAY_SIZE(smiapp_csi_data_formats)); + >= ARRAY_SIZE(ccs_csi_data_formats)); dev_dbg(&client->dev, "new pixel order %s\n", pixel_order_str[pixel_order]); } -static const char * const smiapp_test_patterns[] = { +static const char * const ccs_test_patterns[] = { "Disabled", "Solid Colour", "Eight Vertical Colour Bars", @@ -559,10 +558,10 @@ static const char * const smiapp_test_patterns[] = { "Pseudorandom Sequence (PN9)", }; -static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) +static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) { - struct smiapp_sensor *sensor = - container_of(ctrl->handler, struct smiapp_subdev, ctrl_handler) + struct ccs_sensor *sensor = + container_of(ctrl->handler, struct ccs_subdev, ctrl_handler) ->sensor; struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int pm_status; @@ -585,17 +584,17 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) orient ^= sensor->hvflip_inv_mask; - smiapp_update_mbus_formats(sensor); + ccs_update_mbus_formats(sensor); break; case V4L2_CID_VBLANK: exposure = sensor->exposure->val; - __smiapp_update_exposure_limits(sensor); + __ccs_update_exposure_limits(sensor); if (exposure > sensor->exposure->maximum) { sensor->exposure->val = sensor->exposure->maximum; - rval = smiapp_set_ctrl(sensor->exposure); + rval = ccs_set_ctrl(sensor->exposure); if (rval < 0) return rval; } @@ -605,7 +604,7 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) if (sensor->streaming) return -EBUSY; - rval = smiapp_pll_update(sensor); + rval = ccs_pll_update(sensor); if (rval) return rval; @@ -641,14 +640,14 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_VBLANK: rval = ccs_write(sensor, FRAME_LENGTH_LINES, sensor->pixel_array->crop[ - SMIAPP_PA_PAD_SRC].height + CCS_PA_PAD_SRC].height + ctrl->val); break; case V4L2_CID_HBLANK: rval = ccs_write(sensor, LINE_LENGTH_PCK, sensor->pixel_array->crop[ - SMIAPP_PA_PAD_SRC].width + CCS_PA_PAD_SRC].width + ctrl->val); break; @@ -689,11 +688,11 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl) return rval; } -static const struct v4l2_ctrl_ops smiapp_ctrl_ops = { - .s_ctrl = smiapp_set_ctrl, +static const struct v4l2_ctrl_ops ccs_ctrl_ops = { + .s_ctrl = ccs_set_ctrl, }; -static int smiapp_init_controls(struct smiapp_sensor *sensor) +static int ccs_init_controls(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -705,7 +704,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor) sensor->pixel_array->ctrl_handler.lock = &sensor->mutex; sensor->analog_gain = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), @@ -714,38 +713,38 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor) /* Exposure limits will be updated soon, use just something here. */ sensor->exposure = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_EXPOSURE, 0, 0, 1, 0); sensor->hflip = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); sensor->vflip = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); sensor->vblank = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_VBLANK, 0, 1, 1, 0); if (sensor->vblank) sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE; sensor->hblank = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_HBLANK, 0, 1, 1, 0); if (sensor->hblank) sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE; sensor->pixel_rate_parray = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops, + &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler, - &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN, - ARRAY_SIZE(smiapp_test_patterns) - 1, - 0, 0, smiapp_test_patterns); + &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ccs_test_patterns) - 1, + 0, 0, ccs_test_patterns); if (sensor->pixel_array->ctrl_handler.error) { dev_err(&client->dev, @@ -766,7 +765,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor) sensor->src->ctrl_handler.lock = &sensor->mutex; sensor->pixel_rate_csi = v4l2_ctrl_new_std( - &sensor->src->ctrl_handler, &smiapp_ctrl_ops, + &sensor->src->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); if (sensor->src->ctrl_handler.error) { @@ -785,7 +784,7 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor) * For controls that require information on available media bus codes * and linke frequencies. */ -static int smiapp_init_late_controls(struct smiapp_sensor *sensor) +static int ccs_init_late_controls(struct ccs_sensor *sensor) { unsigned long *valid_link_freqs = &sensor->valid_link_freqs[ sensor->csi_format->compressed - sensor->compressed_min_bpp]; @@ -796,19 +795,19 @@ static int smiapp_init_late_controls(struct smiapp_sensor *sensor) sensor->test_data[i] = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, - &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i, + &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i, 0, max_value, 1, max_value); } sensor->link_freq = v4l2_ctrl_new_int_menu( - &sensor->src->ctrl_handler, &smiapp_ctrl_ops, + &sensor->src->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs), __ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock); return sensor->src->ctrl_handler.error; } -static void smiapp_free_controls(struct smiapp_sensor *sensor) +static void ccs_free_controls(struct ccs_sensor *sensor) { unsigned int i; @@ -816,7 +815,7 @@ static void smiapp_free_controls(struct smiapp_sensor *sensor) v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler); } -static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) +static int ccs_get_mbus_formats(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct smiapp_pll *pll = &sensor->pll; @@ -863,11 +862,11 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n", i, fmt >> 8, (u8)fmt); - for (j = 0; j < ARRAY_SIZE(smiapp_csi_data_formats); j++) { - const struct smiapp_csi_data_format *f = - &smiapp_csi_data_formats[j]; + for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) { + const struct ccs_csi_data_format *f = + &ccs_csi_data_formats[j]; - if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG) + if (f->pixel_order != CCS_PIXEL_ORDER_GRBG) continue; if (f->width != fmt >> @@ -887,12 +886,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) pll->binning_vertical = 1; pll->scale_m = sensor->scale_m; - for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) { + for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) { sensor->compressed_min_bpp = - min(smiapp_csi_data_formats[i].compressed, + min(ccs_csi_data_formats[i].compressed, sensor->compressed_min_bpp); compressed_max_bpp = - max(smiapp_csi_data_formats[i].compressed, + max(ccs_csi_data_formats[i].compressed, compressed_max_bpp); } @@ -903,9 +902,9 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) if (!sensor->valid_link_freqs) return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) { - const struct smiapp_csi_data_format *f = - &smiapp_csi_data_formats[i]; + for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) { + const struct ccs_csi_data_format *f = + &ccs_csi_data_formats[i]; unsigned long *valid_link_freqs = &sensor->valid_link_freqs[ f->compressed - sensor->compressed_min_bpp]; @@ -919,7 +918,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) { pll->link_freq = sensor->hwcfg->op_sys_clock[j]; - rval = smiapp_pll_try(sensor, pll); + rval = ccs_pll_try(sensor, pll); dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n", pll->link_freq, pll->bits_per_pixel, rval ? "not ok" : "ok"); @@ -951,12 +950,12 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor) return -EINVAL; } - smiapp_update_mbus_formats(sensor); + ccs_update_mbus_formats(sensor); return 0; } -static void smiapp_update_blanking(struct smiapp_sensor *sensor) +static void ccs_update_blanking(struct ccs_sensor *sensor) { struct v4l2_ctrl *vblank = sensor->vblank; struct v4l2_ctrl *hblank = sensor->hblank; @@ -980,42 +979,42 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor) min = max_t(int, CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES), min_fll - - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height); - max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height; + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height); + max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height; __v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min); min = max_t(int, min_llp - - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width, + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width, min_lbp); - max = max_llp - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width; + max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width; __v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min); - __smiapp_update_exposure_limits(sensor); + __ccs_update_exposure_limits(sensor); } -static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor) +static int ccs_pll_blanking_update(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; - rval = smiapp_pll_update(sensor); + rval = ccs_pll_update(sensor); if (rval < 0) return rval; /* Output from pixel array, including blanking */ - smiapp_update_blanking(sensor); + ccs_update_blanking(sensor); dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val); dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val); dev_dbg(&client->dev, "real timeperframe\t100/%d\n", sensor->pll.pixel_rate_pixel_array / - ((sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width + ((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width + sensor->hblank->val) * - (sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height + (sensor->pixel_array->crop[CCS_PA_PAD_SRC].height + sensor->vblank->val) / 100)); return 0; @@ -1027,8 +1026,8 @@ static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor) * */ -static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, - u8 *status) +static int ccs_read_nvm_page(struct ccs_sensor *sensor, u32 p, u8 *nvm, + u8 *status) { unsigned int i; int rval; @@ -1082,8 +1081,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm, return 0; } -static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm, - size_t nvm_size) +static int ccs_read_nvm(struct ccs_sensor *sensor, unsigned char *nvm, + size_t nvm_size) { u8 status = 0; u32 p; @@ -1091,7 +1090,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm, for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1) && !rval; p++) { - rval = smiapp_read_nvm_page(sensor, p, nvm, &status); + rval = ccs_read_nvm_page(sensor, p, nvm, &status); nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1; } @@ -1111,7 +1110,7 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm, * SMIA++ CCI address control * */ -static int smiapp_change_cci_addr(struct smiapp_sensor *sensor) +static int ccs_change_cci_addr(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -1142,9 +1141,9 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor) * SMIA++ Mode Control * */ -static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor) +static int ccs_setup_flash_strobe(struct ccs_sensor *sensor) { - struct smiapp_flash_strobe_parms *strobe_setup; + struct ccs_flash_strobe_parms *strobe_setup; unsigned int ext_freq = sensor->hwcfg->ext_clk; u32 tmp; u32 strobe_adjustment; @@ -1268,16 +1267,16 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor) * Power management */ -static int smiapp_power_on(struct device *dev) +static int ccs_power_on(struct device *dev) { struct v4l2_subdev *subdev = dev_get_drvdata(dev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); /* * The sub-device related to the I2C device is always the * source one, i.e. ssds[0]. */ - struct smiapp_sensor *sensor = - container_of(ssd, struct smiapp_sensor, ssds[0]); + struct ccs_sensor *sensor = + container_of(ssd, struct ccs_sensor, ssds[0]); unsigned int sleep; int rval; @@ -1312,7 +1311,7 @@ static int smiapp_power_on(struct device *dev) */ if (sensor->hwcfg->i2c_addr_alt) { - rval = smiapp_change_cci_addr(sensor); + rval = ccs_change_cci_addr(sensor); if (rval) { dev_err(dev, "cci address change error\n"); goto out_cci_addr_fail; @@ -1326,7 +1325,7 @@ static int smiapp_power_on(struct device *dev) } if (sensor->hwcfg->i2c_addr_alt) { - rval = smiapp_change_cci_addr(sensor); + rval = ccs_change_cci_addr(sensor); if (rval) { dev_err(dev, "cci address change error\n"); goto out_cci_addr_fail; @@ -1372,7 +1371,7 @@ static int smiapp_power_on(struct device *dev) if (rval < 0) goto out_cci_addr_fail; - rval = smiapp_call_quirk(sensor, post_poweron); + rval = ccs_call_quirk(sensor, post_poweron); if (rval) { dev_err(dev, "post_poweron quirks failed\n"); goto out_cci_addr_fail; @@ -1390,12 +1389,12 @@ static int smiapp_power_on(struct device *dev) return rval; } -static int smiapp_power_off(struct device *dev) +static int ccs_power_off(struct device *dev) { struct v4l2_subdev *subdev = dev_get_drvdata(dev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct smiapp_sensor *sensor = - container_of(ssd, struct smiapp_sensor, ssds[0]); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct ccs_sensor *sensor = + container_of(ssd, struct ccs_sensor, ssds[0]); /* * Currently power/clock to lens are enable/disabled separately @@ -1420,7 +1419,7 @@ static int smiapp_power_off(struct device *dev) * Video stream management */ -static int smiapp_start_streaming(struct smiapp_sensor *sensor) +static int ccs_start_streaming(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); unsigned int binning_mode; @@ -1454,33 +1453,33 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) goto out; /* Set up PLL */ - rval = smiapp_pll_configure(sensor); + rval = ccs_pll_configure(sensor); if (rval) goto out; /* Analog crop start coordinates */ rval = ccs_write(sensor, X_ADDR_START, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left); + sensor->pixel_array->crop[CCS_PA_PAD_SRC].left); if (rval < 0) goto out; rval = ccs_write(sensor, Y_ADDR_START, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top); + sensor->pixel_array->crop[CCS_PA_PAD_SRC].top); if (rval < 0) goto out; /* Analog crop end coordinates */ rval = ccs_write( sensor, X_ADDR_END, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left - + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1); + sensor->pixel_array->crop[CCS_PA_PAD_SRC].left + + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1); if (rval < 0) goto out; rval = ccs_write( sensor, Y_ADDR_END, - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top - + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1); + sensor->pixel_array->crop[CCS_PA_PAD_SRC].top + + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1); if (rval < 0) goto out; @@ -1494,25 +1493,25 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { rval = ccs_write( sensor, DIGITAL_CROP_X_OFFSET, - sensor->scaler->crop[SMIAPP_PAD_SINK].left); + sensor->scaler->crop[CCS_PAD_SINK].left); if (rval < 0) goto out; rval = ccs_write( sensor, DIGITAL_CROP_Y_OFFSET, - sensor->scaler->crop[SMIAPP_PAD_SINK].top); + sensor->scaler->crop[CCS_PAD_SINK].top); if (rval < 0) goto out; rval = ccs_write( sensor, DIGITAL_CROP_IMAGE_WIDTH, - sensor->scaler->crop[SMIAPP_PAD_SINK].width); + sensor->scaler->crop[CCS_PAD_SINK].width); if (rval < 0) goto out; rval = ccs_write( sensor, DIGITAL_CROP_IMAGE_HEIGHT, - sensor->scaler->crop[SMIAPP_PAD_SINK].height); + sensor->scaler->crop[CCS_PAD_SINK].height); if (rval < 0) goto out; } @@ -1531,11 +1530,11 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) /* Output size from sensor */ rval = ccs_write(sensor, X_OUTPUT_SIZE, - sensor->src->crop[SMIAPP_PAD_SRC].width); + sensor->src->crop[CCS_PAD_SRC].width); if (rval < 0) goto out; rval = ccs_write(sensor, Y_OUTPUT_SIZE, - sensor->src->crop[SMIAPP_PAD_SRC].height); + sensor->src->crop[CCS_PAD_SRC].height); if (rval < 0) goto out; @@ -1544,12 +1543,12 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) && sensor->hwcfg->strobe_setup != NULL && sensor->hwcfg->strobe_setup->trigger != 0) { - rval = smiapp_setup_flash_strobe(sensor); + rval = ccs_setup_flash_strobe(sensor); if (rval) goto out; } - rval = smiapp_call_quirk(sensor, pre_streamon); + rval = ccs_call_quirk(sensor, pre_streamon); if (rval) { dev_err(&client->dev, "pre_streamon quirks failed\n"); goto out; @@ -1563,7 +1562,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor) return rval; } -static int smiapp_stop_streaming(struct smiapp_sensor *sensor) +static int ccs_stop_streaming(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -1573,7 +1572,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor) if (rval) goto out; - rval = smiapp_call_quirk(sensor, post_streamoff); + rval = ccs_call_quirk(sensor, post_streamoff); if (rval) dev_err(&client->dev, "post_streamoff quirks failed\n"); @@ -1586,7 +1585,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor) * V4L2 subdev video operations */ -static int smiapp_pm_get_init(struct smiapp_sensor *sensor) +static int ccs_pm_get_init(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -1610,9 +1609,9 @@ static int smiapp_pm_get_init(struct smiapp_sensor *sensor) return 0; } -static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable) +static int ccs_set_stream(struct v4l2_subdev *subdev, int enable) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -1620,7 +1619,7 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable) return 0; if (!enable) { - smiapp_stop_streaming(sensor); + ccs_stop_streaming(sensor); sensor->streaming = false; pm_runtime_mark_last_busy(&client->dev); pm_runtime_put_autosuspend(&client->dev); @@ -1628,13 +1627,13 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable) return 0; } - rval = smiapp_pm_get_init(sensor); + rval = ccs_pm_get_init(sensor); if (rval) return rval; sensor->streaming = true; - rval = smiapp_start_streaming(sensor); + rval = ccs_start_streaming(sensor); if (rval < 0) { sensor->streaming = false; pm_runtime_mark_last_busy(&client->dev); @@ -1644,12 +1643,12 @@ static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable) return rval; } -static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_mbus_code_enum *code) +static int ccs_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) { struct i2c_client *client = v4l2_get_subdevdata(subdev); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); unsigned int i; int idx = -1; int rval = -EINVAL; @@ -1659,7 +1658,7 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev, dev_err(&client->dev, "subdev %s, pad %d, index %d\n", subdev->name, code->pad, code->index); - if (subdev != &sensor->src->sd || code->pad != SMIAPP_PAD_SRC) { + if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) { if (code->index) goto out; @@ -1668,12 +1667,12 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev, goto out; } - for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) { + for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) { if (sensor->mbus_frame_fmts & (1 << i)) idx++; if (idx == code->index) { - code->code = smiapp_csi_data_formats[i].code; + code->code = ccs_csi_data_formats[i].code; dev_err(&client->dev, "found index %d, i %d, code %x\n", code->index, i, code->code); rval = 0; @@ -1687,22 +1686,21 @@ static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev, return rval; } -static u32 __smiapp_get_mbus_code(struct v4l2_subdev *subdev, - unsigned int pad) +static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); - if (subdev == &sensor->src->sd && pad == SMIAPP_PAD_SRC) + if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC) return sensor->csi_format->code; else return sensor->internal_csi_format->code; } -static int __smiapp_get_format(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) +static int __ccs_get_format(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { fmt->format = *v4l2_subdev_get_try_format(subdev, cfg, @@ -1715,7 +1713,7 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev, else r = &ssd->sink_fmt; - fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad); + fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad); fmt->format.width = r->width; fmt->format.height = r->height; fmt->format.field = V4L2_FIELD_NONE; @@ -1724,26 +1722,26 @@ static int __smiapp_get_format(struct v4l2_subdev *subdev, return 0; } -static int smiapp_get_format(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) +static int ccs_get_format(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int rval; mutex_lock(&sensor->mutex); - rval = __smiapp_get_format(subdev, cfg, fmt); + rval = __ccs_get_format(subdev, cfg, fmt); mutex_unlock(&sensor->mutex); return rval; } -static void smiapp_get_crop_compose(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_rect **crops, - struct v4l2_rect **comps, int which) +static void ccs_get_crop_compose(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_rect **crops, + struct v4l2_rect **comps, int which) { - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); unsigned int i; if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { @@ -1761,27 +1759,27 @@ static void smiapp_get_crop_compose(struct v4l2_subdev *subdev, } if (comps) { *comps = v4l2_subdev_get_try_compose(subdev, cfg, - SMIAPP_PAD_SINK); + CCS_PAD_SINK); BUG_ON(!*comps); } } } /* Changes require propagation only on sink pad. */ -static void smiapp_propagate(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, int which, - int target) +static void ccs_propagate(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, int which, + int target) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct v4l2_rect *comp, *crops[SMIAPP_PADS]; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct v4l2_rect *comp, *crops[CCS_PADS]; - smiapp_get_crop_compose(subdev, cfg, crops, &comp, which); + ccs_get_crop_compose(subdev, cfg, crops, &comp, which); switch (target) { case V4L2_SEL_TGT_CROP: - comp->width = crops[SMIAPP_PAD_SINK]->width; - comp->height = crops[SMIAPP_PAD_SINK]->height; + comp->width = crops[CCS_PAD_SINK]->width; + comp->height = crops[CCS_PAD_SINK]->height; if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { if (ssd == sensor->scaler) { sensor->scale_m = @@ -1795,40 +1793,40 @@ static void smiapp_propagate(struct v4l2_subdev *subdev, } fallthrough; case V4L2_SEL_TGT_COMPOSE: - *crops[SMIAPP_PAD_SRC] = *comp; + *crops[CCS_PAD_SRC] = *comp; break; default: BUG(); } } -static const struct smiapp_csi_data_format -*smiapp_validate_csi_data_format(struct smiapp_sensor *sensor, u32 code) +static const struct ccs_csi_data_format +*ccs_validate_csi_data_format(struct ccs_sensor *sensor, u32 code) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) { - if (sensor->mbus_frame_fmts & (1 << i) - && smiapp_csi_data_formats[i].code == code) - return &smiapp_csi_data_formats[i]; + for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) { + if (sensor->mbus_frame_fmts & (1 << i) && + ccs_csi_data_formats[i].code == code) + return &ccs_csi_data_formats[i]; } return sensor->csi_format; } -static int smiapp_set_format_source(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) +static int ccs_set_format_source(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - const struct smiapp_csi_data_format *csi_format, + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + const struct ccs_csi_data_format *csi_format, *old_csi_format = sensor->csi_format; unsigned long *valid_link_freqs; u32 code = fmt->format.code; unsigned int i; int rval; - rval = __smiapp_get_format(subdev, cfg, fmt); + rval = __ccs_get_format(subdev, cfg, fmt); if (rval) return rval; @@ -1839,7 +1837,7 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev, if (subdev != &sensor->src->sd) return 0; - csi_format = smiapp_validate_csi_data_format(sensor, code); + csi_format = ccs_validate_csi_data_format(sensor, code); fmt->format.code = csi_format->code; @@ -1866,23 +1864,23 @@ static int smiapp_set_format_source(struct v4l2_subdev *subdev, __fls(*valid_link_freqs), ~*valid_link_freqs, __ffs(*valid_link_freqs)); - return smiapp_pll_update(sensor); + return ccs_pll_update(sensor); } -static int smiapp_set_format(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *fmt) +static int ccs_set_format(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct v4l2_rect *crops[SMIAPP_PADS]; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct v4l2_rect *crops[CCS_PADS]; mutex_lock(&sensor->mutex); if (fmt->pad == ssd->source_pad) { int rval; - rval = smiapp_set_format_source(subdev, cfg, fmt); + rval = ccs_set_format_source(subdev, cfg, fmt); mutex_unlock(&sensor->mutex); @@ -1890,7 +1888,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev, } /* Sink pad. Width and height are changeable here. */ - fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad); + fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad); fmt->format.width &= ~1; fmt->format.height &= ~1; fmt->format.field = V4L2_FIELD_NONE; @@ -1904,7 +1902,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE), CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE)); - smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which); + ccs_get_crop_compose(subdev, cfg, crops, NULL, fmt->which); crops[ssd->sink_pad]->left = 0; crops[ssd->sink_pad]->top = 0; @@ -1912,8 +1910,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev, crops[ssd->sink_pad]->height = fmt->format.height; if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) ssd->sink_fmt = *crops[ssd->sink_pad]; - smiapp_propagate(subdev, cfg, fmt->which, - V4L2_SEL_TGT_CROP); + ccs_propagate(subdev, cfg, fmt->which, V4L2_SEL_TGT_CROP); mutex_unlock(&sensor->mutex); @@ -1929,7 +1926,7 @@ static int smiapp_set_format(struct v4l2_subdev *subdev, static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w, int h, int ask_h, u32 flags) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); struct i2c_client *client = v4l2_get_subdevdata(subdev); int val = 0; @@ -1964,27 +1961,27 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w, return val; } -static void smiapp_set_compose_binner(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel, - struct v4l2_rect **crops, - struct v4l2_rect *comp) +static void ccs_set_compose_binner(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel, + struct v4l2_rect **crops, + struct v4l2_rect *comp) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); unsigned int i; unsigned int binh = 1, binv = 1; int best = scaling_goodness( subdev, - crops[SMIAPP_PAD_SINK]->width, sel->r.width, - crops[SMIAPP_PAD_SINK]->height, sel->r.height, sel->flags); + crops[CCS_PAD_SINK]->width, sel->r.width, + crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags); for (i = 0; i < sensor->nbinning_subtypes; i++) { int this = scaling_goodness( subdev, - crops[SMIAPP_PAD_SINK]->width + crops[CCS_PAD_SINK]->width / sensor->binning_subtypes[i].horizontal, sel->r.width, - crops[SMIAPP_PAD_SINK]->height + crops[CCS_PAD_SINK]->height / sensor->binning_subtypes[i].vertical, sel->r.height, sel->flags); @@ -1999,8 +1996,8 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev, sensor->binning_horizontal = binh; } - sel->r.width = (crops[SMIAPP_PAD_SINK]->width / binh) & ~1; - sel->r.height = (crops[SMIAPP_PAD_SINK]->height / binv) & ~1; + sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1; + sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1; } /* @@ -2012,14 +2009,14 @@ static void smiapp_set_compose_binner(struct v4l2_subdev *subdev, * Also try whether horizontal scaler or full scaler gives a better * result. */ -static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel, - struct v4l2_rect **crops, - struct v4l2_rect *comp) +static void ccs_set_compose_scaler(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel, + struct v4l2_rect **crops, + struct v4l2_rect *comp) { struct i2c_client *client = v4l2_get_subdevdata(subdev); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); u32 min, max, a, b, max_m; u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN); int mode = CCS_SCALING_MODE_HORIZONTAL; @@ -2029,15 +2026,15 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, int best = INT_MIN; sel->r.width = min_t(unsigned int, sel->r.width, - crops[SMIAPP_PAD_SINK]->width); + crops[CCS_PAD_SINK]->width); sel->r.height = min_t(unsigned int, sel->r.height, - crops[SMIAPP_PAD_SINK]->height); + crops[CCS_PAD_SINK]->height); - a = crops[SMIAPP_PAD_SINK]->width + a = crops[CCS_PAD_SINK]->width * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width; - b = crops[SMIAPP_PAD_SINK]->height + b = crops[CCS_PAD_SINK]->height * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height; - max_m = crops[SMIAPP_PAD_SINK]->width + max_m = crops[CCS_PAD_SINK]->width * CCS_LIM(sensor, SCALER_N_MIN) / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE); @@ -2071,10 +2068,10 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, for (i = 0; i < ntry; i++) { int this = scaling_goodness( subdev, - crops[SMIAPP_PAD_SINK]->width + crops[CCS_PAD_SINK]->width / try[i] * CCS_LIM(sensor, SCALER_N_MIN), sel->r.width, - crops[SMIAPP_PAD_SINK]->height, + crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags); @@ -2091,11 +2088,11 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, continue; this = scaling_goodness( - subdev, crops[SMIAPP_PAD_SINK]->width + subdev, crops[CCS_PAD_SINK]->width / try[i] * CCS_LIM(sensor, SCALER_N_MIN), sel->r.width, - crops[SMIAPP_PAD_SINK]->height + crops[CCS_PAD_SINK]->height / try[i] * CCS_LIM(sensor, SCALER_N_MIN), sel->r.height, @@ -2109,17 +2106,17 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, } sel->r.width = - (crops[SMIAPP_PAD_SINK]->width + (crops[CCS_PAD_SINK]->width / scale_m * CCS_LIM(sensor, SCALER_N_MIN)) & ~1; if (mode == SMIAPP_SCALING_MODE_BOTH) sel->r.height = - (crops[SMIAPP_PAD_SINK]->height + (crops[CCS_PAD_SINK]->height / scale_m * CCS_LIM(sensor, SCALER_N_MIN)) & ~1; else - sel->r.height = crops[SMIAPP_PAD_SINK]->height; + sel->r.height = crops[CCS_PAD_SINK]->height; if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { sensor->scale_m = scale_m; @@ -2127,57 +2124,54 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev, } } /* We're only called on source pads. This function sets scaling. */ -static int smiapp_set_compose(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) +static int ccs_set_compose(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct v4l2_rect *comp, *crops[SMIAPP_PADS]; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct v4l2_rect *comp, *crops[CCS_PADS]; - smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which); + ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which); sel->r.top = 0; sel->r.left = 0; if (ssd == sensor->binner) - smiapp_set_compose_binner(subdev, cfg, sel, crops, comp); + ccs_set_compose_binner(subdev, cfg, sel, crops, comp); else - smiapp_set_compose_scaler(subdev, cfg, sel, crops, comp); + ccs_set_compose_scaler(subdev, cfg, sel, crops, comp); *comp = sel->r; - smiapp_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE); + ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE); if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) - return smiapp_pll_blanking_update(sensor); + return ccs_pll_blanking_update(sensor); return 0; } -static int __smiapp_sel_supported(struct v4l2_subdev *subdev, - struct v4l2_subdev_selection *sel) +static int __ccs_sel_supported(struct v4l2_subdev *subdev, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); /* We only implement crop in three places. */ switch (sel->target) { case V4L2_SEL_TGT_CROP: case V4L2_SEL_TGT_CROP_BOUNDS: - if (ssd == sensor->pixel_array - && sel->pad == SMIAPP_PA_PAD_SRC) + if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC) return 0; - if (ssd == sensor->src - && sel->pad == SMIAPP_PAD_SRC) + if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) return 0; - if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK && + if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK && CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) return 0; return -EINVAL; case V4L2_SEL_TGT_NATIVE_SIZE: - if (ssd == sensor->pixel_array - && sel->pad == SMIAPP_PA_PAD_SRC) + if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC) return 0; return -EINVAL; case V4L2_SEL_TGT_COMPOSE: @@ -2195,16 +2189,16 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev, } } -static int smiapp_set_crop(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) +static int ccs_set_crop(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct v4l2_rect *src_size, *crops[SMIAPP_PADS]; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct v4l2_rect *src_size, *crops[CCS_PADS]; struct v4l2_rect _r; - smiapp_get_crop_compose(subdev, cfg, crops, NULL, sel->which); + ccs_get_crop_compose(subdev, cfg, crops, NULL, sel->which); if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { if (sel->pad == ssd->sink_pad) @@ -2226,7 +2220,7 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev, } } - if (ssd == sensor->src && sel->pad == SMIAPP_PAD_SRC) { + if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) { sel->r.left = 0; sel->r.top = 0; } @@ -2239,15 +2233,13 @@ static int smiapp_set_crop(struct v4l2_subdev *subdev, *crops[sel->pad] = sel->r; - if (ssd != sensor->pixel_array && sel->pad == SMIAPP_PAD_SINK) - smiapp_propagate(subdev, cfg, sel->which, - V4L2_SEL_TGT_CROP); + if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK) + ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_CROP); return 0; } -static void smiapp_get_native_size(struct smiapp_subdev *ssd, - struct v4l2_rect *r) +static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r) { r->top = 0; r->left = 0; @@ -2255,21 +2247,21 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd, r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1; } -static int __smiapp_get_selection(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) +static int __ccs_get_selection(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_subdev *ssd = to_smiapp_subdev(subdev); - struct v4l2_rect *comp, *crops[SMIAPP_PADS]; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_subdev *ssd = to_ccs_subdev(subdev); + struct v4l2_rect *comp, *crops[CCS_PADS]; struct v4l2_rect sink_fmt; int ret; - ret = __smiapp_sel_supported(subdev, sel); + ret = __ccs_sel_supported(subdev, sel); if (ret) return ret; - smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which); + ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which); if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { sink_fmt = ssd->sink_fmt; @@ -2287,7 +2279,7 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev, case V4L2_SEL_TGT_CROP_BOUNDS: case V4L2_SEL_TGT_NATIVE_SIZE: if (ssd == sensor->pixel_array) - smiapp_get_native_size(ssd, &sel->r); + ccs_get_native_size(ssd, &sel->r); else if (sel->pad == ssd->sink_pad) sel->r = sink_fmt; else @@ -2305,27 +2297,28 @@ static int __smiapp_get_selection(struct v4l2_subdev *subdev, return 0; } -static int smiapp_get_selection(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) +static int ccs_get_selection(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int rval; mutex_lock(&sensor->mutex); - rval = __smiapp_get_selection(subdev, cfg, sel); + rval = __ccs_get_selection(subdev, cfg, sel); mutex_unlock(&sensor->mutex); return rval; } -static int smiapp_set_selection(struct v4l2_subdev *subdev, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_selection *sel) + +static int ccs_set_selection(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int ret; - ret = __smiapp_sel_supported(subdev, sel); + ret = __ccs_sel_supported(subdev, sel); if (ret) return ret; @@ -2333,8 +2326,8 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev, sel->r.left = max(0, sel->r.left & ~1); sel->r.top = max(0, sel->r.top & ~1); - sel->r.width = SMIAPP_ALIGN_DIM(sel->r.width, sel->flags); - sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags); + sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags); + sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags); sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE), @@ -2345,10 +2338,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev, switch (sel->target) { case V4L2_SEL_TGT_CROP: - ret = smiapp_set_crop(subdev, cfg, sel); + ret = ccs_set_crop(subdev, cfg, sel); break; case V4L2_SEL_TGT_COMPOSE: - ret = smiapp_set_compose(subdev, cfg, sel); + ret = ccs_set_compose(subdev, cfg, sel); break; default: ret = -EINVAL; @@ -2358,17 +2351,17 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev, return ret; } -static int smiapp_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames) +static int ccs_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); *frames = sensor->frame_skip; return 0; } -static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines) +static int ccs_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); *lines = sensor->image_start; @@ -2380,22 +2373,22 @@ static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines) */ static ssize_t -smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr, - char *buf) +ccs_sysfs_nvm_read(struct device *dev, struct device_attribute *attr, + char *buf) { struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev)); struct i2c_client *client = v4l2_get_subdevdata(subdev); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int rval; if (!sensor->dev_init_done) return -EBUSY; - rval = smiapp_pm_get_init(sensor); + rval = ccs_pm_get_init(sensor); if (rval < 0) return -ENODEV; - rval = smiapp_read_nvm(sensor, buf, PAGE_SIZE); + rval = ccs_read_nvm(sensor, buf, PAGE_SIZE); if (rval < 0) { pm_runtime_put(&client->dev); dev_err(&client->dev, "nvm read failed\n"); @@ -2411,15 +2404,15 @@ smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr, */ return rval; } -static DEVICE_ATTR(nvm, S_IRUGO, smiapp_sysfs_nvm_read, NULL); +static DEVICE_ATTR(nvm, S_IRUGO, ccs_sysfs_nvm_read, NULL); static ssize_t -smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr, - char *buf) +ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr, + char *buf) { struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev)); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); - struct smiapp_module_info *minfo = &sensor->minfo; + struct ccs_sensor *sensor = to_ccs_sensor(subdev); + struct ccs_module_info *minfo = &sensor->minfo; if (minfo->mipi_manufacturer_id) return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n", @@ -2431,16 +2424,16 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr, minfo->revision_number_major) + 1; } -static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL); +static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL); /* ----------------------------------------------------------------------------- * V4L2 subdev core operations */ -static int smiapp_identify_module(struct smiapp_sensor *sensor) +static int ccs_identify_module(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - struct smiapp_module_info *minfo = &sensor->minfo; + struct ccs_module_info *minfo = &sensor->minfo; unsigned int i; int rval = 0; @@ -2558,34 +2551,34 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) minfo->revision_number_major = minfo->sensor_revision_number; } - for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) { - if (smiapp_module_idents[i].mipi_manufacturer_id && - smiapp_module_idents[i].mipi_manufacturer_id + for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) { + if (ccs_module_idents[i].mipi_manufacturer_id && + ccs_module_idents[i].mipi_manufacturer_id != minfo->mipi_manufacturer_id) continue; - if (smiapp_module_idents[i].smia_manufacturer_id && - smiapp_module_idents[i].smia_manufacturer_id + if (ccs_module_idents[i].smia_manufacturer_id && + ccs_module_idents[i].smia_manufacturer_id != minfo->smia_manufacturer_id) continue; - if (smiapp_module_idents[i].model_id != minfo->model_id) + if (ccs_module_idents[i].model_id != minfo->model_id) continue; - if (smiapp_module_idents[i].flags - & SMIAPP_MODULE_IDENT_FLAG_REV_LE) { - if (smiapp_module_idents[i].revision_number_major + if (ccs_module_idents[i].flags + & CCS_MODULE_IDENT_FLAG_REV_LE) { + if (ccs_module_idents[i].revision_number_major < minfo->revision_number_major) continue; } else { - if (smiapp_module_idents[i].revision_number_major + if (ccs_module_idents[i].revision_number_major != minfo->revision_number_major) continue; } - minfo->name = smiapp_module_idents[i].name; - minfo->quirk = smiapp_module_idents[i].quirk; + minfo->name = ccs_module_idents[i].name; + minfo->quirk = ccs_module_idents[i].quirk; break; } - if (i >= ARRAY_SIZE(smiapp_module_idents)) + if (i >= ARRAY_SIZE(ccs_module_idents)) dev_warn(&client->dev, "no quirks for this module; let's hope it's fully compliant\n"); @@ -2595,14 +2588,14 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor) return 0; } -static const struct v4l2_subdev_ops smiapp_ops; -static const struct v4l2_subdev_internal_ops smiapp_internal_ops; -static const struct media_entity_operations smiapp_entity_ops; +static const struct v4l2_subdev_ops ccs_ops; +static const struct v4l2_subdev_internal_ops ccs_internal_ops; +static const struct media_entity_operations ccs_entity_ops; -static int smiapp_register_subdev(struct smiapp_sensor *sensor, - struct smiapp_subdev *ssd, - struct smiapp_subdev *sink_ssd, - u16 source_pad, u16 sink_pad, u32 link_flags) +static int ccs_register_subdev(struct ccs_sensor *sensor, + struct ccs_subdev *ssd, + struct ccs_subdev *sink_ssd, + u16 source_pad, u16 sink_pad, u32 link_flags) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -2639,57 +2632,58 @@ static int smiapp_register_subdev(struct smiapp_sensor *sensor, return 0; } -static void smiapp_unregistered(struct v4l2_subdev *subdev) +static void ccs_unregistered(struct v4l2_subdev *subdev) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); unsigned int i; for (i = 1; i < sensor->ssds_used; i++) v4l2_device_unregister_subdev(&sensor->ssds[i].sd); } -static int smiapp_registered(struct v4l2_subdev *subdev) +static int ccs_registered(struct v4l2_subdev *subdev) { - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int rval; if (sensor->scaler) { - rval = smiapp_register_subdev( - sensor, sensor->binner, sensor->scaler, - SMIAPP_PAD_SRC, SMIAPP_PAD_SINK, - MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE); + rval = ccs_register_subdev(sensor, sensor->binner, + sensor->scaler, + CCS_PAD_SRC, CCS_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); if (rval < 0) return rval; } - rval = smiapp_register_subdev( - sensor, sensor->pixel_array, sensor->binner, - SMIAPP_PA_PAD_SRC, SMIAPP_PAD_SINK, - MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE); + rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner, + CCS_PA_PAD_SRC, CCS_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); if (rval) goto out_err; return 0; out_err: - smiapp_unregistered(subdev); + ccs_unregistered(subdev); return rval; } -static void smiapp_cleanup(struct smiapp_sensor *sensor) +static void ccs_cleanup(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); device_remove_file(&client->dev, &dev_attr_nvm); device_remove_file(&client->dev, &dev_attr_ident); - smiapp_free_controls(sensor); + ccs_free_controls(sensor); } -static void smiapp_create_subdev(struct smiapp_sensor *sensor, - struct smiapp_subdev *ssd, const char *name, - unsigned short num_pads) +static void ccs_create_subdev(struct ccs_sensor *sensor, + struct ccs_subdev *ssd, const char *name, + unsigned short num_pads) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -2697,7 +2691,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor, return; if (ssd != sensor->src) - v4l2_subdev_init(&ssd->sd, &smiapp_ops); + v4l2_subdev_init(&ssd->sd, &ccs_ops); ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; ssd->sensor = sensor; @@ -2707,7 +2701,7 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor, v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name); - smiapp_get_native_size(ssd, &ssd->sink_fmt); + ccs_get_native_size(ssd, &ssd->sink_fmt); ssd->compose.width = ssd->sink_fmt.width; ssd->compose.height = ssd->sink_fmt.height; @@ -2718,21 +2712,21 @@ static void smiapp_create_subdev(struct smiapp_sensor *sensor, ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK; } - ssd->sd.entity.ops = &smiapp_entity_ops; + ssd->sd.entity.ops = &ccs_entity_ops; if (ssd == sensor->src) return; - ssd->sd.internal_ops = &smiapp_internal_ops; + ssd->sd.internal_ops = &ccs_internal_ops; ssd->sd.owner = THIS_MODULE; ssd->sd.dev = &client->dev; v4l2_set_subdevdata(&ssd->sd, client); } -static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +static int ccs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { - struct smiapp_subdev *ssd = to_smiapp_subdev(sd); - struct smiapp_sensor *sensor = ssd->sensor; + struct ccs_subdev *ssd = to_ccs_subdev(sd); + struct ccs_sensor *sensor = ssd->sensor; unsigned int i; mutex_lock(&sensor->mutex); @@ -2744,7 +2738,7 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) v4l2_subdev_get_try_crop(sd, fh->pad, i); struct v4l2_rect *try_comp; - smiapp_get_native_size(ssd, try_crop); + ccs_get_native_size(ssd, try_crop); try_fmt->width = try_crop->width; try_fmt->height = try_crop->height; @@ -2763,52 +2757,52 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) return 0; } -static const struct v4l2_subdev_video_ops smiapp_video_ops = { - .s_stream = smiapp_set_stream, +static const struct v4l2_subdev_video_ops ccs_video_ops = { + .s_stream = ccs_set_stream, }; -static const struct v4l2_subdev_pad_ops smiapp_pad_ops = { - .enum_mbus_code = smiapp_enum_mbus_code, - .get_fmt = smiapp_get_format, - .set_fmt = smiapp_set_format, - .get_selection = smiapp_get_selection, - .set_selection = smiapp_set_selection, +static const struct v4l2_subdev_pad_ops ccs_pad_ops = { + .enum_mbus_code = ccs_enum_mbus_code, + .get_fmt = ccs_get_format, + .set_fmt = ccs_set_format, + .get_selection = ccs_get_selection, + .set_selection = ccs_set_selection, }; -static const struct v4l2_subdev_sensor_ops smiapp_sensor_ops = { - .g_skip_frames = smiapp_get_skip_frames, - .g_skip_top_lines = smiapp_get_skip_top_lines, +static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = { + .g_skip_frames = ccs_get_skip_frames, + .g_skip_top_lines = ccs_get_skip_top_lines, }; -static const struct v4l2_subdev_ops smiapp_ops = { - .video = &smiapp_video_ops, - .pad = &smiapp_pad_ops, - .sensor = &smiapp_sensor_ops, +static const struct v4l2_subdev_ops ccs_ops = { + .video = &ccs_video_ops, + .pad = &ccs_pad_ops, + .sensor = &ccs_sensor_ops, }; -static const struct media_entity_operations smiapp_entity_ops = { +static const struct media_entity_operations ccs_entity_ops = { .link_validate = v4l2_subdev_link_validate, }; -static const struct v4l2_subdev_internal_ops smiapp_internal_src_ops = { - .registered = smiapp_registered, - .unregistered = smiapp_unregistered, - .open = smiapp_open, +static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = { + .registered = ccs_registered, + .unregistered = ccs_unregistered, + .open = ccs_open, }; -static const struct v4l2_subdev_internal_ops smiapp_internal_ops = { - .open = smiapp_open, +static const struct v4l2_subdev_internal_ops ccs_internal_ops = { + .open = ccs_open, }; /* ----------------------------------------------------------------------------- * I2C Driver */ -static int __maybe_unused smiapp_suspend(struct device *dev) +static int __maybe_unused ccs_suspend(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *subdev = i2c_get_clientdata(client); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); bool streaming = sensor->streaming; int rval; @@ -2821,7 +2815,7 @@ static int __maybe_unused smiapp_suspend(struct device *dev) } if (sensor->streaming) - smiapp_stop_streaming(sensor); + ccs_stop_streaming(sensor); /* save state for resume */ sensor->streaming = streaming; @@ -2829,24 +2823,24 @@ static int __maybe_unused smiapp_suspend(struct device *dev) return 0; } -static int __maybe_unused smiapp_resume(struct device *dev) +static int __maybe_unused ccs_resume(struct device *dev) { struct i2c_client *client = to_i2c_client(dev); struct v4l2_subdev *subdev = i2c_get_clientdata(client); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); int rval = 0; pm_runtime_put(dev); if (sensor->streaming) - rval = smiapp_start_streaming(sensor); + rval = ccs_start_streaming(sensor); return rval; } -static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev) +static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) { - struct smiapp_hwconfig *hwcfg; + struct ccs_hwconfig *hwcfg; struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; struct fwnode_handle *ep; struct fwnode_handle *fwnode = dev_fwnode(dev); @@ -2898,7 +2892,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev) switch (rotation) { case 180: hwcfg->module_board_orient = - SMIAPP_MODULE_BOARD_ORIENT_180; + CCS_MODULE_BOARD_ORIENT_180; fallthrough; case 0: break; @@ -2942,10 +2936,10 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev) return NULL; } -static int smiapp_probe(struct i2c_client *client) +static int ccs_probe(struct i2c_client *client) { - struct smiapp_sensor *sensor; - struct smiapp_hwconfig *hwcfg = smiapp_get_hwconfig(&client->dev); + struct ccs_sensor *sensor; + struct ccs_hwconfig *hwcfg = ccs_get_hwconfig(&client->dev); unsigned int i; int rval; @@ -2959,8 +2953,8 @@ static int smiapp_probe(struct i2c_client *client) sensor->hwcfg = hwcfg; sensor->src = &sensor->ssds[sensor->ssds_used]; - v4l2_i2c_subdev_init(&sensor->src->sd, client, &smiapp_ops); - sensor->src->sd.internal_ops = &smiapp_internal_src_ops; + v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops); + sensor->src->sd.internal_ops = &ccs_internal_src_ops; sensor->vana = devm_regulator_get(&client->dev, "vana"); if (IS_ERR(sensor->vana)) { @@ -3016,13 +3010,13 @@ static int smiapp_probe(struct i2c_client *client) if (IS_ERR(sensor->xshutdown)) return PTR_ERR(sensor->xshutdown); - rval = smiapp_power_on(&client->dev); + rval = ccs_power_on(&client->dev); if (rval < 0) return rval; mutex_init(&sensor->mutex); - rval = smiapp_identify_module(sensor); + rval = ccs_identify_module(sensor); if (rval) { rval = -ENODEV; goto out_power_off; @@ -3032,7 +3026,7 @@ static int smiapp_probe(struct i2c_client *client) if (rval) goto out_power_off; - rval = smiapp_read_frame_fmt(sensor); + rval = ccs_read_frame_fmt(sensor); if (rval) { rval = -ENODEV; goto out_free_ccs_limits; @@ -3044,7 +3038,7 @@ static int smiapp_probe(struct i2c_client *client) * The application of H-FLIP and V-FLIP on the sensor is modified by * the sensor orientation on the board. * - * For SMIAPP_BOARD_SENSOR_ORIENT_180 the default behaviour is to set + * For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set * both H-FLIP and V-FLIP for normal operation which also implies * that a set/unset operation for user space HFLIP and VFLIP v4l2 * controls will need to be internally inverted. @@ -3052,12 +3046,12 @@ static int smiapp_probe(struct i2c_client *client) * Rotation also changes the bayer pattern. */ if (sensor->hwcfg->module_board_orient == - SMIAPP_MODULE_BOARD_ORIENT_180) + CCS_MODULE_BOARD_ORIENT_180) sensor->hvflip_inv_mask = CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR | CCS_IMAGE_ORIENTATION_VERTICAL_FLIP; - rval = smiapp_call_quirk(sensor, limits); + rval = ccs_call_quirk(sensor, limits); if (rval) { dev_err(&client->dev, "limits quirks failed\n"); goto out_free_ccs_limits; @@ -3136,36 +3130,36 @@ static int smiapp_probe(struct i2c_client *client) if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0) sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; - smiapp_create_subdev(sensor, sensor->scaler, " scaler", 2); - smiapp_create_subdev(sensor, sensor->binner, " binner", 2); - smiapp_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1); + ccs_create_subdev(sensor, sensor->scaler, " scaler", 2); + ccs_create_subdev(sensor, sensor->binner, " binner", 2); + ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1); dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile); sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; - rval = smiapp_init_controls(sensor); + rval = ccs_init_controls(sensor); if (rval < 0) goto out_cleanup; - rval = smiapp_call_quirk(sensor, init); + rval = ccs_call_quirk(sensor, init); if (rval) goto out_cleanup; - rval = smiapp_get_mbus_formats(sensor); + rval = ccs_get_mbus_formats(sensor); if (rval) { rval = -ENODEV; goto out_cleanup; } - rval = smiapp_init_late_controls(sensor); + rval = ccs_init_late_controls(sensor); if (rval) { rval = -ENODEV; goto out_cleanup; } mutex_lock(&sensor->mutex); - rval = smiapp_pll_blanking_update(sensor); + rval = ccs_pll_blanking_update(sensor); mutex_unlock(&sensor->mutex); if (rval) { dev_err(&client->dev, "update mode failed\n"); @@ -3202,71 +3196,71 @@ static int smiapp_probe(struct i2c_client *client) media_entity_cleanup(&sensor->src->sd.entity); out_cleanup: - smiapp_cleanup(sensor); + ccs_cleanup(sensor); out_free_ccs_limits: kfree(sensor->ccs_limits); out_power_off: - smiapp_power_off(&client->dev); + ccs_power_off(&client->dev); mutex_destroy(&sensor->mutex); return rval; } -static int smiapp_remove(struct i2c_client *client) +static int ccs_remove(struct i2c_client *client) { struct v4l2_subdev *subdev = i2c_get_clientdata(client); - struct smiapp_sensor *sensor = to_smiapp_sensor(subdev); + struct ccs_sensor *sensor = to_ccs_sensor(subdev); unsigned int i; v4l2_async_unregister_subdev(subdev); pm_runtime_disable(&client->dev); if (!pm_runtime_status_suspended(&client->dev)) - smiapp_power_off(&client->dev); + ccs_power_off(&client->dev); pm_runtime_set_suspended(&client->dev); for (i = 0; i < sensor->ssds_used; i++) { v4l2_device_unregister_subdev(&sensor->ssds[i].sd); media_entity_cleanup(&sensor->ssds[i].sd.entity); } - smiapp_cleanup(sensor); + ccs_cleanup(sensor); mutex_destroy(&sensor->mutex); kfree(sensor->ccs_limits); return 0; } -static const struct of_device_id smiapp_of_table[] = { +static const struct of_device_id ccs_of_table[] = { { .compatible = "nokia,smia" }, { }, }; -MODULE_DEVICE_TABLE(of, smiapp_of_table); +MODULE_DEVICE_TABLE(of, ccs_of_table); -static const struct i2c_device_id smiapp_id_table[] = { +static const struct i2c_device_id ccs_id_table[] = { { SMIAPP_NAME, 0 }, { }, }; -MODULE_DEVICE_TABLE(i2c, smiapp_id_table); +MODULE_DEVICE_TABLE(i2c, ccs_id_table); -static const struct dev_pm_ops smiapp_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(smiapp_suspend, smiapp_resume) - SET_RUNTIME_PM_OPS(smiapp_power_off, smiapp_power_on, NULL) +static const struct dev_pm_ops ccs_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume) + SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL) }; -static struct i2c_driver smiapp_i2c_driver = { +static struct i2c_driver ccs_i2c_driver = { .driver = { - .of_match_table = smiapp_of_table, - .name = SMIAPP_NAME, - .pm = &smiapp_pm_ops, + .of_match_table = ccs_of_table, + .name = CCS_NAME, + .pm = &ccs_pm_ops, }, - .probe_new = smiapp_probe, - .remove = smiapp_remove, - .id_table = smiapp_id_table, + .probe_new = ccs_probe, + .remove = ccs_remove, + .id_table = ccs_id_table, }; -static int smiapp_module_init(void) +static int ccs_module_init(void) { unsigned int i, l; @@ -3289,17 +3283,17 @@ static int smiapp_module_init(void) if (WARN_ON(l != CCS_L_LAST)) return -EINVAL; - return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver); + return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver); } -static void smiapp_module_cleanup(void) +static void ccs_module_cleanup(void) { - i2c_del_driver(&smiapp_i2c_driver); + i2c_del_driver(&ccs_i2c_driver); } -module_init(smiapp_module_init); -module_exit(smiapp_module_cleanup); +module_init(ccs_module_init); +module_exit(ccs_module_cleanup); MODULE_AUTHOR("Sakari Ailus "); -MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver"); +MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/ccs-quirk.c similarity index 83% rename from drivers/media/i2c/smiapp/smiapp-quirk.c rename to drivers/media/i2c/smiapp/ccs-quirk.c index 5db97a16eccf..6c48d0901952 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.c +++ b/drivers/media/i2c/smiapp/ccs-quirk.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/smiapp-quirk.c + * drivers/media/i2c/smiapp/ccs-quirk.c * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -10,12 +10,11 @@ #include +#include "ccs.h" #include "ccs-limits.h" -#include "smiapp.h" - -static int ccs_write_addr_8s(struct smiapp_sensor *sensor, - const struct smiapp_reg_8 *regs, int len) +static int ccs_write_addr_8s(struct ccs_sensor *sensor, + const struct ccs_reg_8 *regs, int len) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; @@ -33,7 +32,7 @@ static int ccs_write_addr_8s(struct smiapp_sensor *sensor, return 0; } -static int jt8ew9_limits(struct smiapp_sensor *sensor) +static int jt8ew9_limits(struct ccs_sensor *sensor) { if (sensor->minfo.revision_number_major < 0x03) sensor->frame_skip = 1; @@ -46,9 +45,9 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor) return 0; } -static int jt8ew9_post_poweron(struct smiapp_sensor *sensor) +static int jt8ew9_post_poweron(struct ccs_sensor *sensor) { - static const struct smiapp_reg_8 regs[] = { + static const struct ccs_reg_8 regs[] = { { 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */ { 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */ { 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */ @@ -84,15 +83,15 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor) return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs)); } -const struct smiapp_quirk smiapp_jt8ew9_quirk = { +const struct ccs_quirk smiapp_jt8ew9_quirk = { .limits = jt8ew9_limits, .post_poweron = jt8ew9_post_poweron, }; -static int imx125es_post_poweron(struct smiapp_sensor *sensor) +static int imx125es_post_poweron(struct ccs_sensor *sensor) { /* Taken from v02. No idea what the other two are. */ - static const struct smiapp_reg_8 regs[] = { + static const struct ccs_reg_8 regs[] = { /* * 0x3302: clk during frame blanking: * 0x00 - HS mode, 0x01 - LP11 @@ -105,11 +104,11 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor) return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs)); } -const struct smiapp_quirk smiapp_imx125es_quirk = { +const struct ccs_quirk smiapp_imx125es_quirk = { .post_poweron = imx125es_post_poweron, }; -static int jt8ev1_limits(struct smiapp_sensor *sensor) +static int jt8ev1_limits(struct ccs_sensor *sensor) { ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271); ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184); @@ -117,11 +116,11 @@ static int jt8ev1_limits(struct smiapp_sensor *sensor) return 0; } -static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) +static int jt8ev1_post_poweron(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; - static const struct smiapp_reg_8 regs[] = { + static const struct ccs_reg_8 regs[] = { { 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */ { 0x30a3, 0xd0 }, /* FLASH STROBE enable */ { 0x3237, 0x00 }, /* For control of pulse timing for ADC */ @@ -142,7 +141,7 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) { 0x33cf, 0xec }, /* For Black sun */ { 0x3328, 0x80 }, /* Ugh. No idea what's this. */ }; - static const struct smiapp_reg_8 regs_96[] = { + static const struct ccs_reg_8 regs_96[] = { { 0x30ae, 0x00 }, /* For control of ADC clock */ { 0x30af, 0xd0 }, { 0x30b0, 0x01 }, @@ -163,12 +162,12 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor) } } -static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor) +static int jt8ev1_pre_streamon(struct ccs_sensor *sensor) { return ccs_write_addr(sensor, 0x3328, 0x00); } -static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) +static int jt8ev1_post_streamoff(struct ccs_sensor *sensor) { int rval; @@ -188,14 +187,14 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor) return ccs_write_addr(sensor, 0x3328, 0x80); } -static int jt8ev1_init(struct smiapp_sensor *sensor) +static int jt8ev1_init(struct ccs_sensor *sensor) { sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE; return 0; } -const struct smiapp_quirk smiapp_jt8ev1_quirk = { +const struct ccs_quirk smiapp_jt8ev1_quirk = { .limits = jt8ev1_limits, .post_poweron = jt8ev1_post_poweron, .pre_streamon = jt8ev1_pre_streamon, @@ -203,13 +202,13 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = { .init = jt8ev1_init, }; -static int tcm8500md_limits(struct smiapp_sensor *sensor) +static int tcm8500md_limits(struct ccs_sensor *sensor) { ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000); return 0; } -const struct smiapp_quirk smiapp_tcm8500md_quirk = { +const struct ccs_quirk smiapp_tcm8500md_quirk = { .limits = tcm8500md_limits, }; diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/ccs-quirk.h similarity index 59% rename from drivers/media/i2c/smiapp/smiapp-quirk.h rename to drivers/media/i2c/smiapp/ccs-quirk.h index 8a479f17cd19..d208379158f2 100644 --- a/drivers/media/i2c/smiapp/smiapp-quirk.h +++ b/drivers/media/i2c/smiapp/ccs-quirk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * drivers/media/i2c/smiapp/smiapp-quirk.h + * drivers/media/i2c/smiapp/ccs-quirk.h * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -8,13 +8,13 @@ * Contact: Sakari Ailus */ -#ifndef __SMIAPP_QUIRK__ -#define __SMIAPP_QUIRK__ +#ifndef __CCS_QUIRK__ +#define __CCS_QUIRK__ -struct smiapp_sensor; +struct ccs_sensor; /** - * struct smiapp_quirk - quirks for sensors that deviate from SMIA++ standard + * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard * * @limits: Replace sensor->limits with values which can't be read from * sensor registers. Called the first time the sensor is powered up. @@ -36,43 +36,43 @@ struct smiapp_sensor; * access may be done by the caller (default read * value is zero), else negative error code on error */ -struct smiapp_quirk { - int (*limits)(struct smiapp_sensor *sensor); - int (*post_poweron)(struct smiapp_sensor *sensor); - int (*pre_streamon)(struct smiapp_sensor *sensor); - int (*post_streamoff)(struct smiapp_sensor *sensor); - unsigned long (*pll_flags)(struct smiapp_sensor *sensor); - int (*init)(struct smiapp_sensor *sensor); - int (*reg_access)(struct smiapp_sensor *sensor, bool write, u32 *reg, +struct ccs_quirk { + int (*limits)(struct ccs_sensor *sensor); + int (*post_poweron)(struct ccs_sensor *sensor); + int (*pre_streamon)(struct ccs_sensor *sensor); + int (*post_streamoff)(struct ccs_sensor *sensor); + unsigned long (*pll_flags)(struct ccs_sensor *sensor); + int (*init)(struct ccs_sensor *sensor); + int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg, u32 *val); unsigned long flags; }; -#define SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0) +#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0) -struct smiapp_reg_8 { +struct ccs_reg_8 { u16 reg; u8 val; }; -#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \ +#define CCS_MK_QUIRK_REG_8(_reg, _val) \ { \ .reg = (u16)_reg, \ .val = _val, \ } -#define smiapp_call_quirk(sensor, _quirk, ...) \ +#define ccs_call_quirk(sensor, _quirk, ...) \ ((sensor)->minfo.quirk && \ (sensor)->minfo.quirk->_quirk ? \ (sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0) -#define smiapp_needs_quirk(sensor, _quirk) \ +#define ccs_needs_quirk(sensor, _quirk) \ ((sensor)->minfo.quirk ? \ (sensor)->minfo.quirk->flags & _quirk : 0) -extern const struct smiapp_quirk smiapp_jt8ev1_quirk; -extern const struct smiapp_quirk smiapp_imx125es_quirk; -extern const struct smiapp_quirk smiapp_jt8ew9_quirk; -extern const struct smiapp_quirk smiapp_tcm8500md_quirk; +extern const struct ccs_quirk smiapp_jt8ev1_quirk; +extern const struct ccs_quirk smiapp_imx125es_quirk; +extern const struct ccs_quirk smiapp_jt8ew9_quirk; +extern const struct ccs_quirk smiapp_tcm8500md_quirk; -#endif /* __SMIAPP_QUIRK__ */ +#endif /* __CCS_QUIRK__ */ diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/ccs-reg-access.c similarity index 79% rename from drivers/media/i2c/smiapp/smiapp-regs.c rename to drivers/media/i2c/smiapp/ccs-reg-access.c index 173d9f8fe56c..4e6d212473fc 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.c +++ b/drivers/media/i2c/smiapp/ccs-reg-access.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/smiapp-regs.c + * drivers/media/i2c/smiapp/ccs-regs.c * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -13,8 +13,7 @@ #include #include -#include "smiapp.h" -#include "smiapp-regs.h" +#include "ccs.h" static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, uint32_t phloat) @@ -66,7 +65,7 @@ static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. */ -static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len, +static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len, u32 *val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -113,7 +112,7 @@ static int ____ccs_read_addr(struct smiapp_sensor *sensor, u16 reg, u16 len, } /* Read a register using 8-bit access only. */ -static int ____ccs_read_addr_8only(struct smiapp_sensor *sensor, u16 reg, +static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg, u16 len, u32 *val) { unsigned int i; @@ -147,7 +146,7 @@ unsigned int ccs_reg_width(u32 reg) * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. */ -static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val, +static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, bool only8) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -155,11 +154,10 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val, int rval; if (!only8) - rval = ____ccs_read_addr(sensor, SMIAPP_REG_ADDR(reg), len, - val); + rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val); else - rval = ____ccs_read_addr_8only(sensor, SMIAPP_REG_ADDR(reg), - len, val); + rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len, + val); if (rval < 0) return rval; @@ -169,21 +167,20 @@ static int __ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val, return 0; } -int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val) { return __ccs_read_addr( sensor, reg, val, - smiapp_needs_quirk(sensor, - SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY)); + ccs_needs_quirk(sensor, CCS_QUIRK_FLAG_8BIT_READ_ONLY)); } -static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, +static int ccs_read_addr_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val, bool force8) { int rval; *val = 0; - rval = smiapp_call_quirk(sensor, reg_access, false, ®, val); + rval = ccs_call_quirk(sensor, reg_access, false, ®, val); if (rval == -ENOIOCTLCMD) return 0; if (rval < 0) @@ -195,17 +192,17 @@ static int ccs_read_addr_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, return ccs_read_addr_no_quirk(sensor, reg, val); } -int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val) { return ccs_read_addr_quirk(sensor, reg, val, false); } -int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) +int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val) { return ccs_read_addr_quirk(sensor, reg, val, true); } -int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) +int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct i2c_msg msg; @@ -222,7 +219,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) msg.len = 2 + len; msg.buf = data; - put_unaligned_be16(SMIAPP_REG_ADDR(reg), data); + put_unaligned_be16(CCS_REG_ADDR(reg), data); put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2); for (retries = 0; retries < 5; retries++) { @@ -245,7 +242,7 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) dev_err(&client->dev, "wrote 0x%x to offset 0x%x error %d\n", val, - SMIAPP_REG_ADDR(reg), r); + CCS_REG_ADDR(reg), r); return r; } @@ -254,11 +251,11 @@ int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) * Write to a 8/16-bit register. * Returns zero if successful, or non-zero otherwise. */ -int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val) +int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val) { int rval; - rval = smiapp_call_quirk(sensor, reg_access, true, ®, &val); + rval = ccs_call_quirk(sensor, reg_access, true, ®, &val); if (rval == -ENOIOCTLCMD) return 0; if (rval < 0) diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/ccs-reg-access.h similarity index 55% rename from drivers/media/i2c/smiapp/smiapp-regs.h rename to drivers/media/i2c/smiapp/ccs-reg-access.h index 5df794f65dfc..76ac036a9538 100644 --- a/drivers/media/i2c/smiapp/smiapp-regs.h +++ b/drivers/media/i2c/smiapp/ccs-reg-access.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * include/media/smiapp/smiapp-regs.h + * include/media/smiapp/ccs-regs.h * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -16,15 +16,15 @@ #include "ccs-regs.h" -#define SMIAPP_REG_ADDR(reg) ((u16)reg) +#define CCS_REG_ADDR(reg) ((u16)reg) -struct smiapp_sensor; +struct ccs_sensor; -int ccs_read_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int ccs_read_addr(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int ccs_read_addr_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); -int ccs_write_addr_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); -int ccs_write_addr(struct smiapp_sensor *sensor, u32 reg, u32 val); +int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val); +int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val); +int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val); +int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val); +int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val); unsigned int ccs_reg_width(u32 reg); diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/ccs.h similarity index 65% rename from drivers/media/i2c/smiapp/smiapp.h rename to drivers/media/i2c/smiapp/ccs.h index c6e4e05a7522..20b1125d87dc 100644 --- a/drivers/media/i2c/smiapp/smiapp.h +++ b/drivers/media/i2c/smiapp/ccs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * drivers/media/i2c/smiapp/smiapp.h + * drivers/media/i2c/smiapp/ccs.h * * Generic driver for SMIA/SMIA++ compliant camera modules * @@ -8,19 +8,18 @@ * Contact: Sakari Ailus */ -#ifndef __SMIAPP_PRIV_H_ -#define __SMIAPP_PRIV_H_ +#ifndef __CCS_H__ +#define __CCS_H__ #include #include #include +#include "ccs-quirk.h" #include "ccs-regs.h" - -#include "smiapp-pll.h" +#include "ccs-reg-access.h" +#include "../smiapp-pll.h" #include "smiapp-reg-defs.h" -#include "smiapp-regs.h" -#include "smiapp-quirk.h" /* * Standard SMIA++ constants @@ -41,12 +40,13 @@ (1000 + (SMIAPP_RESET_DELAY_CLOCKS * 1000 \ + (clk) / 1000 - 1) / ((clk) / 1000)) -#define SMIAPP_COLOUR_COMPONENTS 4 +#define CCS_COLOUR_COMPONENTS 4 -#define SMIAPP_NAME "smiapp" +#define SMIAPP_NAME "smiapp" +#define CCS_NAME "ccs" -#define SMIAPP_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */ -#define SMIAPP_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */ +#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */ +#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */ /* * Sometimes due to board layout considerations the camera module can be @@ -54,12 +54,12 @@ * corrected by giving a default H-FLIP and V-FLIP in the sensor readout. * FIXME: rotation also changes the bayer pattern. */ -enum smiapp_module_board_orient { - SMIAPP_MODULE_BOARD_ORIENT_0 = 0, - SMIAPP_MODULE_BOARD_ORIENT_180, +enum ccs_module_board_orient { + CCS_MODULE_BOARD_ORIENT_0 = 0, + CCS_MODULE_BOARD_ORIENT_180, }; -struct smiapp_flash_strobe_parms { +struct ccs_flash_strobe_parms { u8 mode; u32 strobe_width_high_us; u16 strobe_delay; @@ -67,7 +67,7 @@ struct smiapp_flash_strobe_parms { u8 trigger; }; -struct smiapp_hwconfig { +struct ccs_hwconfig { /* * Change the cci address if i2c_addr_alt is set. * Both default and alternate cci addr need to be present @@ -78,19 +78,19 @@ struct smiapp_hwconfig { uint32_t ext_clk; /* sensor external clk */ unsigned int lanes; /* Number of CSI-2 lanes */ - uint32_t csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */ + uint32_t csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */ uint64_t *op_sys_clock; - enum smiapp_module_board_orient module_board_orient; + enum ccs_module_board_orient module_board_orient; - struct smiapp_flash_strobe_parms *strobe_setup; + struct ccs_flash_strobe_parms *strobe_setup; }; -struct smiapp_quirk; +struct ccs_quirk; -#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0) +#define CCS_MODULE_IDENT_FLAG_REV_LE (1 << 0) -struct smiapp_module_ident { +struct ccs_module_ident { u16 mipi_manufacturer_id; u16 model_id; u8 smia_manufacturer_id; @@ -99,10 +99,10 @@ struct smiapp_module_ident { u8 flags; char *name; - const struct smiapp_quirk *quirk; + const struct ccs_quirk *quirk; }; -struct smiapp_module_info { +struct ccs_module_info { u32 smia_manufacturer_id; u32 mipi_manufacturer_id; u32 model_id; @@ -126,10 +126,10 @@ struct smiapp_module_info { u32 smiapp_profile; char *name; - const struct smiapp_quirk *quirk; + const struct ccs_quirk *quirk; }; -#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \ +#define CCS_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \ { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ @@ -137,22 +137,22 @@ struct smiapp_module_info { .name = _name, \ .quirk = _quirk, } -#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \ +#define CCS_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \ { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ - .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \ + .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \ .name = _name, \ .quirk = _quirk, } -#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \ +#define CCS_IDENT_L(manufacturer, model, rev, _name) \ { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ - .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \ + .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \ .name = _name, } -#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \ +#define CCS_IDENT_Q(manufacturer, model, rev, _name, _quirk) \ { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ @@ -160,49 +160,49 @@ struct smiapp_module_info { .name = _name, \ .quirk = _quirk, } -#define SMIAPP_IDENT(manufacturer, model, rev, _name) \ +#define CCS_IDENT(manufacturer, model, rev, _name) \ { .smia_manufacturer_id = manufacturer, \ .model_id = model, \ .revision_number_major = rev, \ .flags = 0, \ .name = _name, } -struct smiapp_csi_data_format { +struct ccs_csi_data_format { u32 code; u8 width; u8 compressed; u8 pixel_order; }; -#define SMIAPP_SUBDEVS 3 +#define CCS_SUBDEVS 3 -#define SMIAPP_PA_PAD_SRC 0 -#define SMIAPP_PAD_SINK 0 -#define SMIAPP_PAD_SRC 1 -#define SMIAPP_PADS 2 +#define CCS_PA_PAD_SRC 0 +#define CCS_PAD_SINK 0 +#define CCS_PAD_SRC 1 +#define CCS_PADS 2 -struct smiapp_binning_subtype { +struct ccs_binning_subtype { u8 horizontal:4; u8 vertical:4; } __packed; -struct smiapp_subdev { +struct ccs_subdev { struct v4l2_subdev sd; - struct media_pad pads[SMIAPP_PADS]; + struct media_pad pads[CCS_PADS]; struct v4l2_rect sink_fmt; - struct v4l2_rect crop[SMIAPP_PADS]; + struct v4l2_rect crop[CCS_PADS]; struct v4l2_rect compose; /* compose on sink */ unsigned short sink_pad; unsigned short source_pad; int npads; - struct smiapp_sensor *sensor; + struct ccs_sensor *sensor; struct v4l2_ctrl_handler ctrl_handler; }; /* - * struct smiapp_sensor - Main device structure + * struct ccs_sensor - Main device structure */ -struct smiapp_sensor { +struct ccs_sensor { /* * "mutex" is used to serialise access to all fields here * except v4l2_ctrls at the end of the struct. "mutex" is also @@ -210,22 +210,22 @@ struct smiapp_sensor { * information. */ struct mutex mutex; - struct smiapp_subdev ssds[SMIAPP_SUBDEVS]; + struct ccs_subdev ssds[CCS_SUBDEVS]; u32 ssds_used; - struct smiapp_subdev *src; - struct smiapp_subdev *binner; - struct smiapp_subdev *scaler; - struct smiapp_subdev *pixel_array; - struct smiapp_hwconfig *hwcfg; + struct ccs_subdev *src; + struct ccs_subdev *binner; + struct ccs_subdev *scaler; + struct ccs_subdev *pixel_array; + struct ccs_hwconfig *hwcfg; struct regulator *vana; struct clk *ext_clk; struct gpio_desc *xshutdown; void *ccs_limits; u8 nbinning_subtypes; - struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1]; + struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1]; u32 mbus_frame_fmts; - const struct smiapp_csi_data_format *csi_format; - const struct smiapp_csi_data_format *internal_csi_format; + const struct ccs_csi_data_format *csi_format; + const struct ccs_csi_data_format *internal_csi_format; u32 default_mbus_frame_fmts; int default_pixel_order; @@ -246,7 +246,7 @@ struct smiapp_sensor { bool dev_init_done; u8 compressed_min_bpp; - struct smiapp_module_info minfo; + struct ccs_module_info minfo; struct smiapp_pll pll; @@ -265,16 +265,16 @@ struct smiapp_sensor { struct v4l2_ctrl *link_freq; struct v4l2_ctrl *pixel_rate_csi; /* test pattern colour components */ - struct v4l2_ctrl *test_data[SMIAPP_COLOUR_COMPONENTS]; + struct v4l2_ctrl *test_data[CCS_COLOUR_COMPONENTS]; }; -#define to_smiapp_subdev(_sd) \ - container_of(_sd, struct smiapp_subdev, sd) +#define to_ccs_subdev(_sd) \ + container_of(_sd, struct ccs_subdev, sd) -#define to_smiapp_sensor(_sd) \ - (to_smiapp_subdev(_sd)->sensor) +#define to_ccs_sensor(_sd) \ + (to_ccs_subdev(_sd)->sensor) -void ccs_replace_limit(struct smiapp_sensor *sensor, +void ccs_replace_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset, u32 val); -#endif /* __SMIAPP_PRIV_H_ */ +#endif /* __CCS_H__ */ From patchwork Wed Sep 30 15:27:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B70F618 for ; Wed, 30 Sep 2020 15:30:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 446FC221EF for ; Wed, 30 Sep 2020 15:30:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730833AbgI3PaY (ORCPT ); Wed, 30 Sep 2020 11:30:24 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730832AbgI3P3D (ORCPT ); Wed, 30 Sep 2020 11:29:03 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id BEB74634CA1 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 016/100] smiapp: Differentiate CCS sensors from SMIA in subdev naming Date: Wed, 30 Sep 2020 18:27:34 +0300 Message-Id: <20200930152858.8471-17-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Call CCS compliant sensors as "ccs" instead of "smiapp" in absence of a device specific name. This is done based on the value of the manufacturer ID register that is only present in CCS. Signed-off-by: Sakari Ailus --- drivers/media/i2c/smiapp/ccs-core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/smiapp/ccs-core.c index dd093a7d2ef4..c82e311d2661 100644 --- a/drivers/media/i2c/smiapp/ccs-core.c +++ b/drivers/media/i2c/smiapp/ccs-core.c @@ -2437,8 +2437,6 @@ static int ccs_identify_module(struct ccs_sensor *sensor) unsigned int i; int rval = 0; - minfo->name = SMIAPP_NAME; - /* Module info */ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID, &minfo->mipi_manufacturer_id); @@ -2528,15 +2526,18 @@ static int ccs_identify_module(struct ccs_sensor *sensor) "sensor revision 0x%2.2x firmware version 0x%2.2x\n", minfo->sensor_revision_number, minfo->sensor_firmware_version); - if (minfo->ccs_version) + if (minfo->ccs_version) { dev_dbg(&client->dev, "MIPI CCS version %u.%u", (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK) >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT, (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK)); - else + minfo->name = CCS_NAME; + } else { dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n", minfo->smia_version, minfo->smiapp_version); + minfo->name = SMIAPP_NAME; + } /* * Some modules have bad data in the lvalues below. Hope the From patchwork Wed Sep 30 15:27:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4177618 for ; Wed, 30 Sep 2020 15:30:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 94430221EF for ; Wed, 30 Sep 2020 15:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729434AbgI3PaV (ORCPT ); Wed, 30 Sep 2020 11:30:21 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730833AbgI3P3E (ORCPT ); Wed, 30 Sep 2020 11:29:04 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id D2D2A634CA3 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 017/100] smiapp: Rename as "ccs" Date: Wed, 30 Sep 2020 18:27:35 +0300 Message-Id: <20200930152858.8471-18-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Rename the "smiapp" driver as "ccs". MIPI CCS is the contemporary standard for raw Bayer camera sensors. The driver retains support for the SMIA++ and SMIA compliant camera sensors. A module alias is added for old user space using "smiapp" module name. Add Intel copyright while at it. Signed-off-by: Sakari Ailus --- MAINTAINERS | 20 +++++++++---------- drivers/media/i2c/Kconfig | 2 +- drivers/media/i2c/Makefile | 2 +- drivers/media/i2c/{smiapp => ccs}/Kconfig | 7 ++++--- drivers/media/i2c/{smiapp => ccs}/Makefile | 4 ++-- drivers/media/i2c/{smiapp => ccs}/ccs-core.c | 6 ++++-- .../media/i2c/{smiapp => ccs}/ccs-limits.c | 0 .../media/i2c/{smiapp => ccs}/ccs-limits.h | 0 drivers/media/i2c/{smiapp => ccs}/ccs-os.h | 0 drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c | 5 +++-- drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h | 5 +++-- .../i2c/{smiapp => ccs}/ccs-reg-access.c | 5 +++-- .../i2c/{smiapp => ccs}/ccs-reg-access.h | 5 +++-- drivers/media/i2c/{smiapp => ccs}/ccs-regs.h | 0 drivers/media/i2c/{smiapp => ccs}/ccs.h | 3 ++- .../i2c/{smiapp => ccs}/smiapp-reg-defs.h | 3 ++- 16 files changed, 38 insertions(+), 29 deletions(-) rename drivers/media/i2c/{smiapp => ccs}/Kconfig (55%) rename drivers/media/i2c/{smiapp => ccs}/Makefile (57%) rename drivers/media/i2c/{smiapp => ccs}/ccs-core.c (99%) rename drivers/media/i2c/{smiapp => ccs}/ccs-limits.c (100%) rename drivers/media/i2c/{smiapp => ccs}/ccs-limits.h (100%) rename drivers/media/i2c/{smiapp => ccs}/ccs-os.h (100%) rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.c (97%) rename drivers/media/i2c/{smiapp => ccs}/ccs-quirk.h (94%) rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.c (97%) rename drivers/media/i2c/{smiapp => ccs}/ccs-reg-access.h (86%) rename drivers/media/i2c/{smiapp => ccs}/ccs-regs.h (100%) rename drivers/media/i2c/{smiapp => ccs}/ccs.h (98%) rename drivers/media/i2c/{smiapp => ccs}/smiapp-reg-defs.h (99%) diff --git a/MAINTAINERS b/MAINTAINERS index d3126fc2cca2..06cb2c865b04 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11560,6 +11560,16 @@ M: Oliver Neukum S: Maintained F: drivers/usb/image/microtek.* +MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER +M: Sakari Ailus +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +F: drivers/media/i2c/ccs/ +F: drivers/media/i2c/smiapp-pll.c +F: drivers/media/i2c/smiapp-pll.h +F: include/uapi/linux/smiapp.h + MIPS M: Thomas Bogendoerfer L: linux-mips@vger.kernel.org @@ -15955,16 +15965,6 @@ S: Maintained F: drivers/firmware/smccc/ F: include/linux/arm-smccc.h -SMIA AND SMIA++ IMAGE SENSOR DRIVER -M: Sakari Ailus -L: linux-media@vger.kernel.org -S: Maintained -F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt -F: drivers/media/i2c/smiapp-pll.c -F: drivers/media/i2c/smiapp-pll.h -F: drivers/media/i2c/smiapp/ -F: include/uapi/linux/smiapp.h - SMM665 HARDWARE MONITOR DRIVER M: Guenter Roeck L: linux-hwmon@vger.kernel.org diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c64326ca331c..41a8b6189259 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1233,7 +1233,7 @@ config VIDEO_S5K5BAF This is a V4L2 sensor driver for Samsung S5K5BAF 2M camera sensor with an embedded SoC image signal processor. -source "drivers/media/i2c/smiapp/Kconfig" +source "drivers/media/i2c/ccs/Kconfig" source "drivers/media/i2c/et8ek8/Kconfig" config VIDEO_S5C73M3 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index f0a77473979d..cb0be09e38bd 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -2,7 +2,7 @@ msp3400-objs := msp3400-driver.o msp3400-kthreads.o obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o -obj-$(CONFIG_VIDEO_SMIAPP) += smiapp/ +obj-$(CONFIG_VIDEO_CCS) += ccs/ obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/ obj-$(CONFIG_VIDEO_CX25840) += cx25840/ obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/ diff --git a/drivers/media/i2c/smiapp/Kconfig b/drivers/media/i2c/ccs/Kconfig similarity index 55% rename from drivers/media/i2c/smiapp/Kconfig rename to drivers/media/i2c/ccs/Kconfig index 6893b532824f..b4f8b10da420 100644 --- a/drivers/media/i2c/smiapp/Kconfig +++ b/drivers/media/i2c/ccs/Kconfig @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only -config VIDEO_SMIAPP - tristate "SMIA++/SMIA sensor support" +config VIDEO_CCS + tristate "MIPI CCS/SMIA++/SMIA sensor support" depends on I2C && VIDEO_V4L2 && HAVE_CLK select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_SMIAPP_PLL select V4L2_FWNODE help - This is a generic driver for SMIA++/SMIA camera modules. + This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant + camera sensors. diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/ccs/Makefile similarity index 57% rename from drivers/media/i2c/smiapp/Makefile rename to drivers/media/i2c/ccs/Makefile index c9d300b5d2bc..08dd4e948fb0 100644 --- a/drivers/media/i2c/smiapp/Makefile +++ b/drivers/media/i2c/ccs/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -smiapp-objs += ccs-core.o ccs-reg-access.o \ +ccs-objs += ccs-core.o ccs-reg-access.o \ ccs-quirk.o ccs-limits.o -obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o +obj-$(CONFIG_VIDEO_CCS) += ccs.o ccflags-y += -I $(srctree)/drivers/media/i2c diff --git a/drivers/media/i2c/smiapp/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c similarity index 99% rename from drivers/media/i2c/smiapp/ccs-core.c rename to drivers/media/i2c/ccs/ccs-core.c index c82e311d2661..6a47a5c16bb1 100644 --- a/drivers/media/i2c/smiapp/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/ccs-core.c + * drivers/media/i2c/ccs/ccs-core.c * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2010--2012 Nokia Corporation * Contact: Sakari Ailus * @@ -3298,3 +3299,4 @@ module_exit(ccs_module_cleanup); MODULE_AUTHOR("Sakari Ailus "); MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver"); MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("smiapp"); diff --git a/drivers/media/i2c/smiapp/ccs-limits.c b/drivers/media/i2c/ccs/ccs-limits.c similarity index 100% rename from drivers/media/i2c/smiapp/ccs-limits.c rename to drivers/media/i2c/ccs/ccs-limits.c diff --git a/drivers/media/i2c/smiapp/ccs-limits.h b/drivers/media/i2c/ccs/ccs-limits.h similarity index 100% rename from drivers/media/i2c/smiapp/ccs-limits.h rename to drivers/media/i2c/ccs/ccs-limits.h diff --git a/drivers/media/i2c/smiapp/ccs-os.h b/drivers/media/i2c/ccs/ccs-os.h similarity index 100% rename from drivers/media/i2c/smiapp/ccs-os.h rename to drivers/media/i2c/ccs/ccs-os.h diff --git a/drivers/media/i2c/smiapp/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c similarity index 97% rename from drivers/media/i2c/smiapp/ccs-quirk.c rename to drivers/media/i2c/ccs/ccs-quirk.c index 6c48d0901952..5a24da1d7aa9 100644 --- a/drivers/media/i2c/smiapp/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/ccs-quirk.c + * drivers/media/i2c/ccs/ccs-quirk.c * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ diff --git a/drivers/media/i2c/smiapp/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h similarity index 94% rename from drivers/media/i2c/smiapp/ccs-quirk.h rename to drivers/media/i2c/ccs/ccs-quirk.h index d208379158f2..3e7779e2fc4b 100644 --- a/drivers/media/i2c/smiapp/ccs-quirk.h +++ b/drivers/media/i2c/ccs/ccs-quirk.h @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * drivers/media/i2c/smiapp/ccs-quirk.h + * drivers/media/i2c/ccs/ccs-quirk.h * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c similarity index 97% rename from drivers/media/i2c/smiapp/ccs-reg-access.c rename to drivers/media/i2c/ccs/ccs-reg-access.c index 4e6d212473fc..a8e9a235bfb3 100644 --- a/drivers/media/i2c/smiapp/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp/ccs-regs.c + * drivers/media/i2c/ccs/ccs-reg-access.c * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ diff --git a/drivers/media/i2c/smiapp/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h similarity index 86% rename from drivers/media/i2c/smiapp/ccs-reg-access.h rename to drivers/media/i2c/ccs/ccs-reg-access.h index 76ac036a9538..9fdf5659ed09 100644 --- a/drivers/media/i2c/smiapp/ccs-reg-access.h +++ b/drivers/media/i2c/ccs/ccs-reg-access.h @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * include/media/smiapp/ccs-regs.h + * include/media/ccs/ccs-reg-access.h * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ diff --git a/drivers/media/i2c/smiapp/ccs-regs.h b/drivers/media/i2c/ccs/ccs-regs.h similarity index 100% rename from drivers/media/i2c/smiapp/ccs-regs.h rename to drivers/media/i2c/ccs/ccs-regs.h diff --git a/drivers/media/i2c/smiapp/ccs.h b/drivers/media/i2c/ccs/ccs.h similarity index 98% rename from drivers/media/i2c/smiapp/ccs.h rename to drivers/media/i2c/ccs/ccs.h index 20b1125d87dc..7f6ed95b7b78 100644 --- a/drivers/media/i2c/smiapp/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -2,8 +2,9 @@ /* * drivers/media/i2c/smiapp/ccs.h * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2010--2012 Nokia Corporation * Contact: Sakari Ailus */ diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h similarity index 99% rename from drivers/media/i2c/smiapp/smiapp-reg-defs.h rename to drivers/media/i2c/ccs/smiapp-reg-defs.h index 06b69b1ab55f..e80c110ebf3a 100644 --- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h +++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h @@ -2,8 +2,9 @@ /* * drivers/media/i2c/smiapp/smiapp-reg-defs.h * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ From patchwork Wed Sep 30 15:27:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809639 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A053174A for ; Wed, 30 Sep 2020 15:30:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B6312311B for ; Wed, 30 Sep 2020 15:30:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731179AbgI3PaV (ORCPT ); Wed, 30 Sep 2020 11:30:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730882AbgI3P3E (ORCPT ); Wed, 30 Sep 2020 11:29:04 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC255C061755 for ; Wed, 30 Sep 2020 08:29:04 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id EBAD6634CA4 for ; Wed, 30 Sep 2020 18:28:47 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 018/100] ccs: Remove profile concept Date: Wed, 30 Sep 2020 18:27:36 +0300 Message-Id: <20200930152858.8471-19-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The driver doesn't do anything tangible with profiles. Remove the notion, and use the capabilities directly. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 23 ++++++----------------- drivers/media/i2c/ccs/ccs.h | 2 -- 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 6a47a5c16bb1..22050d33f0e8 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -377,7 +377,7 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) rval = ccs_write(sensor, REQUESTED_LINK_RATE, DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); - if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0) + if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) return rval; rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div); @@ -3096,23 +3096,17 @@ static int ccs_probe(struct i2c_client *client) } } - /* We consider this as profile 0 sensor if any of these are zero. */ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) || !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) || !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) || !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) { - sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0; + /* No OP clock branch */ + sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; } else if (CCS_LIM(sensor, SCALING_CAPABILITY) - != CCS_SCALING_CAPABILITY_NONE) { - if (CCS_LIM(sensor, SCALING_CAPABILITY) - == CCS_SCALING_CAPABILITY_HORIZONTAL) - sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1; - else - sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2; - sensor->scaler = &sensor->ssds[sensor->ssds_used]; - sensor->ssds_used++; - } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) + != CCS_SCALING_CAPABILITY_NONE || + CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) { + /* We have a scaler or digital crop. */ sensor->scaler = &sensor->ssds[sensor->ssds_used]; sensor->ssds_used++; } @@ -3128,16 +3122,11 @@ static int ccs_probe(struct i2c_client *client) sensor->pll.csi2.lanes = sensor->hwcfg->lanes; sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); - /* Profile 0 sensors have no separate OP clock branch. */ - if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0) - sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; ccs_create_subdev(sensor, sensor->scaler, " scaler", 2); ccs_create_subdev(sensor, sensor->binner, " binner", 2); ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1); - dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile); - sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; rval = ccs_init_controls(sensor); diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 7f6ed95b7b78..8933f3d40fa5 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -124,8 +124,6 @@ struct ccs_module_info { u32 smiapp_version; u32 ccs_version; - u32 smiapp_profile; - char *name; const struct ccs_quirk *quirk; }; From patchwork Wed Sep 30 15:27:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80852618 for ; Wed, 30 Sep 2020 15:30:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D3D8221EF for ; Wed, 30 Sep 2020 15:30:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731175AbgI3PaT (ORCPT ); Wed, 30 Sep 2020 11:30:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730893AbgI3P3E (ORCPT ); Wed, 30 Sep 2020 11:29:04 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDC69C0613D0 for ; Wed, 30 Sep 2020 08:29:04 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 0F633634CA5 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 019/100] ccs: Give all subdevs a function Date: Wed, 30 Sep 2020 18:27:37 +0300 Message-Id: <20200930152858.8471-20-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This removes a warning at driver probe time telling that one or two entities have no function set. The function used for both the binner and scaler is the scaler. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 22050d33f0e8..1880ed31845e 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -2685,7 +2685,7 @@ static void ccs_cleanup(struct ccs_sensor *sensor) static void ccs_create_subdev(struct ccs_sensor *sensor, struct ccs_subdev *ssd, const char *name, - unsigned short num_pads) + unsigned short num_pads, u32 function) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); @@ -2696,6 +2696,7 @@ static void ccs_create_subdev(struct ccs_sensor *sensor, v4l2_subdev_init(&ssd->sd, &ccs_ops); ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ssd->sd.entity.function = function; ssd->sensor = sensor; ssd->npads = num_pads; @@ -3123,11 +3124,12 @@ static int ccs_probe(struct i2c_client *client) sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); - ccs_create_subdev(sensor, sensor->scaler, " scaler", 2); - ccs_create_subdev(sensor, sensor->binner, " binner", 2); - ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1); - - sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ccs_create_subdev(sensor, sensor->scaler, " scaler", 2, + MEDIA_ENT_F_CAM_SENSOR); + ccs_create_subdev(sensor, sensor->binner, " binner", 2, + MEDIA_ENT_F_PROC_VIDEO_SCALER); + ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1, + MEDIA_ENT_F_PROC_VIDEO_SCALER); rval = ccs_init_controls(sensor); if (rval < 0) From patchwork Wed Sep 30 15:27:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 158A2139A for ; Wed, 30 Sep 2020 15:30:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01E422220C for ; Wed, 30 Sep 2020 15:30:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731177AbgI3PaU (ORCPT ); Wed, 30 Sep 2020 11:30:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730898AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02034C0613D1 for ; Wed, 30 Sep 2020 08:29:05 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 252E3634C87 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 020/100] dt-bindings: Add vendor prefix for MIPI Alliance Date: Wed, 30 Sep 2020 18:27:38 +0300 Message-Id: <20200930152858.8471-21-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a vendor prefix for MIPI Alliance, Inc. Signed-off-by: Sakari Ailus --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 63996ab03521..f16b53909e6e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -663,6 +663,8 @@ patternProperties: description: Miniand Tech "^minix,.*": description: MINIX Technology Ltd. + "^mipi,.*": + description: MIPI Alliance, Inc. "^miramems,.*": description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": From patchwork Wed Sep 30 15:27:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0C44618 for ; Wed, 30 Sep 2020 15:30:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC24A221EF for ; Wed, 30 Sep 2020 15:30:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731171AbgI3PaR (ORCPT ); Wed, 30 Sep 2020 11:30:17 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730876AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 379F8634C8C for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 021/100] dt-bindings: nokia,smia: Fix link-frequencies documentation Date: Wed, 30 Sep 2020 18:27:39 +0300 Message-Id: <20200930152858.8471-22-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The link-frequencies property belongs to the endpoint, not to the node representing the device. Signed-off-by: Sakari Ailus --- .../devicetree/bindings/media/i2c/nokia,smia.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt index 10ece8108081..6c45c79ef91f 100644 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt @@ -20,8 +20,6 @@ Mandatory properties dependent). - clocks: External clock to the sensor - clock-frequency: Frequency of the external clock to the sensor -- link-frequencies: List of allowed data link frequencies. An array of - 64-bit elements. Optional properties @@ -39,6 +37,8 @@ Endpoint node mandatory properties ---------------------------------- - data-lanes: <1..n> +- link-frequencies: List of allowed data link frequencies. An array of + 64-bit elements. Example @@ -55,11 +55,13 @@ Example clocks = <&omap3_isp 0>; clock-frequency = <9600000>; nokia,nvm-size = <512>; /* 8 * 64 */ - link-frequencies = /bits/ 64 <199200000 210000000 499200000>; port { smiapp_ep: endpoint { data-lanes = <1 2>; remote-endpoint = <&csi2a_ep>; + link-frequencies = + /bits/ 64 <199200000 210000000 + 499200000>; }; }; }; From patchwork Wed Sep 30 15:27:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1163618 for ; Wed, 30 Sep 2020 15:30:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 902C1221EF for ; Wed, 30 Sep 2020 15:30:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731173AbgI3PaS (ORCPT ); Wed, 30 Sep 2020 11:30:18 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730761AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 4832C634CA9 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 022/100] dt-bindings: nokia,smia: Make vana-supply optional Date: Wed, 30 Sep 2020 18:27:40 +0300 Message-Id: <20200930152858.8471-23-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org vana-supply is optional in the spec, therefore make it optional in bindings, too. Signed-off-by: Sakari Ailus --- Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt index 6c45c79ef91f..5ea4f799877b 100644 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt @@ -16,8 +16,6 @@ Mandatory properties - compatible: "nokia,smia" - reg: I2C address (0x10, or an alternative address) -- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor - dependent). - clocks: External clock to the sensor - clock-frequency: Frequency of the external clock to the sensor @@ -31,6 +29,8 @@ Optional properties - rotation: Integer property; valid values are 0 (sensor mounted upright) and 180 (sensor mounted upside down). See ../video-interfaces.txt . +- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor + dependent). Endpoint node mandatory properties From patchwork Wed Sep 30 15:27:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A7F692C for ; Wed, 30 Sep 2020 15:30:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0496722207 for ; Wed, 30 Sep 2020 15:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731174AbgI3PaT (ORCPT ); Wed, 30 Sep 2020 11:30:19 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730873AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 59F82634CAA for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 023/100] dt-bindings: nokia,smia: Convert to YAML Date: Wed, 30 Sep 2020 18:27:41 +0300 Message-Id: <20200930152858.8471-24-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Convert nokia,smia DT bindings to YAML. Also add explicit license to bindings. Signed-off-by: Sakari Ailus --- .../bindings/media/i2c/nokia,smia.txt | 68 -------- .../bindings/media/i2c/nokia,smia.yaml | 147 ++++++++++++++++++ 2 files changed, 147 insertions(+), 68 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.txt create mode 100644 Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt deleted file mode 100644 index 5ea4f799877b..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +++ /dev/null @@ -1,68 +0,0 @@ -SMIA/SMIA++ sensor - -SMIA (Standard Mobile Imaging Architecture) is an image sensor standard -defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension -of that. These definitions are valid for both types of sensors. - -More detailed documentation can be found in -Documentation/devicetree/bindings/media/video-interfaces.txt . - -The device node should contain a "port" node which may contain one or more -endpoint nodes, in accordance with video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt . - -Mandatory properties --------------------- - -- compatible: "nokia,smia" -- reg: I2C address (0x10, or an alternative address) -- clocks: External clock to the sensor -- clock-frequency: Frequency of the external clock to the sensor - - -Optional properties -------------------- - -- reset-gpios: XSHUTDOWN GPIO -- flash-leds: See ../video-interfaces.txt -- lens-focus: See ../video-interfaces.txt -- rotation: Integer property; valid values are 0 (sensor mounted upright) - and 180 (sensor mounted upside down). See - ../video-interfaces.txt . -- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor - dependent). - - -Endpoint node mandatory properties ----------------------------------- - -- data-lanes: <1..n> -- link-frequencies: List of allowed data link frequencies. An array of - 64-bit elements. - - -Example -------- - -&i2c2 { - clock-frequency = <400000>; - - camera-sensor@10 { - compatible = "nokia,smia"; - reg = <0x10>; - reset-gpios = <&gpio3 20 0>; - vana-supply = <&vaux3>; - clocks = <&omap3_isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <512>; /* 8 * 64 */ - port { - smiapp_ep: endpoint { - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - link-frequencies = - /bits/ 64 <199200000 210000000 - 499200000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml new file mode 100644 index 000000000000..3d6f68b0e559 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2014--2020 Intel Corporation + +$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMIA/SMIA++ sensor + +maintainers: + - Sakari Ailus + +description: + + SMIA (Standard Mobile Imaging Architecture) is an image sensor standard + defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of + that. These definitions are valid for both types of sensors. + + More detailed documentation can be found in + Documentation/devicetree/bindings/media/video-interfaces.txt . + +properties: + compatible: + const: nokia,smia + + reg: + maxItems: 1 + + vana-supply: + description: Analogue voltage supply (VANA), typically 2,8 volts (sensor + dependent). + maxItems: 1 + + clocks: + description: External clock to the sensor. + maxItems: 1 + + clock-frequency: + description: Frequency of the external clock to the sensor. + + reset-gpios: + description: Reset GPIO. Also commonly called XSHUTDOWN in hardware + documentation. + maxItems: 1 + + flash-leds: + description: Flash LED phandles. See ../video-interfaces.txt for details. + + lens-focus: + description: Lens focus controller phandles. See ../video-interfaces.txt + for details. + + rotation: + description: Rotation; either 0 or 180 degrees. + + port: + type: object + properties: + endpoint: + type: object + properties: + link-frequencies: + $ref: /schemas/types.yaml#/definitions/uint64-array + description: List of allowed data link frequencies. An array of + 64-bit elements. + data-lanes: + oneOf: + - items: + - const: 1 + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - const: 5 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - const: 5 + - const: 6 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - const: 5 + - const: 6 + - const: 7 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - const: 5 + - const: 6 + - const: 7 + - const: 8 + required: + - link-frequencies + - data-lanes + +required: + - compatible + - reg + - clock-frequency + - clocks + +examples: + - | + i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + + camera-sensor@10 { + compatible = "nokia,smia"; + reg = <0x10>; + reset-gpios = <&gpio3 20 0>; + vana-supply = <&vaux3>; + clocks = <&omap3_isp 0>; + clock-frequency = <9600000>; + nokia,nvm-size = <512>; /* 8 * 64 */ + port { + smiapp_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&csi2a_ep>; + link-frequencies = /bits/ 64 <199200000 210000000 + 499200000>; + }; + }; + }; + }; +... From patchwork Wed Sep 30 15:27:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 950FA92C for ; Wed, 30 Sep 2020 15:30:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 813472220C for ; Wed, 30 Sep 2020 15:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731172AbgI3PaR (ORCPT ); Wed, 30 Sep 2020 11:30:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730928AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B8ECC061755 for ; Wed, 30 Sep 2020 08:29:05 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 72633634CBD for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 024/100] dt-bindings: nokia,smia: Use better active polarity for reset Date: Wed, 30 Sep 2020 18:27:42 +0300 Message-Id: <20200930152858.8471-25-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Generally reset signal is active low on camera sensors. The example had it high. Make it low, and use GPIO_ACTIVE_LOW in gpio.h for that. Signed-off-by: Sakari Ailus --- Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml index 3d6f68b0e559..d7de07e99008 100644 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml +++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml @@ -120,6 +120,8 @@ required: examples: - | + #include + i2c2 { #address-cells = <1>; #size-cells = <0>; @@ -129,7 +131,7 @@ examples: camera-sensor@10 { compatible = "nokia,smia"; reg = <0x10>; - reset-gpios = <&gpio3 20 0>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; vana-supply = <&vaux3>; clocks = <&omap3_isp 0>; clock-frequency = <9600000>; From patchwork Wed Sep 30 15:27:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1ABD992C for ; Wed, 30 Sep 2020 15:30:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06CF9221EC for ; Wed, 30 Sep 2020 15:30:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731160AbgI3PaM (ORCPT ); Wed, 30 Sep 2020 11:30:12 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729343AbgI3P3G (ORCPT ); Wed, 30 Sep 2020 11:29:06 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 867F8634CBE for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 025/100] dt-bindings: Amend SMIA bindings with MIPI CCS support Date: Wed, 30 Sep 2020 18:27:43 +0300 Message-Id: <20200930152858.8471-26-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Amend the existing SMIA bindings by adding MIPI CCS support. Besides the compatible string, two new regulator supplies are added. Rename the old bindings accordingly as CCS is the current standard. Signed-off-by: Sakari Ailus --- .../i2c/{nokia,smia.yaml => mipi,ccs.yaml} | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/media/i2c/{nokia,smia.yaml => mipi,ccs.yaml} (89%) diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml b/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml similarity index 89% rename from Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml rename to Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml index d7de07e99008..6ac01ec8610c 100644 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.yaml +++ b/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml @@ -1,26 +1,32 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (C) 2014--2020 Intel Corporation -$id: http://devicetree.org/schemas/media/i2c/nokia,smia.yaml# +$id: http://devicetree.org/schemas/media/i2c/mipi,ccs.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SMIA/SMIA++ sensor +title: MIPI CCS, SMIA++ and SMIA compliant camera sensors maintainers: - Sakari Ailus description: + CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the + MIPI Alliance; see + . + SMIA (Standard Mobile Imaging Architecture) is an image sensor standard defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of - that. These definitions are valid for both types of sensors. + that. More detailed documentation can be found in Documentation/devicetree/bindings/media/video-interfaces.txt . properties: compatible: - const: nokia,smia + oneOf: + - const: mipi,ccs + - const: nokia,smia reg: maxItems: 1 @@ -129,7 +135,7 @@ examples: clock-frequency = <400000>; camera-sensor@10 { - compatible = "nokia,smia"; + compatible = "mipi,ccs"; reg = <0x10>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; vana-supply = <&vaux3>; @@ -137,7 +143,7 @@ examples: clock-frequency = <9600000>; nokia,nvm-size = <512>; /* 8 * 64 */ port { - smiapp_ep: endpoint { + ccs_ep: endpoint { data-lanes = <1 2>; remote-endpoint = <&csi2a_ep>; link-frequencies = /bits/ 64 <199200000 210000000 From patchwork Wed Sep 30 15:27:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 370B7139A for ; Wed, 30 Sep 2020 15:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 233BB2311C for ; Wed, 30 Sep 2020 15:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731162AbgI3PaO (ORCPT ); Wed, 30 Sep 2020 11:30:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730944AbgI3P3G (ORCPT ); Wed, 30 Sep 2020 11:29:06 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A72ECC061755 for ; Wed, 30 Sep 2020 08:29:06 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 9C00E634C8D for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 026/100] dt-bindings: Add bus-type for C-PHY support Date: Wed, 30 Sep 2020 18:27:44 +0300 Message-Id: <20200930152858.8471-27-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org C-PHY is required Signed-off-by: Sakari Ailus --- .../devicetree/bindings/media/i2c/mipi,ccs.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml index 6ac01ec8610c..b7908f6e48b9 100644 --- a/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml +++ b/Documentation/devicetree/bindings/media/i2c/mipi,ccs.yaml @@ -114,6 +114,14 @@ properties: - const: 6 - const: 7 - const: 8 + bus-type: + description: The type of the data bus. + oneOf: + - const: 1 # CSI-2 C-PHY + - const: 2 # CSI-1 + - const: 3 # CCP2 + - const: 4 # CSI-2 D-PHY + required: - link-frequencies - data-lanes @@ -148,6 +156,7 @@ examples: remote-endpoint = <&csi2a_ep>; link-frequencies = /bits/ 64 <199200000 210000000 499200000>; + bus-type = <4>; }; }; }; From patchwork Wed Sep 30 15:27:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 088C7618 for ; Wed, 30 Sep 2020 15:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E89902311C for ; Wed, 30 Sep 2020 15:30:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731164AbgI3PaO (ORCPT ); Wed, 30 Sep 2020 11:30:14 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730915AbgI3P3G (ORCPT ); Wed, 30 Sep 2020 11:29:06 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id ACE35634C89 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 027/100] ccs: Request for "reset" GPIO Date: Wed, 30 Sep 2020 18:27:45 +0300 Message-Id: <20200930152858.8471-28-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The DT bindings documented "reset-gpios" property but the driver never made use of it. Instead it used a GPIO called "xshutdown", with apprently wrong polarity. Fix this by requesting "reset" GPIO with the right polarity first, and if that fails, then request "xshutdown" GPIO with the old polarity. This way it works for new users as expected while if someone, somewhere, depended on "xshutdown" GPIO, that continues to work as well. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 14 ++++++++++++-- drivers/media/i2c/ccs/ccs.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 1880ed31845e..775037ce361f 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1295,6 +1295,7 @@ static int ccs_power_on(struct device *dev) } usleep_range(1000, 1000); + gpiod_set_value(sensor->reset, 0); gpiod_set_value(sensor->xshutdown, 1); sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk); @@ -1381,6 +1382,7 @@ static int ccs_power_on(struct device *dev) return 0; out_cci_addr_fail: + gpiod_set_value(sensor->reset, 1); gpiod_set_value(sensor->xshutdown, 0); clk_disable_unprepare(sensor->ext_clk); @@ -1407,6 +1409,7 @@ static int ccs_power_off(struct device *dev) if (sensor->hwcfg->i2c_addr_alt) ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); + gpiod_set_value(sensor->reset, 1); gpiod_set_value(sensor->xshutdown, 0); clk_disable_unprepare(sensor->ext_clk); usleep_range(5000, 5000); @@ -3008,8 +3011,15 @@ static int ccs_probe(struct i2c_client *client) return -EINVAL; } - sensor->xshutdown = devm_gpiod_get_optional(&client->dev, "xshutdown", - GPIOD_OUT_LOW); + sensor->reset = devm_gpiod_get_optional(&client->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->reset)) + return PTR_ERR(sensor->reset); + /* Support old users that may have used "xshutdown" property. */ + if (!sensor->reset) + sensor->xshutdown = devm_gpiod_get_optional(&client->dev, + "xshutdown", + GPIOD_OUT_LOW); if (IS_ERR(sensor->xshutdown)) return PTR_ERR(sensor->xshutdown); diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 8933f3d40fa5..bfe39e02f5e9 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -219,6 +219,7 @@ struct ccs_sensor { struct regulator *vana; struct clk *ext_clk; struct gpio_desc *xshutdown; + struct gpio_desc *reset; void *ccs_limits; u8 nbinning_subtypes; struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1]; From patchwork Wed Sep 30 15:27:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B05192C for ; Wed, 30 Sep 2020 15:30:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A27722207 for ; Wed, 30 Sep 2020 15:30:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731168AbgI3PaQ (ORCPT ); Wed, 30 Sep 2020 11:30:16 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730904AbgI3P3F (ORCPT ); Wed, 30 Sep 2020 11:29:05 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id BDC52634CBF for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 028/100] ccs: Add "mipi,ccs" compatible string Date: Wed, 30 Sep 2020 18:27:46 +0300 Message-Id: <20200930152858.8471-29-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add "mipi,ccs" compatible string to the CCS driver. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 775037ce361f..7cdd81e3bb6e 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3237,6 +3237,7 @@ static int ccs_remove(struct i2c_client *client) static const struct of_device_id ccs_of_table[] = { { .compatible = "nokia,smia" }, + { .compatible = "mipi,ccs" }, { }, }; MODULE_DEVICE_TABLE(of, ccs_of_table); From patchwork Wed Sep 30 15:27:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2F60618 for ; Wed, 30 Sep 2020 15:30:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A08972220C for ; Wed, 30 Sep 2020 15:30:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730965AbgI3PaN (ORCPT ); Wed, 30 Sep 2020 11:30:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730966AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF773C0613D0 for ; Wed, 30 Sep 2020 08:29:06 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id D0C83634CC0 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 029/100] =?utf-8?q?ccs=3A_Remove_the_I=C2=B2C_ID_table?= Date: Wed, 30 Sep 2020 18:27:47 +0300 Message-Id: <20200930152858.8471-30-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The I²C ID table is no longer needed; remove it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 7cdd81e3bb6e..ddcdd7098a1f 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3242,12 +3242,6 @@ static const struct of_device_id ccs_of_table[] = { }; MODULE_DEVICE_TABLE(of, ccs_of_table); -static const struct i2c_device_id ccs_id_table[] = { - { SMIAPP_NAME, 0 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, ccs_id_table); - static const struct dev_pm_ops ccs_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume) SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL) @@ -3261,7 +3255,6 @@ static struct i2c_driver ccs_i2c_driver = { }, .probe_new = ccs_probe, .remove = ccs_remove, - .id_table = ccs_id_table, }; static int ccs_module_init(void) From patchwork Wed Sep 30 15:27:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 944FB92C for ; Wed, 30 Sep 2020 15:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FD7C2311A for ; Wed, 30 Sep 2020 15:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731166AbgI3PaP (ORCPT ); Wed, 30 Sep 2020 11:30:15 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730923AbgI3P3G (ORCPT ); Wed, 30 Sep 2020 11:29:06 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id E260E634CC1 for ; Wed, 30 Sep 2020 18:28:48 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 030/100] ccs: Remove remaining support for platform data Date: Wed, 30 Sep 2020 18:27:48 +0300 Message-Id: <20200930152858.8471-31-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org No need to support platform data; remove support for conveying hardware configuration that way. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index ddcdd7098a1f..610a2d22a5ca 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -2854,9 +2854,6 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) int i; int rval; - if (!fwnode) - return dev->platform_data; - ep = fwnode_graph_get_next_endpoint(fwnode, NULL); if (!ep) return NULL; From patchwork Wed Sep 30 15:27:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77BDC618 for ; Wed, 30 Sep 2020 15:30:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A88C221E7 for ; Wed, 30 Sep 2020 15:30:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731154AbgI3PaK (ORCPT ); Wed, 30 Sep 2020 11:30:10 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730949AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 0C7AD634CCA for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 031/100] ccs: Make hwcfg part of the device specific struct Date: Wed, 30 Sep 2020 18:27:49 +0300 Message-Id: <20200930152858.8471-32-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org There's no need to allocate the hardware configuration struct separately. Put it in struct ccs_sensor. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 94 ++++++++++++++++--------------- drivers/media/i2c/ccs/ccs-quirk.c | 4 +- drivers/media/i2c/ccs/ccs.h | 2 +- 3 files changed, 51 insertions(+), 49 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 610a2d22a5ca..d8553aba00c8 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -803,7 +803,7 @@ static int ccs_init_late_controls(struct ccs_sensor *sensor) sensor->link_freq = v4l2_ctrl_new_int_menu( &sensor->src->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs), - __ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock); + __ffs(*valid_link_freqs), sensor->hwcfg.op_sys_clock); return sensor->src->ctrl_handler.error; } @@ -916,8 +916,8 @@ static int ccs_get_mbus_formats(struct ccs_sensor *sensor) pll->bits_per_pixel = f->compressed; - for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) { - pll->link_freq = sensor->hwcfg->op_sys_clock[j]; + for (j = 0; sensor->hwcfg.op_sys_clock[j]; j++) { + pll->link_freq = sensor->hwcfg.op_sys_clock[j]; rval = ccs_pll_try(sensor, pll); dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n", @@ -1117,21 +1117,21 @@ static int ccs_change_cci_addr(struct ccs_sensor *sensor) int rval; u32 val; - client->addr = sensor->hwcfg->i2c_addr_dfl; + client->addr = sensor->hwcfg.i2c_addr_dfl; rval = ccs_write(sensor, CCI_ADDRESS_CTRL, - sensor->hwcfg->i2c_addr_alt << 1); + sensor->hwcfg.i2c_addr_alt << 1); if (rval) return rval; - client->addr = sensor->hwcfg->i2c_addr_alt; + client->addr = sensor->hwcfg.i2c_addr_alt; /* verify addr change went ok */ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val); if (rval) return rval; - if (val != sensor->hwcfg->i2c_addr_alt << 1) + if (val != sensor->hwcfg.i2c_addr_alt << 1) return -ENODEV; return 0; @@ -1145,13 +1145,13 @@ static int ccs_change_cci_addr(struct ccs_sensor *sensor) static int ccs_setup_flash_strobe(struct ccs_sensor *sensor) { struct ccs_flash_strobe_parms *strobe_setup; - unsigned int ext_freq = sensor->hwcfg->ext_clk; + unsigned int ext_freq = sensor->hwcfg.ext_clk; u32 tmp; u32 strobe_adjustment; u32 strobe_width_high_rs; int rval; - strobe_setup = sensor->hwcfg->strobe_setup; + strobe_setup = sensor->hwcfg.strobe_setup; /* * How to calculate registers related to strobe length. Please @@ -1259,7 +1259,7 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor) rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger); out: - sensor->hwcfg->strobe_setup->trigger = 0; + sensor->hwcfg.strobe_setup->trigger = 0; return rval; } @@ -1298,7 +1298,7 @@ static int ccs_power_on(struct device *dev) gpiod_set_value(sensor->reset, 0); gpiod_set_value(sensor->xshutdown, 1); - sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk); + sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk); usleep_range(sleep, sleep); /* @@ -1312,7 +1312,7 @@ static int ccs_power_on(struct device *dev) * is found. */ - if (sensor->hwcfg->i2c_addr_alt) { + if (sensor->hwcfg.i2c_addr_alt) { rval = ccs_change_cci_addr(sensor); if (rval) { dev_err(dev, "cci address change error\n"); @@ -1326,7 +1326,7 @@ static int ccs_power_on(struct device *dev) goto out_cci_addr_fail; } - if (sensor->hwcfg->i2c_addr_alt) { + if (sensor->hwcfg.i2c_addr_alt) { rval = ccs_change_cci_addr(sensor); if (rval) { dev_err(dev, "cci address change error\n"); @@ -1342,13 +1342,13 @@ static int ccs_power_on(struct device *dev) } rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ, - sensor->hwcfg->ext_clk / (1000000 / (1 << 8))); + sensor->hwcfg.ext_clk / (1000000 / (1 << 8))); if (rval) { dev_err(dev, "extclk frequency set failed\n"); goto out_cci_addr_fail; } - rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1); + rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1); if (rval) { dev_err(dev, "csi lane mode set failed\n"); goto out_cci_addr_fail; @@ -1362,7 +1362,7 @@ static int ccs_power_on(struct device *dev) } rval = ccs_write(sensor, CSI_SIGNALING_MODE, - sensor->hwcfg->csi_signalling_mode); + sensor->hwcfg.csi_signalling_mode); if (rval) { dev_err(dev, "csi signalling mode set failed\n"); goto out_cci_addr_fail; @@ -1406,7 +1406,7 @@ static int ccs_power_off(struct device *dev) * really see a power off and next time the cci address change * will fail. So do a soft reset explicitly here. */ - if (sensor->hwcfg->i2c_addr_alt) + if (sensor->hwcfg.i2c_addr_alt) ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); gpiod_set_value(sensor->reset, 1); @@ -1545,8 +1545,8 @@ static int ccs_start_streaming(struct ccs_sensor *sensor) if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) & (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE | SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) && - sensor->hwcfg->strobe_setup != NULL && - sensor->hwcfg->strobe_setup->trigger != 0) { + sensor->hwcfg.strobe_setup != NULL && + sensor->hwcfg.strobe_setup->trigger != 0) { rval = ccs_setup_flash_strobe(sensor); if (rval) goto out; @@ -2844,9 +2844,9 @@ static int __maybe_unused ccs_resume(struct device *dev) return rval; } -static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) +static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev) { - struct ccs_hwconfig *hwcfg; + struct ccs_hwconfig *hwcfg = &sensor->hwcfg; struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; struct fwnode_handle *ep; struct fwnode_handle *fwnode = dev_fwnode(dev); @@ -2856,7 +2856,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) ep = fwnode_graph_get_next_endpoint(fwnode, NULL); if (!ep) - return NULL; + return -ENODEV; bus_cfg.bus_type = V4L2_MBUS_CSI2_DPHY; rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); @@ -2868,10 +2868,6 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) if (rval) goto out_err; - hwcfg = devm_kzalloc(dev, sizeof(*hwcfg), GFP_KERNEL); - if (!hwcfg) - goto out_err; - switch (bus_cfg.bus_type) { case V4L2_MBUS_CSI2_DPHY: hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY; @@ -2885,6 +2881,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) break; default: dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type); + rval = -EINVAL; goto out_err; } @@ -2901,6 +2898,7 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) break; default: dev_err(dev, "invalid rotation %u\n", rotation); + rval = -EINVAL; goto out_err; } } @@ -2915,14 +2913,17 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) if (!bus_cfg.nr_of_link_frequencies) { dev_warn(dev, "no link frequencies defined\n"); + rval = -EINVAL; goto out_err; } hwcfg->op_sys_clock = devm_kcalloc( dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */, sizeof(*hwcfg->op_sys_clock), GFP_KERNEL); - if (!hwcfg->op_sys_clock) + if (!hwcfg->op_sys_clock) { + rval = -ENOMEM; goto out_err; + } for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i]; @@ -2931,29 +2932,30 @@ static struct ccs_hwconfig *ccs_get_hwconfig(struct device *dev) v4l2_fwnode_endpoint_free(&bus_cfg); fwnode_handle_put(ep); - return hwcfg; + + return 0; out_err: v4l2_fwnode_endpoint_free(&bus_cfg); fwnode_handle_put(ep); - return NULL; + + return rval; } static int ccs_probe(struct i2c_client *client) { struct ccs_sensor *sensor; - struct ccs_hwconfig *hwcfg = ccs_get_hwconfig(&client->dev); unsigned int i; int rval; - if (hwcfg == NULL) - return -ENODEV; - sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); if (sensor == NULL) return -ENOMEM; - sensor->hwcfg = hwcfg; + rval = ccs_get_hwconfig(sensor, &client->dev); + if (rval) + return rval; + sensor->src = &sensor->ssds[sensor->ssds_used]; v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops); @@ -2976,33 +2978,33 @@ static int ccs_probe(struct i2c_client *client) } if (sensor->ext_clk) { - if (sensor->hwcfg->ext_clk) { + if (sensor->hwcfg.ext_clk) { unsigned long rate; rval = clk_set_rate(sensor->ext_clk, - sensor->hwcfg->ext_clk); + sensor->hwcfg.ext_clk); if (rval < 0) { dev_err(&client->dev, "unable to set clock freq to %u\n", - sensor->hwcfg->ext_clk); + sensor->hwcfg.ext_clk); return rval; } rate = clk_get_rate(sensor->ext_clk); - if (rate != sensor->hwcfg->ext_clk) { + if (rate != sensor->hwcfg.ext_clk) { dev_err(&client->dev, "can't set clock freq, asked for %u but got %lu\n", - sensor->hwcfg->ext_clk, rate); + sensor->hwcfg.ext_clk, rate); return rval; } } else { - sensor->hwcfg->ext_clk = clk_get_rate(sensor->ext_clk); + sensor->hwcfg.ext_clk = clk_get_rate(sensor->ext_clk); dev_dbg(&client->dev, "obtained clock freq %u\n", - sensor->hwcfg->ext_clk); + sensor->hwcfg.ext_clk); } - } else if (sensor->hwcfg->ext_clk) { + } else if (sensor->hwcfg.ext_clk) { dev_dbg(&client->dev, "assuming clock freq %u\n", - sensor->hwcfg->ext_clk); + sensor->hwcfg.ext_clk); } else { dev_err(&client->dev, "unable to obtain clock freq\n"); return -EINVAL; @@ -3055,7 +3057,7 @@ static int ccs_probe(struct i2c_client *client) * * Rotation also changes the bayer pattern. */ - if (sensor->hwcfg->module_board_orient == + if (sensor->hwcfg.module_board_orient == CCS_MODULE_BOARD_ORIENT_180) sensor->hvflip_inv_mask = CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR | @@ -3127,8 +3129,8 @@ static int ccs_probe(struct i2c_client *client) /* prepare PLL configuration input values */ sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2; - sensor->pll.csi2.lanes = sensor->hwcfg->lanes; - sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk; + sensor->pll.csi2.lanes = sensor->hwcfg.lanes; + sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); ccs_create_subdev(sensor, sensor->scaler, " scaler", 2, diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index 5a24da1d7aa9..facec28f8447 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -152,13 +152,13 @@ static int jt8ev1_post_poweron(struct ccs_sensor *sensor) if (rval < 0) return rval; - switch (sensor->hwcfg->ext_clk) { + switch (sensor->hwcfg.ext_clk) { case 9600000: return ccs_write_addr_8s(sensor, regs_96, ARRAY_SIZE(regs_96)); default: dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n", - sensor->hwcfg->ext_clk); + sensor->hwcfg.ext_clk); return 0; } } diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index bfe39e02f5e9..2d1e8339f663 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -215,7 +215,7 @@ struct ccs_sensor { struct ccs_subdev *binner; struct ccs_subdev *scaler; struct ccs_subdev *pixel_array; - struct ccs_hwconfig *hwcfg; + struct ccs_hwconfig hwcfg; struct regulator *vana; struct clk *ext_clk; struct gpio_desc *xshutdown; From patchwork Wed Sep 30 15:27:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809611 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 941A992C for ; Wed, 30 Sep 2020 15:30:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BBB421D7F for ; Wed, 30 Sep 2020 15:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731155AbgI3PaL (ORCPT ); Wed, 30 Sep 2020 11:30:11 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730962AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 30C33634C8E for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 032/100] ccs: Add CCS static data parser library Date: Wed, 30 Sep 2020 18:27:50 +0300 Message-Id: <20200930152858.8471-33-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a parser library for parsing the CCS static data format. The library may be also compiled in user space as the format has uses also in the user space. Therefore it is dual licensed under the 3-clause BSD license as well. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/Makefile | 2 +- drivers/media/i2c/ccs/ccs-data-defs.h | 215 ++++++ drivers/media/i2c/ccs/ccs-data.c | 949 ++++++++++++++++++++++++++ drivers/media/i2c/ccs/ccs-data.h | 116 ++++ 4 files changed, 1281 insertions(+), 1 deletion(-) create mode 100644 drivers/media/i2c/ccs/ccs-data-defs.h create mode 100644 drivers/media/i2c/ccs/ccs-data.c create mode 100644 drivers/media/i2c/ccs/ccs-data.h diff --git a/drivers/media/i2c/ccs/Makefile b/drivers/media/i2c/ccs/Makefile index 08dd4e948fb0..44601ba8cd53 100644 --- a/drivers/media/i2c/ccs/Makefile +++ b/drivers/media/i2c/ccs/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only ccs-objs += ccs-core.o ccs-reg-access.o \ - ccs-quirk.o ccs-limits.o + ccs-quirk.o ccs-limits.o ccs-data.o obj-$(CONFIG_VIDEO_CCS) += ccs.o ccflags-y += -I $(srctree)/drivers/media/i2c diff --git a/drivers/media/i2c/ccs/ccs-data-defs.h b/drivers/media/i2c/ccs/ccs-data-defs.h new file mode 100644 index 000000000000..ffc5154d2c66 --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-data-defs.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* Copyright 2019--2020 Intel Corporation */ + +#ifndef __CCS_DATA_DEFS_H__ +#define __CCS_DATA_DEFS_H__ + +#include "ccs-data.h" + +#define CCS_STATIC_DATA_VERSION 0 + +enum __ccs_data_length_specifier_id { + CCS_DATA_LENGTH_SPECIFIER_1 = 0, + CCS_DATA_LENGTH_SPECIFIER_2 = 1, + CCS_DATA_LENGTH_SPECIFIER_3 = 2 +}; +#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6 + +struct __ccs_data_length_specifier { + uint8_t length; +} __attribute__((packed)); + +struct __ccs_data_length_specifier2 { + uint8_t length[2]; +} __attribute__((packed)); + +struct __ccs_data_length_specifier3 { + uint8_t length[3]; +} __attribute__((packed)); + +struct __ccs_data_block { + uint8_t id; + struct __ccs_data_length_specifier length; +} __attribute__((packed)); + +#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5 + +struct __ccs_data_block3 { + uint8_t id; + struct __ccs_data_length_specifier2 length; +} __attribute__((packed)); + +struct __ccs_data_block4 { + uint8_t id; + struct __ccs_data_length_specifier3 length; +} __attribute__((packed)); + +enum __ccs_data_block_id { + CCS_DATA_BLOCK_ID_DUMMY = 1, + CCS_DATA_BLOCK_ID_DATA_VERSION = 2, + CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3, + CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4, + CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5, + CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6, + CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32, + CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33, + CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36, + CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37, + CCS_DATA_BLOCK_ID_LICENSE = 40, + CCS_DATA_BLOCK_ID_END = 127, +}; + +struct __ccs_data_block_version { + uint8_t static_data_version_major[2]; + uint8_t static_data_version_minor[2]; + uint8_t year[2]; + uint8_t month; + uint8_t day; +} __attribute__((packed)); + +struct __ccs_data_block_regs { + uint8_t reg_len; +} __attribute__((packed)); + +#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07 +#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3 +#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38 +#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6 +enum ccs_data_block_regs_sel { + CCS_DATA_BLOCK_REGS_SEL_REGS = 0, + CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1, + CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2, +}; + +struct __ccs_data_block_regs2 { + uint8_t reg_len; + uint8_t addr; +} __attribute__((packed)); + +#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01 +#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1 +#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e + +struct __ccs_data_block_regs3 { + uint8_t reg_len; + uint8_t addr[2]; +} __attribute__((packed)); + +#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f + +enum __ccs_data_ffd_pixelcode { + CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1, + CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2, + CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3, + CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4, + CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13, + CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17, + CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18, + CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33, + CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34, + CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36, + CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38, + CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39, + CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40, + CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41, + CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41, +}; + +struct __ccs_data_block_ffd_entry { + uint8_t pixelcode; + uint8_t reserved; + uint8_t value[2]; +} __attribute__((packed)); + +struct __ccs_data_block_ffd { + uint8_t num_column_descs; + uint8_t num_row_descs; +} __attribute__((packed)); + +enum __ccs_data_block_rule_id { + CCS_DATA_BLOCK_RULE_ID_IF = 1, + CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2, + CCS_DATA_BLOCK_RULE_ID_FFD = 3, + CCS_DATA_BLOCK_RULE_ID_MSR = 4, + CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5, +}; + +struct __ccs_data_block_rule_if { + uint8_t addr[2]; + uint8_t value; + uint8_t mask; +} __attribute__((packed)); + +enum __ccs_data_block_pdaf_readout_order{ + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1, + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2, + CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3, +}; + +struct __ccs_data_block_pdaf_readout { + uint8_t pdaf_readout_info_reserved; + uint8_t pdaf_readout_info_order; +} __attribute__((packed)); + +struct __ccs_data_block_pdaf_pix_loc_block_desc { + uint8_t block_type_id; + uint8_t repeat_x[2]; +} __attribute__((packed)); + +struct __ccs_data_block_pdaf_pix_loc_block_desc_group { + uint8_t num_block_descs[2]; + uint8_t repeat_y; +} __attribute__((packed)); + +enum __ccs_data_block_pdaf_pix_loc_pixel_type { + CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0, + CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1, + CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2, + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3, + CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4, + CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5, + CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6, + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7, + CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8, + CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9, + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10, + CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11, +}; + +struct __ccs_data_block_pdaf_pix_loc_pixel_desc { + uint8_t pixel_type; + uint8_t small_offset_x; + uint8_t small_offset_y; +} __attribute__((packed)); + +struct __ccs_data_block_pdaf_pix_loc { + uint8_t main_offset_x[2]; + uint8_t main_offset_y[2]; + uint8_t global_pdaf_type; + uint8_t block_width; + uint8_t block_height; + uint8_t num_block_desc_groups[2]; +} __attribute__((packed)); + +struct __ccs_data_block_end { + uint8_t crc[4]; +} __attribute__((packed)); + +#endif /* __CCS_DATA_DEFS_H__ */ diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c new file mode 100644 index 000000000000..16aeeee45936 --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-data.c @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* Copyright 2019--2020 Intel Corporation */ + +#include "ccs-os.h" + +#include "ccs-data-defs.h" + +struct bin_container { + void *base; + void *now; + void *end; + size_t size; +}; + +static uint32_t u8_arr_to_u32(const uint8_t *arr, unsigned int size) +{ + unsigned int i; + uint32_t value = arr[0]; + + for (i = 1; i < size; i++) { + value <<= 8; + value += arr[i]; + } + + return value; +} + +static void *bin_alloc(struct bin_container *bin, size_t len) +{ + void *ptr; + + len = align2(len, 8); + + if (bin->end - bin->now < len) + return NULL; + + ptr = bin->now; + bin->now += len; + + return ptr; +} + +static void bin_reserve(struct bin_container *bin, size_t len) +{ + bin->size += align2(len, 8); +} + +static int bin_backing_alloc(struct bin_container *bin) +{ + bin->base = bin->now = os_calloc(bin->size); + if (!bin->base) + return -ENOMEM; + + bin->end = bin->base + bin->size; + + return 0; +} + +#define is_contained(var, endp) \ + (sizeof(*var) <= (endp) - (void *)(var)) +#define has_headroom(ptr, headroom, endp) \ + ((headroom) <= (endp) - (void *)(ptr)) +#define is_contained_with_headroom(var, headroom, endp) \ + (sizeof(*var) + (headroom) <= (endp) - (void *)(var)) + +static int +ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len, + size_t *__hlen, size_t *__plen, + const void *endp) +{ + size_t hlen, plen; + + if (!is_contained(__len, endp)) + return -ENODATA; + + switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) { + case CCS_DATA_LENGTH_SPECIFIER_1: + hlen = sizeof(*__len); + plen = __len->length & + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1); + break; + case CCS_DATA_LENGTH_SPECIFIER_2: { + struct __ccs_data_length_specifier2 *__len2 = (void *)__len; + + if (!is_contained(__len2, endp)) + return -ENODATA; + + hlen = sizeof(*__len2); + plen = ((size_t) + (__len2->length[0] & + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1)) + << 8) + __len2->length[1]; + break; + } + case CCS_DATA_LENGTH_SPECIFIER_3: { + struct __ccs_data_length_specifier3 *__len3 = (void *)__len; + + if (!is_contained(__len3, endp)) + return -ENODATA; + + hlen = sizeof(*__len3); + plen = ((size_t) + (__len3->length[0] & + ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1)) + << 16) + u8_arr_to_u32(&__len3->length[1], + sizeof(__len3->length) - 1); + break; + } + default: + return -EINVAL; + } + + if (!has_headroom(__len, hlen + plen, endp)) + return -ENODATA; + + *__hlen = hlen; + *__plen = plen; + + return 0; +} + +static uint8_t +ccs_data_parse_format_version(const struct __ccs_data_block *block) +{ + return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT; +} + +static uint8_t ccs_data_parse_block_id(const struct __ccs_data_block *block, + bool is_first) +{ + if (!is_first) + return block->id; + + return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1); +} + +static int ccs_data_parse_version(struct bin_container *bin, + struct ccs_data_container *ccsdata, + const void *payload, const void *endp) +{ + const struct __ccs_data_block_version *v = payload; + struct ccs_data_block_version *vv; + + if (v + 1 != endp) + return -ENODATA; + + if (!bin->base) { + bin_reserve(bin, sizeof(*ccsdata->version)); + return 0; + } + + ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version)); + if (!ccsdata->version) + return -ENOMEM; + + vv = ccsdata->version; + vv->version_major = u8_arr_to_u32(v->static_data_version_major, 2); + vv->version_minor = u8_arr_to_u32(v->static_data_version_minor, 2); + vv->date_year = u8_arr_to_u32(v->year, 2); + vv->date_month = v->month; + vv->date_day = v->day; + + return 0; +} + +static void print_ccs_data_version(printf_ctx fh, + struct ccs_data_block_version *v) +{ + os_printf(fh, + "static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n", + v->version_major, v->version_minor, + v->date_year, v->date_month, v->date_day); +} + +static int ccs_data_block_parse_header(const struct __ccs_data_block *block, + bool is_first, unsigned int *__block_id, + const void **payload, + const struct __ccs_data_block **next_block, + const void *endp, printf_ctx fh, + bool verbose) +{ + size_t plen, hlen; + uint8_t block_id; + int rval; + + if (!is_contained(block, endp)) + return -ENODATA; + + rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen, + endp); + if (rval < 0) + return rval; + + block_id = ccs_data_parse_block_id(block, is_first); + + if (verbose) + os_printf(fh, + "Block ID 0x%2.2x, header length %zu, payload length %zu\n", + block_id, hlen, plen); + + if (!has_headroom(&block->length, hlen + plen, endp)) + return -ENODATA; + + if (__block_id) + *__block_id = block_id; + + if (payload) + *payload = (void *)&block->length + hlen; + + if (next_block) + *next_block = (void *)&block->length + hlen + plen; + + return 0; +} + +static int ccs_data_parse_regs(struct bin_container *bin, + struct ccs_reg **__regs, + size_t *__num_regs, const void *payload, + const void *endp, printf_ctx fh) +{ + struct ccs_reg *regs_base, *regs; + size_t num_regs = 0; + uint16_t addr = 0; + + if (bin->base && __regs) { + regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs); + if (!regs) + return -ENOMEM; + } + + while (payload < endp && num_regs < INT_MAX) { + const struct __ccs_data_block_regs *r = payload; + size_t len; + const void *data; + + if (!is_contained(r, endp)) + return -ENODATA; + + switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) { + case CCS_DATA_BLOCK_REGS_SEL_REGS: + addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK; + len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK) + >> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1; + + if (!is_contained_with_headroom(r, len, endp)) + return -ENODATA; + + data = r + 1; + break; + case CCS_DATA_BLOCK_REGS_SEL_REGS2: { + const struct __ccs_data_block_regs2 *r2 = payload; + + if (!is_contained(r2, endp)) + return -ENODATA; + + addr += ((uint16_t)(r2->reg_len & + CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8) + + r2->addr; + len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK) + >> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1; + + if (!is_contained_with_headroom(r2, len, endp)) + return -ENODATA; + + data = r2 + 1; + break; + } + case CCS_DATA_BLOCK_REGS_SEL_REGS3: { + const struct __ccs_data_block_regs3 *r3 = payload; + + if (!is_contained(r3, endp)) + return -ENODATA; + + addr = u8_arr_to_u32(r3->addr, sizeof(r3->addr)); + len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1; + + if (!is_contained_with_headroom(r3, len, endp)) + return -ENODATA; + + data = r3 + 1; + break; + } + default: + return -EINVAL; + } + + num_regs++; + + if (!bin->base) { + bin_reserve(bin, len); + } else if (__regs) { + regs->addr = addr; + regs->len = len; + regs->value = bin_alloc(bin, len); + if (!regs->value) + return -ENOMEM; + + memcpy(regs->value, data, len); + regs++; + } + + addr += len; + payload = data + len; + } + + if (!bin->base) + bin_reserve(bin, sizeof(*regs) * num_regs); + + if (__num_regs) + *__num_regs = num_regs; + + if (bin->base && __regs) + *__regs = regs_base; + + return 0; +} + +static int ccs_data_parse_reg_rules(struct bin_container *bin, + struct ccs_reg **__regs, + size_t *__num_regs, + const void *payload, + const void *endp, printf_ctx fh) +{ + int rval; + + if (!bin->base) + return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, fh); + + rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, fh); + if (rval) + return rval; + + return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp, + fh); +} + +static void assign_ffd_entry(struct ccs_frame_format_desc *desc, + const struct __ccs_data_block_ffd_entry *ent) +{ + desc->pixelcode = ent->pixelcode; + desc->value = u8_arr_to_u32(ent->value, sizeof(ent->value)); +} + +static int ccs_data_parse_ffd(struct bin_container *bin, + struct ccs_frame_format_descs **ffd, + const void *payload, + const void *endp, printf_ctx fh) +{ + const struct __ccs_data_block_ffd *__ffd = payload; + const struct __ccs_data_block_ffd_entry *__entry; + unsigned int i; + + if (!is_contained(__ffd, endp)) + return -ENODATA; + + if ((void *)__ffd + sizeof(*__ffd) + + ((uint32_t)__ffd->num_column_descs + + (uint32_t)__ffd->num_row_descs) * + sizeof(struct __ccs_data_block_ffd_entry) != endp) + return -ENODATA; + + if (!bin->base) { + bin_reserve(bin, sizeof(**ffd)); + bin_reserve(bin, __ffd->num_column_descs * + sizeof(struct ccs_frame_format_desc)); + bin_reserve(bin, __ffd->num_row_descs * + sizeof(struct ccs_frame_format_desc)); + + return 0; + } + + *ffd = bin_alloc(bin, sizeof(**ffd)); + if (!*ffd) + return -ENOMEM; + + (*ffd)->num_column_descs = __ffd->num_column_descs; + (*ffd)->num_row_descs = __ffd->num_row_descs; + __entry = (void *)(__ffd + 1); + + (*ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs * + sizeof(*(*ffd)->column_descs)); + if (!(*ffd)->column_descs) + return -ENOMEM; + + for (i = 0; i < __ffd->num_column_descs; i++, __entry++) + assign_ffd_entry(&(*ffd)->column_descs[i], __entry); + + (*ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs * + sizeof(*(*ffd)->row_descs)); + if (!(*ffd)->row_descs) + return -ENOMEM; + + for (i = 0; i < __ffd->num_row_descs; i++, __entry++) + assign_ffd_entry(&(*ffd)->row_descs[i], __entry); + + if (__entry != endp) + return -EPROTO; + + return 0; +} + +static int ccs_data_parse_pdaf_readout(struct bin_container *bin, + struct ccs_pdaf_readout **pdaf_readout, + const void *payload, + const void *endp, printf_ctx fh) +{ + const struct __ccs_data_block_pdaf_readout *__pdaf = payload; + + if (!is_contained(__pdaf, endp)) + return -ENODATA; + + if (!bin->base) { + bin_reserve(bin, sizeof(**pdaf_readout)); + } else { + *pdaf_readout = bin_alloc(bin, sizeof(**pdaf_readout)); + if (!*pdaf_readout) + return -ENOMEM; + + (*pdaf_readout)->pdaf_readout_info_order = + __pdaf->pdaf_readout_info_order; + } + + return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd, + __pdaf + 1, endp, fh); +} + +static int ccs_data_parse_rules(struct bin_container *bin, + struct ccs_rule **__rules, + size_t *__num_rules, const void *payload, + const void *endp, printf_ctx fh) +{ + struct ccs_rule *rules_base, *rules = NULL, *next_rule; + size_t num_rules = 0; + const void *__next_rule = payload; + int rval; + + if (bin->base) { + rules_base = next_rule = + bin_alloc(bin, sizeof(*rules) * *__num_rules); + if (!rules_base) + return -ENOMEM; + } + + while (__next_rule < endp) { + size_t rule_hlen, rule_plen, rule_plen2; + const uint8_t *__rule_type; + const void *rule_payload; + + /* Size of a single rule */ + rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen, + &rule_plen, endp); + + if (rval < 0) + return rval; + + __rule_type = __next_rule + rule_hlen; + + if (!is_contained(__rule_type, endp)) + return -ENODATA; + + rule_payload = __rule_type + 1; + rule_plen2 = rule_plen - sizeof(*__rule_type); + + switch (*__rule_type) { + case CCS_DATA_BLOCK_RULE_ID_IF: { + const struct __ccs_data_block_rule_if *__if_rules = + rule_payload; + const size_t __num_if_rules = + rule_plen2 / sizeof(*__if_rules); + struct ccs_if_rule *if_rule; + + if (!has_headroom(__if_rules, + sizeof(*__if_rules) * __num_if_rules, + rule_payload + rule_plen2)) + return -ENODATA; + + /* Also check there is no extra data */ + if (__if_rules + __num_if_rules != + rule_payload + rule_plen2) + return -EINVAL; + + if (!bin->base) { + bin_reserve(bin, + sizeof(*if_rule) * + __num_if_rules); + num_rules++; + } else { + unsigned int i; + + rules = next_rule; + next_rule++; + + if_rule = bin_alloc(bin, + sizeof(*if_rule) * + __num_if_rules); + if (!if_rule) + return -ENOMEM; + + for (i = 0; i < __num_if_rules; i++) { + if_rule[i].addr = + u8_arr_to_u32( + __if_rules[i].addr, + sizeof(__if_rules[i]. + addr)); + if_rule[i].value = __if_rules[i].value; + if_rule[i].mask = __if_rules[i].mask; + } + + rules->if_rules = if_rule; + rules->num_if_rules = __num_if_rules; + } + break; + } + case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS: + rval = ccs_data_parse_reg_rules(bin, &rules->read_only_regs, + &rules->num_read_only_regs, + rule_payload, + rule_payload + rule_plen2, + fh); + if (rval) + return rval; + break; + case CCS_DATA_BLOCK_RULE_ID_FFD: + rval = ccs_data_parse_ffd(bin, &rules->frame_format, + rule_payload, + rule_payload + rule_plen2, + fh); + if (rval) + return rval; + break; + case CCS_DATA_BLOCK_RULE_ID_MSR: + rval = ccs_data_parse_reg_rules(bin, + &rules->manufacturer_regs, + &rules->num_manufacturer_regs, + rule_payload, + rule_payload + rule_plen2, + fh); + if (rval) + return rval; + break; + case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT: + rval = ccs_data_parse_pdaf_readout(bin, + &rules->pdaf_readout, + rule_payload, + rule_payload + rule_plen2, + fh); + if (rval) + return rval; + break; + default: + os_printf(fh, + "Don't know how to handle rule type %u!\n", + *__rule_type); + return -EINVAL; + } + __next_rule = __next_rule + rule_hlen + rule_plen; + } + + if (!bin->base) { + bin_reserve(bin, sizeof(*rules) * num_rules); + *__num_rules = num_rules; + } else { + *__rules = rules_base; + } + + return 0; +} + +static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_loc **pdaf, + const void *payload, const void *endp, + printf_ctx fh) +{ + const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload; + const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group; + const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc; + unsigned int i; + uint16_t num_block_desc_groups; + uint8_t max_block_type_id = 0; + const uint8_t *__num_pixel_descs; + + if (!is_contained(__pdaf, endp)) + return -ENODATA; + + if (bin->base) { + *pdaf = bin_alloc(bin, sizeof(**pdaf)); + if (!*pdaf) + return -ENOMEM; + } else { + bin_reserve(bin, sizeof(**pdaf)); + } + + num_block_desc_groups = + u8_arr_to_u32(__pdaf->num_block_desc_groups, + sizeof(__pdaf->num_block_desc_groups)); + + if (bin->base) { + (*pdaf)->main_offset_x = + u8_arr_to_u32(__pdaf->main_offset_x, + sizeof(__pdaf->main_offset_x)); + (*pdaf)->main_offset_y = + u8_arr_to_u32(__pdaf->main_offset_y, + sizeof(__pdaf->main_offset_y)); + (*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type; + (*pdaf)->block_width = __pdaf->block_width; + (*pdaf)->block_height = __pdaf->block_height; + (*pdaf)->num_block_desc_groups = num_block_desc_groups; + } + + __bdesc_group = (const void *)(__pdaf + 1); + + if (bin->base) { + (*pdaf)->block_desc_groups = + bin_alloc(bin, + sizeof(struct ccs_pdaf_pix_loc_block_desc_group) * + num_block_desc_groups); + if (!(*pdaf)->block_desc_groups) + return -ENOMEM; + } else { + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) * + num_block_desc_groups); + } + + for (i = 0; i < num_block_desc_groups; i++) { + const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc; + uint16_t num_block_descs; + unsigned int j; + + if (!is_contained(__bdesc_group, endp)) + return -ENODATA; + + num_block_descs = + u8_arr_to_u32(__bdesc_group->num_block_descs, + sizeof(__bdesc_group->num_block_descs)); + + if (bin->base) { + (*pdaf)->block_desc_groups[i].repeat_y = + __bdesc_group->repeat_y; + (*pdaf)->block_desc_groups[i].num_block_descs = + num_block_descs; + } + + __bdesc = (const void *)(__bdesc_group + 1); + + if (bin->base) { + (*pdaf)->block_desc_groups[i].block_descs = + bin_alloc(bin, + sizeof(struct ccs_pdaf_pix_loc_block_desc) * + num_block_descs); + if (!(*pdaf)->block_desc_groups[i].block_descs) + return -ENOMEM; + } else { + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) * + num_block_descs); + } + + for (j = 0; j < num_block_descs; j++, __bdesc++) { + struct ccs_pdaf_pix_loc_block_desc *bdesc; + + if (!is_contained(__bdesc, endp)) + return -ENODATA; + + if (max_block_type_id <= __bdesc->block_type_id) + max_block_type_id = __bdesc->block_type_id + 1; + + if (!bin->base) + continue; + + bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j]; + + bdesc->repeat_x = u8_arr_to_u32( + __bdesc->repeat_x, + sizeof(__bdesc->repeat_x)); + + if (__bdesc->block_type_id >= num_block_descs) + return -EINVAL; + + bdesc->block_type_id = __bdesc->block_type_id; + } + + __bdesc_group = (const void *)__bdesc; + } + + __num_pixel_descs = (const void *)__bdesc_group; + + if (bin->base) { + (*pdaf)->pixel_desc_groups = + bin_alloc(bin, + sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) * + max_block_type_id); + if (!(*pdaf)->pixel_desc_groups) + return -ENOMEM; + (*pdaf)->num_pixel_desc_grups = max_block_type_id; + } else { + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) * + max_block_type_id); + } + + for (i = 0; i < max_block_type_id; i++) { + struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup; + unsigned int j; + + if (!is_contained(__num_pixel_descs, endp)) + return -ENODATA; + + if (bin->base) { + pdgroup = &(*pdaf)->pixel_desc_groups[i]; + pdgroup->descs = + bin_alloc(bin, + sizeof(struct ccs_pdaf_pix_loc_pixel_desc) * + *__num_pixel_descs); + if (!pdgroup->descs) + return -ENOMEM; + pdgroup->num_descs = *__num_pixel_descs; + } else { + bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) * + *__num_pixel_descs); + } + + __pixel_desc = (const void *)(__num_pixel_descs + 1); + + for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) { + struct ccs_pdaf_pix_loc_pixel_desc *pdesc; + + if (!is_contained(__pixel_desc, endp)) + return -ENODATA; + + if (!bin->base) + continue; + + pdesc = &pdgroup->descs[j]; + pdesc->pixel_type = __pixel_desc->pixel_type; + pdesc->small_offset_x = __pixel_desc->small_offset_x; + pdesc->small_offset_y = __pixel_desc->small_offset_y; + } + + __num_pixel_descs = (const void *)(__pixel_desc + 1); + } + + return 0; +} + +static int ccs_data_parse_license(struct bin_container *bin, + char **__license, + size_t *__license_length, + const void *payload, const void *endp) +{ + size_t size = endp - payload; + char *license; + + if (!bin->base) { + bin_reserve(bin, size); + return 0; + } + + license = bin_alloc(bin, size); + if (!license) + return -ENOMEM; + + memcpy(license, payload, size); + + *__license = license; + *__license_length = size; + + return 0; +} + +static int ccs_data_parse_end(bool *end, const void *payload, const void *endp, + printf_ctx fh) +{ + const struct __ccs_data_block_end *__end = payload; + + if (__end + 1 != endp) { + os_printf(fh, "Invalid end block length %u\n", + (unsigned int)(endp - payload)); + return -ENODATA; + } + + *end = true; + + return 0; +} + +static int __ccs_data_parse(struct bin_container *bin, + struct ccs_data_container *ccsdata, + const void *data, size_t len, printf_ctx fh, + bool verbose) +{ + const struct __ccs_data_block *block = data; + const struct __ccs_data_block *endp = data + len; + unsigned int version; + bool is_first = true; + int rval; + + version = ccs_data_parse_format_version(block); + if (version != CCS_STATIC_DATA_VERSION) { + os_printf(fh, "Don't know how to handle version %u\n", version); + return -EINVAL; + } + + if (verbose) + os_printf(fh, "Parsing CCS static data version %u\n", version); + + if (!bin->base) + *ccsdata = (struct ccs_data_container){ 0 }; + + while (block < endp) { + const struct __ccs_data_block *next_block; + unsigned int block_id; + const void *payload; + + rval = ccs_data_block_parse_header(block, is_first, &block_id, + &payload, &next_block, endp, + fh, + bin->base ? false : verbose); + + if (rval < 0) + return rval; + + switch (block_id) { + case CCS_DATA_BLOCK_ID_DUMMY: + break; + case CCS_DATA_BLOCK_ID_DATA_VERSION: + rval = ccs_data_parse_version(bin, ccsdata, payload, + next_block); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS: + rval = ccs_data_parse_regs( + bin, &ccsdata->sensor_read_only_regs, + &ccsdata->num_sensor_read_only_regs, payload, + next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS: + rval = ccs_data_parse_regs( + bin, &ccsdata->sensor_manufacturer_regs, + &ccsdata->num_sensor_manufacturer_regs, payload, + next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS: + rval = ccs_data_parse_regs( + bin, &ccsdata->module_read_only_regs, + &ccsdata->num_module_read_only_regs, payload, + next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS: + rval = ccs_data_parse_regs( + bin, &ccsdata->module_manufacturer_regs, + &ccsdata->num_module_manufacturer_regs, payload, + next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION: + rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf, + payload, next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION: + rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf, + payload, next_block, fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK: + rval = ccs_data_parse_rules( + bin, &ccsdata->sensor_rules, + &ccsdata->num_sensor_rules, payload, next_block, + fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK: + rval = ccs_data_parse_rules( + bin, &ccsdata->module_rules, + &ccsdata->num_module_rules, payload, next_block, + fh); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_LICENSE: + rval = ccs_data_parse_license(bin, &ccsdata->license, + &ccsdata->license_length, + payload, next_block); + if (rval < 0) + return rval; + break; + case CCS_DATA_BLOCK_ID_END: + rval = ccs_data_parse_end(&ccsdata->end, payload, + next_block, fh); + if (rval < 0) + return rval; + break; + default: + os_printf(fh, "WARNING: not handling block ID 0x%2.2x\n", + block_id); + } + + block = next_block; + is_first = false; + } + + return 0; +} + +int ccs_data_parse(struct ccs_data_container *ccsdata, + const void *data, size_t len, printf_ctx fh, bool verbose) +{ + struct bin_container bin = { 0 }; + int rval; + + rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, verbose); + if (rval) + return rval; + + rval = bin_backing_alloc(&bin); + if (rval) + return rval; + + rval = __ccs_data_parse(&bin, ccsdata, data, len, fh, false); + if (rval) + goto out_free; + + if (verbose && ccsdata->version) + print_ccs_data_version(fh, ccsdata->version); + + if (bin.now != bin.end) { + rval = -EPROTO; + os_printf(fh, "parsing mismatch; base %p; now %p; end %p\n", + bin.base, bin.now, bin.end); + goto out_free; + } + + ccsdata->backing = bin.base; + + return 0; + +out_free: + os_free(bin.base); + + return rval; +} diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h new file mode 100644 index 000000000000..1dfc697fccdf --- /dev/null +++ b/drivers/media/i2c/ccs/ccs-data.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* Copyright 2019--2020 Intel Corporation */ + +#ifndef __CCS_DATA_H__ +#define __CCS_DATA_H__ + +#include "ccs-os.h" + +struct ccs_data_block_version { + uint16_t version_major; + uint16_t version_minor; + uint16_t date_year; + uint8_t date_month; + uint8_t date_day; +}; + +struct ccs_reg { + uint16_t addr; + uint16_t len; + uint8_t *value; +}; + +struct ccs_if_rule { + uint16_t addr; + uint8_t value; + uint8_t mask; +}; + +struct ccs_frame_format_desc { + uint8_t pixelcode; + uint16_t value; +}; + +struct ccs_frame_format_descs { + uint8_t num_column_descs; + uint8_t num_row_descs; + struct ccs_frame_format_desc *column_descs; + struct ccs_frame_format_desc *row_descs; +}; + +struct ccs_pdaf_readout { + uint8_t pdaf_readout_info_order; + struct ccs_frame_format_descs *ffd; +}; + +struct ccs_rule { + size_t num_if_rules; + struct ccs_if_rule *if_rules; + size_t num_read_only_regs; + struct ccs_reg *read_only_regs; + size_t num_manufacturer_regs; + struct ccs_reg *manufacturer_regs; + struct ccs_frame_format_descs *frame_format; + struct ccs_pdaf_readout *pdaf_readout; +}; + +struct ccs_pdaf_pix_loc_block_desc { + uint8_t block_type_id; + uint16_t repeat_x; +}; + +struct ccs_pdaf_pix_loc_block_desc_group { + uint8_t repeat_y; + uint16_t num_block_descs; + struct ccs_pdaf_pix_loc_block_desc *block_descs; +}; + +struct ccs_pdaf_pix_loc_pixel_desc { + uint8_t pixel_type; + uint8_t small_offset_x; + uint8_t small_offset_y; +}; + +struct ccs_pdaf_pix_loc_pixel_desc_group { + uint8_t num_descs; + struct ccs_pdaf_pix_loc_pixel_desc *descs; +}; + +struct ccs_pdaf_pix_loc { + uint16_t main_offset_x; + uint16_t main_offset_y; + uint8_t global_pdaf_type; + uint8_t block_width; + uint8_t block_height; + uint16_t num_block_desc_groups; + struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups; + uint8_t num_pixel_desc_grups; + struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups; +}; + +struct ccs_data_container { + struct ccs_data_block_version *version; + size_t num_sensor_read_only_regs; + struct ccs_reg *sensor_read_only_regs; + size_t num_sensor_manufacturer_regs; + struct ccs_reg *sensor_manufacturer_regs; + size_t num_sensor_rules; + struct ccs_rule *sensor_rules; + size_t num_module_read_only_regs; + struct ccs_reg *module_read_only_regs; + size_t num_module_manufacturer_regs; + struct ccs_reg *module_manufacturer_regs; + size_t num_module_rules; + struct ccs_rule *module_rules; + struct ccs_pdaf_pix_loc *sensor_pdaf; + struct ccs_pdaf_pix_loc *module_pdaf; + size_t license_length; + char *license; + bool end; + void *backing; +}; + +int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data, + size_t len, printf_ctx fh, bool verbose); + +#endif /* __CCS_DATA_H__ */ From patchwork Wed Sep 30 15:27:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1CAD618 for ; Wed, 30 Sep 2020 15:30:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E79221941 for ; Wed, 30 Sep 2020 15:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731152AbgI3PaI (ORCPT ); Wed, 30 Sep 2020 11:30:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730972AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DCBEC061755 for ; Wed, 30 Sep 2020 08:29:07 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 59270634CCD for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 033/100] ccs: Combine revision number major and minor into one Date: Wed, 30 Sep 2020 18:27:51 +0300 Message-Id: <20200930152858.8471-34-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The module revision number major and minor are both 8 bits while the sensor revision number is 16 bits. Combine the module revision into one number. This also adds printing the lowest 8 bits of the module version through the sysfs attribute. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 25 ++++++++++++++----------- drivers/media/i2c/ccs/ccs-quirk.c | 2 +- drivers/media/i2c/ccs/ccs.h | 3 +-- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index d8553aba00c8..f888f434cdd2 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -2421,11 +2421,11 @@ ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr, if (minfo->mipi_manufacturer_id) return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n", minfo->mipi_manufacturer_id, minfo->model_id, - minfo->revision_number_major) + 1; + minfo->revision_number) + 1; else return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n", minfo->smia_manufacturer_id, minfo->model_id, - minfo->revision_number_major) + 1; + minfo->revision_number) + 1; } static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL); @@ -2439,6 +2439,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor) struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct ccs_module_info *minfo = &sensor->minfo; unsigned int i; + u32 rev; int rval = 0; /* Module info */ @@ -2454,11 +2455,13 @@ static int ccs_identify_module(struct ccs_sensor *sensor) if (!rval) rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_REVISION_NUMBER_MAJOR, - &minfo->revision_number_major); - if (!rval) + &rev); + if (!rval) { rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_REVISION_NUMBER_MINOR, - &minfo->revision_number_minor); + &minfo->revision_number); + minfo->revision_number |= rev << 8; + } if (!rval) rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR, &minfo->module_year); @@ -2513,9 +2516,9 @@ static int ccs_identify_module(struct ccs_sensor *sensor) minfo->smia_manufacturer_id, minfo->model_id); dev_dbg(&client->dev, - "module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n", - minfo->revision_number_major, minfo->revision_number_minor, - minfo->module_year, minfo->module_month, minfo->module_day); + "module revision 0x%4.4x date %2.2d-%2.2d-%2.2d\n", + minfo->revision_number, minfo->module_year, minfo->module_month, + minfo->module_day); if (minfo->sensor_mipi_manufacturer_id) dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n", @@ -2553,7 +2556,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor) minfo->smia_manufacturer_id = minfo->sensor_smia_manufacturer_id; minfo->model_id = minfo->sensor_model_id; - minfo->revision_number_major = minfo->sensor_revision_number; + minfo->revision_number = minfo->sensor_revision_number; } for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) { @@ -2570,11 +2573,11 @@ static int ccs_identify_module(struct ccs_sensor *sensor) if (ccs_module_idents[i].flags & CCS_MODULE_IDENT_FLAG_REV_LE) { if (ccs_module_idents[i].revision_number_major - < minfo->revision_number_major) + < (minfo->revision_number >> 8)) continue; } else { if (ccs_module_idents[i].revision_number_major - != minfo->revision_number_major) + != (minfo->revision_number >> 8)) continue; } diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index facec28f8447..07c5733b4244 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -35,7 +35,7 @@ static int ccs_write_addr_8s(struct ccs_sensor *sensor, static int jt8ew9_limits(struct ccs_sensor *sensor) { - if (sensor->minfo.revision_number_major < 0x03) + if (sensor->minfo.revision_number < 0x0300) sensor->frame_skip = 1; /* Below 24 gain doesn't have effect at all, */ diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 2d1e8339f663..ad2ff5a74424 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -107,8 +107,7 @@ struct ccs_module_info { u32 smia_manufacturer_id; u32 mipi_manufacturer_id; u32 model_id; - u32 revision_number_major; - u32 revision_number_minor; + u32 revision_number; u32 module_year; u32 module_month; From patchwork Wed Sep 30 15:27:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C64292C for ; Wed, 30 Sep 2020 15:30:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86C8D21D43 for ; Wed, 30 Sep 2020 15:30:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731153AbgI3PaI (ORCPT ); Wed, 30 Sep 2020 11:30:08 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728805AbgI3P3H (ORCPT ); Wed, 30 Sep 2020 11:29:07 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 6CA9F634CCF for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 034/100] ccs: Read CCS static data from firmware binaries Date: Wed, 30 Sep 2020 18:27:52 +0300 Message-Id: <20200930152858.8471-35-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Read the CCS static data for sensors and modules. The files are expected to be found in "ccs" directory. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 30 ++++++++++++++++++++++++++++++ drivers/media/i2c/ccs/ccs.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index f888f434cdd2..58b4e9051184 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -2948,6 +2949,8 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev) static int ccs_probe(struct i2c_client *client) { struct ccs_sensor *sensor; + const struct firmware *fw; + char filename[40]; unsigned int i; int rval; @@ -3037,6 +3040,31 @@ static int ccs_probe(struct i2c_client *client) goto out_power_off; } + WARN_ON(snprintf(filename, sizeof(filename), + "ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw", + sensor->minfo.sensor_mipi_manufacturer_id, + sensor->minfo.sensor_model_id, + sensor->minfo.sensor_revision_number) >= + sizeof(filename)); + rval = request_firmware(&fw, filename, &client->dev); + if (!rval) { + ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev, + true); + release_firmware(fw); + } + + WARN_ON(snprintf(filename, sizeof(filename), + "ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw", + sensor->minfo.mipi_manufacturer_id, + sensor->minfo.model_id, + sensor->minfo.revision_number) >= sizeof(filename)); + rval = request_firmware(&fw, filename, &client->dev); + if (!rval) { + ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev, + true); + release_firmware(fw); + } + rval = ccs_read_all_limits(sensor); if (rval) goto out_power_off; @@ -3233,6 +3261,8 @@ static int ccs_remove(struct i2c_client *client) ccs_cleanup(sensor); mutex_destroy(&sensor->mutex); kfree(sensor->ccs_limits); + kvfree(sensor->sdata.backing); + kvfree(sensor->mdata.backing); return 0; } diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index ad2ff5a74424..cbcd93b519da 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -16,6 +16,7 @@ #include #include +#include "ccs-data.h" #include "ccs-quirk.h" #include "ccs-regs.h" #include "ccs-reg-access.h" @@ -227,6 +228,7 @@ struct ccs_sensor { const struct ccs_csi_data_format *internal_csi_format; u32 default_mbus_frame_fmts; int default_pixel_order; + struct ccs_data_container sdata, mdata; u8 binning_horizontal; u8 binning_vertical; From patchwork Wed Sep 30 15:27:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809591 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B02992C for ; Wed, 30 Sep 2020 15:30:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BE6F21481 for ; Wed, 30 Sep 2020 15:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731146AbgI3PaD (ORCPT ); Wed, 30 Sep 2020 11:30:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730982AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8980FC061755 for ; Wed, 30 Sep 2020 08:29:08 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 81A32634CD0 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 035/100] ccs: Stop reading arrays after the first zero Date: Wed, 30 Sep 2020 18:27:53 +0300 Message-Id: <20200930152858.8471-36-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The register arrays have a certain size but not all the entries will be relevant. In practice reading can be stopped after encountering a zero value in the array. Do that to avoid extra reads. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 58b4e9051184..4c08e2d1d94c 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -193,6 +193,9 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor) goto out_err; } + if (!val && j) + break; + ccs_assign_limit(ptr, width, val); dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n", From patchwork Wed Sep 30 15:27:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809597 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FC3692C for ; Wed, 30 Sep 2020 15:30:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 41FA5216C4 for ; Wed, 30 Sep 2020 15:30:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730959AbgI3PaF (ORCPT ); Wed, 30 Sep 2020 11:30:05 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730967AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 92A8A634CD1 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 036/100] ccs: The functions to get compose or crop rectangle never return NULL Date: Wed, 30 Sep 2020 18:27:54 +0300 Message-Id: <20200930152858.8471-37-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The NULL check is not needed as the functions do not return NULL. Remove the check (and BUG). Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 4c08e2d1d94c..9a3d7131cd10 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1760,16 +1760,12 @@ static void ccs_get_crop_compose(struct v4l2_subdev *subdev, *comps = &ssd->compose; } else { if (crops) { - for (i = 0; i < subdev->entity.num_pads; i++) { + for (i = 0; i < subdev->entity.num_pads; i++) crops[i] = v4l2_subdev_get_try_crop(subdev, cfg, i); - BUG_ON(!crops[i]); - } } - if (comps) { + if (comps) *comps = v4l2_subdev_get_try_compose(subdev, cfg, CCS_PAD_SINK); - BUG_ON(!*comps); - } } } From patchwork Wed Sep 30 15:27:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D364692C for ; Wed, 30 Sep 2020 15:30:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4BC621481 for ; Wed, 30 Sep 2020 15:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730967AbgI3PaH (ORCPT ); Wed, 30 Sep 2020 11:30:07 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730968AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A45C2634CD2 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 037/100] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON Date: Wed, 30 Sep 2020 18:27:55 +0300 Message-Id: <20200930152858.8471-38-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org If an internal driver error was encountered, BUG was issued. Instead, do less harsh WARN_ON_ONCE and try to manage with the consequences. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 9a3d7131cd10..f51e1ae505b3 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -540,6 +540,10 @@ static void ccs_update_mbus_formats(struct ccs_sensor *sensor) to_csi_format_idx(sensor->internal_csi_format) & ~3; unsigned int pixel_order = ccs_pixel_order(sensor); + if (WARN_ON_ONCE(max(internal_csi_format_idx, csi_format_idx) + + pixel_order >= ARRAY_SIZE(ccs_csi_data_formats))) + return; + sensor->mbus_frame_fmts = sensor->default_mbus_frame_fmts << pixel_order; sensor->csi_format = @@ -548,9 +552,6 @@ static void ccs_update_mbus_formats(struct ccs_sensor *sensor) &ccs_csi_data_formats[internal_csi_format_idx + pixel_order]; - BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order - >= ARRAY_SIZE(ccs_csi_data_formats)); - dev_dbg(&client->dev, "new pixel order %s\n", pixel_order_str[pixel_order]); } @@ -1800,7 +1801,7 @@ static void ccs_propagate(struct v4l2_subdev *subdev, *crops[CCS_PAD_SRC] = *comp; break; default: - BUG(); + WARN_ON_ONCE(1); } } From patchwork Wed Sep 30 15:27:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8B5A618 for ; Wed, 30 Sep 2020 15:30:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C53402176B for ; Wed, 30 Sep 2020 15:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731151AbgI3PaH (ORCPT ); Wed, 30 Sep 2020 11:30:07 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730973AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id B7FF0634CD4 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 038/100] ccs: Refactor register reading a little Date: Wed, 30 Sep 2020 18:27:56 +0300 Message-Id: <20200930152858.8471-39-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Rework quirk and 8-bit only access functions with a single function that takes arguments. This is later extensible to support yet more flags. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-reg-access.c | 37 ++++++++++++-------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index a8e9a235bfb3..abec746f3c93 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -168,39 +168,36 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, return 0; } -int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val) -{ - return __ccs_read_addr( - sensor, reg, val, - ccs_needs_quirk(sensor, CCS_QUIRK_FLAG_8BIT_READ_ONLY)); -} - -static int ccs_read_addr_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val, - bool force8) +static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, + bool force8, bool quirk) { int rval; - *val = 0; - rval = ccs_call_quirk(sensor, reg_access, false, ®, val); - if (rval == -ENOIOCTLCMD) - return 0; - if (rval < 0) - return rval; + if (quirk) { + *val = 0; + rval = ccs_call_quirk(sensor, reg_access, false, ®, val); + if (rval == -ENOIOCTLCMD) + return 0; + if (rval < 0) + return rval; - if (force8) - return __ccs_read_addr(sensor, reg, val, true); + if (force8) + return __ccs_read_addr(sensor, reg, val, true); + } - return ccs_read_addr_no_quirk(sensor, reg, val); + return __ccs_read_addr(sensor, reg, val, + ccs_needs_quirk(sensor, + CCS_QUIRK_FLAG_8BIT_READ_ONLY)); } int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_quirk(sensor, reg, val, false); + return ccs_read_addr_raw(sensor, reg, val, false, true); } int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_quirk(sensor, reg, val, true); + return ccs_read_addr_raw(sensor, reg, val, true, true); } int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) From patchwork Wed Sep 30 15:27:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809595 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E48C618 for ; Wed, 30 Sep 2020 15:30:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E93721734 for ; Wed, 30 Sep 2020 15:30:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731148AbgI3PaD (ORCPT ); Wed, 30 Sep 2020 11:30:03 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730969AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id CC564634CD5 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 039/100] ccs: Make real to integer number conversion optional Date: Wed, 30 Sep 2020 18:27:57 +0300 Message-Id: <20200930152858.8471-40-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The limit values will be raw soon, and the conversion takes place later on. Prepare for that. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-reg-access.c | 35 +++++++++++++++++++------- drivers/media/i2c/ccs/ccs-reg-access.h | 2 ++ 2 files changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index abec746f3c93..fe6112cba6be 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -143,14 +143,23 @@ unsigned int ccs_reg_width(u32 reg) return sizeof(uint8_t); } +u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + + if (reg & CCS_FL_FLOAT_IREAL) + val = float_to_u32_mul_1000000(client, val); + + return val; +} + /* * Read a 8/16/32-bit i2c register. The value is returned in 'val'. * Returns zero if successful, or non-zero otherwise. */ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, - bool only8) + bool only8, bool conv) { - struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); unsigned int len = ccs_reg_width(reg); int rval; @@ -162,14 +171,16 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, if (rval < 0) return rval; - if (reg & CCS_FL_FLOAT_IREAL) - *val = float_to_u32_mul_1000000(client, *val); + if (!conv) + return 0; + + *val = ccs_reg_conv(sensor, reg, *val); return 0; } static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, - bool force8, bool quirk) + bool force8, bool quirk, bool conv) { int rval; @@ -182,22 +193,28 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, return rval; if (force8) - return __ccs_read_addr(sensor, reg, val, true); + return __ccs_read_addr(sensor, reg, val, true, conv); } return __ccs_read_addr(sensor, reg, val, ccs_needs_quirk(sensor, - CCS_QUIRK_FLAG_8BIT_READ_ONLY)); + CCS_QUIRK_FLAG_8BIT_READ_ONLY), + conv); } int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_raw(sensor, reg, val, false, true); + return ccs_read_addr_raw(sensor, reg, val, false, true, true); } int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_raw(sensor, reg, val, true, true); + return ccs_read_addr_raw(sensor, reg, val, true, true, true); +} + +int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val) +{ + return ccs_read_addr_raw(sensor, reg, val, false, true, false); } int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h index 9fdf5659ed09..5f6ff9c57698 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.h +++ b/drivers/media/i2c/ccs/ccs-reg-access.h @@ -24,10 +24,12 @@ struct ccs_sensor; int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val); int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val); int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val); +int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val); int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val); int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val); unsigned int ccs_reg_width(u32 reg); +u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val); #define ccs_read(sensor, reg_name, val) \ ccs_read_addr(sensor, CCS_R_##reg_name, val) From patchwork Wed Sep 30 15:27:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44DBB92C for ; Wed, 30 Sep 2020 15:30:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34C412158C for ; Wed, 30 Sep 2020 15:30:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731149AbgI3PaD (ORCPT ); Wed, 30 Sep 2020 11:30:03 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730970AbgI3P3I (ORCPT ); Wed, 30 Sep 2020 11:29:08 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id E24C3634CD7 for ; Wed, 30 Sep 2020 18:28:49 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 040/100] ccs: Move limit value real to integer conversion from read to access time Date: Wed, 30 Sep 2020 18:27:58 +0300 Message-Id: <20200930152858.8471-41-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Instead of converting the limit values at register read time, do that at access time instead. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index f51e1ae505b3..34878678bc5f 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -124,6 +124,7 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset) { void *ptr; + u32 val; int ret; ret = ccs_limit_ptr(sensor, limit, offset, &ptr); @@ -132,16 +133,20 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor, switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) { case sizeof(u8): - return *(u8 *)ptr; + val = *(u8 *)ptr; + break; case sizeof(u16): - return *(u16 *)ptr; + val = *(u16 *)ptr; + break; case sizeof(u32): - return *(u32 *)ptr; + val = *(u32 *)ptr; + break; + default: + WARN_ON(1); + return 0; } - WARN_ON(1); - - return 0; + return ccs_reg_conv(sensor, ccs_limits[limit].reg, val); } #define CCS_LIM(sensor, limit) \ @@ -182,7 +187,7 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor) j++, reg += width, ptr += width) { u32 val; - ret = ccs_read_addr(sensor, reg, &val); + ret = ccs_read_addr_noconv(sensor, reg, &val); if (ret) goto out_err; From patchwork Wed Sep 30 15:27:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 15DE0618 for ; Wed, 30 Sep 2020 15:30:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F1EE620EDD for ; Wed, 30 Sep 2020 15:30:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730980AbgI3P37 (ORCPT ); Wed, 30 Sep 2020 11:29:59 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730975AbgI3P3J (ORCPT ); Wed, 30 Sep 2020 11:29:09 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 02FBC634C95 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 041/100] ccs: Read ireal numbers correctly Date: Wed, 30 Sep 2020 18:27:59 +0300 Message-Id: <20200930152858.8471-42-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some limit values are available in q16.q16 format, referred to as 32-bit unsigned ireal in CCS. Read these correctly. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 10 ++-------- drivers/media/i2c/ccs/ccs-reg-access.c | 23 +++++++++++++++++++++-- drivers/media/i2c/ccs/ccs.h | 9 +++++++++ 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 34878678bc5f..40e0fc84205c 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -120,8 +120,8 @@ void ccs_replace_limit(struct ccs_sensor *sensor, ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val); } -static u32 ccs_get_limit(struct ccs_sensor *sensor, - unsigned int limit, unsigned int offset) +u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit, + unsigned int offset) { void *ptr; u32 val; @@ -149,12 +149,6 @@ static u32 ccs_get_limit(struct ccs_sensor *sensor, return ccs_reg_conv(sensor, ccs_limits[limit].reg, val); } -#define CCS_LIM(sensor, limit) \ - ccs_get_limit(sensor, CCS_L_##limit, 0) - -#define CCS_LIM_AT(sensor, limit, offset) \ - ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset)) - static int ccs_read_all_limits(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index fe6112cba6be..91ccbca11577 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -15,6 +15,7 @@ #include #include "ccs.h" +#include "ccs-limits.h" static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, uint32_t phloat) @@ -143,12 +144,30 @@ unsigned int ccs_reg_width(u32 reg) return sizeof(uint8_t); } +static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val) +{ + if (val >> 10 > U32_MAX / 15625) { + dev_warn(&client->dev, "value %u overflows!\n", val); + return U32_MAX; + } + + return ((val >> 10) * 15625) + + (val & GENMASK(9, 0)) * 15625 / 1024; +} + u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - if (reg & CCS_FL_FLOAT_IREAL) - val = float_to_u32_mul_1000000(client, val); + if (reg & CCS_FL_FLOAT_IREAL) { + if (CCS_LIM(sensor, CLOCK_CAPA_TYPE_CAPABILITY) & + CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL) + val = ireal32_to_u32_mul_1000000(client, val); + else + val = float_to_u32_mul_1000000(client, val); + } else if (reg & CCS_FL_IREAL) { + val = ireal32_to_u32_mul_1000000(client, val); + } return val; } diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index cbcd93b519da..f60d1801c469 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -17,6 +17,7 @@ #include #include "ccs-data.h" +#include "ccs-limits.h" #include "ccs-quirk.h" #include "ccs-regs.h" #include "ccs-reg-access.h" @@ -50,6 +51,12 @@ #define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */ #define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */ +#define CCS_LIM(sensor, limit) \ + ccs_get_limit(sensor, CCS_L_##limit, 0) + +#define CCS_LIM_AT(sensor, limit, offset) \ + ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset)) + /* * Sometimes due to board layout considerations the camera module can be * mounted rotated. The typical rotation used is 180 degrees which can be @@ -277,5 +284,7 @@ struct ccs_sensor { void ccs_replace_limit(struct ccs_sensor *sensor, unsigned int limit, unsigned int offset, u32 val); +u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit, + unsigned int offset); #endif /* __CCS_H__ */ From patchwork Wed Sep 30 15:28:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43F7C618 for ; Wed, 30 Sep 2020 15:30:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 22352207C3 for ; Wed, 30 Sep 2020 15:30:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730957AbgI3P36 (ORCPT ); Wed, 30 Sep 2020 11:29:58 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730977AbgI3P3J (ORCPT ); Wed, 30 Sep 2020 11:29:09 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 1AF3D634CD8 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 042/100] smiapp-pll: Rename as ccs-pll Date: Wed, 30 Sep 2020 18:28:00 +0300 Message-Id: <20200930152858.8471-43-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org MIPI CCS replaces SMIA and SMIA++ as the current standard. CCS brings new features while existing functionality will be supported. Rename the smiapp-pll as ccs-pll accordingly. Also add Intel copyright to the files. Signed-off-by: Sakari Ailus --- drivers/media/i2c/Kconfig | 2 +- drivers/media/i2c/Makefile | 2 +- drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} | 60 +++++++++---------- drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} | 40 ++++++------- drivers/media/i2c/ccs/Kconfig | 2 +- drivers/media/i2c/ccs/ccs-core.c | 18 +++--- drivers/media/i2c/ccs/ccs-quirk.c | 2 +- drivers/media/i2c/ccs/ccs.h | 4 +- 8 files changed, 64 insertions(+), 66 deletions(-) rename drivers/media/i2c/{smiapp-pll.c => ccs-pll.c} (90%) rename drivers/media/i2c/{smiapp-pll.h => ccs-pll.h} (68%) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 41a8b6189259..4b6fcf13d527 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -722,7 +722,7 @@ menu "Camera sensor devices" config VIDEO_APTINA_PLL tristate -config VIDEO_SMIAPP_PLL +config VIDEO_CCS_PLL tristate config VIDEO_HI556 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index cb0be09e38bd..c716bac3ed4b 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -104,7 +104,7 @@ obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o obj-$(CONFIG_VIDEO_LM3560) += lm3560.o obj-$(CONFIG_VIDEO_LM3646) += lm3646.o -obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o +obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o obj-$(CONFIG_VIDEO_AK881X) += ak881x.o obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o obj-$(CONFIG_VIDEO_I2C) += video-i2c.o diff --git a/drivers/media/i2c/smiapp-pll.c b/drivers/media/i2c/ccs-pll.c similarity index 90% rename from drivers/media/i2c/smiapp-pll.c rename to drivers/media/i2c/ccs-pll.c index 690abe8cbdb2..d2f0f7375f5c 100644 --- a/drivers/media/i2c/smiapp-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * drivers/media/i2c/smiapp-pll.c + * drivers/media/i2c/ccs-pll.c * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic MIPI CCS/SMIA/SMIA++ PLL calculator * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation * Contact: Sakari Ailus */ @@ -13,7 +14,7 @@ #include #include -#include "smiapp-pll.h" +#include "ccs-pll.h" /* Return an even number or one. */ static inline uint32_t clk_div_even(uint32_t a) @@ -50,11 +51,11 @@ static int bounds_check(struct device *dev, uint32_t val, return -EINVAL; } -static void print_pll(struct device *dev, struct smiapp_pll *pll) +static void print_pll(struct device *dev, struct ccs_pll *pll) { dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); - if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { + if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); } @@ -64,7 +65,7 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll) dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz); - if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { + if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", pll->op.sys_clk_freq_hz); dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", @@ -75,10 +76,9 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll) } static int check_all_bounds(struct device *dev, - const struct smiapp_pll_limits *limits, - const struct smiapp_pll_branch_limits *op_limits, - struct smiapp_pll *pll, - struct smiapp_pll_branch *op_pll) + const struct ccs_pll_limits *limits, + const struct ccs_pll_branch_limits *op_limits, + struct ccs_pll *pll, struct ccs_pll_branch *op_pll) { int rval; @@ -118,7 +118,7 @@ static int check_all_bounds(struct device *dev, * If there are no OP clocks, the VT clocks are contained in * the OP clock struct. */ - if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) return rval; if (!rval) @@ -148,11 +148,11 @@ static int check_all_bounds(struct device *dev, * * @return Zero on success, error code on error. */ -static int __smiapp_pll_calculate( - struct device *dev, const struct smiapp_pll_limits *limits, - const struct smiapp_pll_branch_limits *op_limits, - struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, - uint32_t div, uint32_t lane_op_clock_ratio) +static int +__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, + const struct ccs_pll_branch_limits *op_limits, + struct ccs_pll *pll, struct ccs_pll_branch *op_pll, + uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -252,7 +252,7 @@ static int __smiapp_pll_calculate( op_pll->pix_clk_freq_hz = op_pll->sys_clk_freq_hz / op_pll->pix_clk_div; - if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* No OP clocks --- VT clocks are used instead. */ goto out_skip_vt_calc; } @@ -383,12 +383,11 @@ static int __smiapp_pll_calculate( return check_all_bounds(dev, limits, op_limits, pll, op_pll); } -int smiapp_pll_calculate(struct device *dev, - const struct smiapp_pll_limits *limits, - struct smiapp_pll *pll) +int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, + struct ccs_pll *pll) { - const struct smiapp_pll_branch_limits *op_limits = &limits->op; - struct smiapp_pll_branch *op_pll = &pll->op; + const struct ccs_pll_branch_limits *op_limits = &limits->op; + struct ccs_pll_branch *op_pll = &pll->op; uint16_t min_pre_pll_clk_div; uint16_t max_pre_pll_clk_div; uint32_t lane_op_clock_ratio; @@ -396,7 +395,7 @@ int smiapp_pll_calculate(struct device *dev, unsigned int i; int rval = -EINVAL; - if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* * If there's no OP PLL at all, use the VT values * instead. The OP values are ignored for the rest of @@ -406,7 +405,7 @@ int smiapp_pll_calculate(struct device *dev, op_pll = &pll->vt; } - if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) + if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) lane_op_clock_ratio = pll->csi2.lanes; else lane_op_clock_ratio = 1; @@ -416,12 +415,12 @@ int smiapp_pll_calculate(struct device *dev, pll->binning_vertical); switch (pll->bus_type) { - case SMIAPP_PLL_BUS_TYPE_CSI2: + case CCS_PLL_BUS_TYPE_CSI2: /* CSI transfers 2 bits per clock per lane; thus times 2 */ pll->pll_op_clk_freq_hz = pll->link_freq * 2 * (pll->csi2.lanes / lane_op_clock_ratio); break; - case SMIAPP_PLL_BUS_TYPE_PARALLEL: + case CCS_PLL_BUS_TYPE_PARALLEL: pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel / DIV_ROUND_UP(pll->bits_per_pixel, pll->parallel.bus_width); @@ -461,9 +460,8 @@ int smiapp_pll_calculate(struct device *dev, for (pll->pre_pll_clk_div = min_pre_pll_clk_div; pll->pre_pll_clk_div <= max_pre_pll_clk_div; pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { - rval = __smiapp_pll_calculate(dev, limits, op_limits, pll, - op_pll, mul, div, - lane_op_clock_ratio); + rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll, + mul, div, lane_op_clock_ratio); if (rval) continue; @@ -475,8 +473,8 @@ int smiapp_pll_calculate(struct device *dev, return rval; } -EXPORT_SYMBOL_GPL(smiapp_pll_calculate); +EXPORT_SYMBOL_GPL(ccs_pll_calculate); MODULE_AUTHOR("Sakari Ailus "); -MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator"); +MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/smiapp-pll.h b/drivers/media/i2c/ccs-pll.h similarity index 68% rename from drivers/media/i2c/smiapp-pll.h rename to drivers/media/i2c/ccs-pll.h index bd6902f54539..88d641ee3fa1 100644 --- a/drivers/media/i2c/smiapp-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -1,32 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * drivers/media/i2c/smiapp-pll.h + * drivers/media/i2c/ccs-pll.h * - * Generic driver for SMIA/SMIA++ compliant camera modules + * Generic MIPI CCS/SMIA/SMIA++ PLL calculator * + * Copyright (C) 2020 Intel Corporation * Copyright (C) 2012 Nokia Corporation * Contact: Sakari Ailus */ -#ifndef SMIAPP_PLL_H -#define SMIAPP_PLL_H +#ifndef CCS_PLL_H +#define CCS_PLL_H /* CSI-2 or CCP-2 */ -#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00 -#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01 +#define CCS_PLL_BUS_TYPE_CSI2 0x00 +#define CCS_PLL_BUS_TYPE_PARALLEL 0x01 /* op pix clock is for all lanes in total normally */ -#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) -#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1) +#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) +#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) -struct smiapp_pll_branch { +struct ccs_pll_branch { uint16_t sys_clk_div; uint16_t pix_clk_div; uint32_t sys_clk_freq_hz; uint32_t pix_clk_freq_hz; }; -struct smiapp_pll { +struct ccs_pll { /* input values */ uint8_t bus_type; union { @@ -51,14 +52,14 @@ struct smiapp_pll { uint16_t pll_multiplier; uint32_t pll_ip_clk_freq_hz; uint32_t pll_op_clk_freq_hz; - struct smiapp_pll_branch vt; - struct smiapp_pll_branch op; + struct ccs_pll_branch vt; + struct ccs_pll_branch op; uint32_t pixel_rate_csi; uint32_t pixel_rate_pixel_array; }; -struct smiapp_pll_branch_limits { +struct ccs_pll_branch_limits { uint16_t min_sys_clk_div; uint16_t max_sys_clk_div; uint32_t min_sys_clk_freq_hz; @@ -69,7 +70,7 @@ struct smiapp_pll_branch_limits { uint32_t max_pix_clk_freq_hz; }; -struct smiapp_pll_limits { +struct ccs_pll_limits { /* Strict PLL limits */ uint32_t min_ext_clk_freq_hz; uint32_t max_ext_clk_freq_hz; @@ -82,8 +83,8 @@ struct smiapp_pll_limits { uint32_t min_pll_op_freq_hz; uint32_t max_pll_op_freq_hz; - struct smiapp_pll_branch_limits vt; - struct smiapp_pll_branch_limits op; + struct ccs_pll_branch_limits vt; + struct ccs_pll_branch_limits op; /* Other relevant limits */ uint32_t min_line_length_pck_bin; @@ -92,8 +93,7 @@ struct smiapp_pll_limits { struct device; -int smiapp_pll_calculate(struct device *dev, - const struct smiapp_pll_limits *limits, - struct smiapp_pll *pll); +int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, + struct ccs_pll *pll); -#endif /* SMIAPP_PLL_H */ +#endif /* CCS_PLL_H */ diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig index b4f8b10da420..59f35b33ddc1 100644 --- a/drivers/media/i2c/ccs/Kconfig +++ b/drivers/media/i2c/ccs/Kconfig @@ -4,7 +4,7 @@ config VIDEO_CCS depends on I2C && VIDEO_V4L2 && HAVE_CLK select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API - select VIDEO_SMIAPP_PLL + select VIDEO_CCS_PLL select V4L2_FWNODE help This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 40e0fc84205c..21765f98bdc4 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -357,7 +357,7 @@ static int ccs_read_frame_fmt(struct ccs_sensor *sensor) static int ccs_pll_configure(struct ccs_sensor *sensor) { - struct smiapp_pll *pll = &sensor->pll; + struct ccs_pll *pll = &sensor->pll; int rval; rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div); @@ -380,7 +380,7 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) rval = ccs_write(sensor, REQUESTED_LINK_RATE, DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); - if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) + if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) return rval; rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div); @@ -390,10 +390,10 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div); } -static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll) +static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - struct smiapp_pll_limits lim = { + struct ccs_pll_limits lim = { .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV), .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV), .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ), @@ -425,12 +425,12 @@ static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll) .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK), }; - return smiapp_pll_calculate(&client->dev, &lim, pll); + return ccs_pll_calculate(&client->dev, &lim, pll); } static int ccs_pll_update(struct ccs_sensor *sensor) { - struct smiapp_pll *pll = &sensor->pll; + struct ccs_pll *pll = &sensor->pll; int rval; pll->binning_horizontal = sensor->binning_horizontal; @@ -823,7 +823,7 @@ static void ccs_free_controls(struct ccs_sensor *sensor) static int ccs_get_mbus_formats(struct ccs_sensor *sensor) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); - struct smiapp_pll *pll = &sensor->pll; + struct ccs_pll *pll = &sensor->pll; u8 compressed_max_bpp = 0; unsigned int type, n; unsigned int i, pixel_order; @@ -3141,7 +3141,7 @@ static int ccs_probe(struct i2c_client *client) !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) || !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) { /* No OP clock branch */ - sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; + sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS; } else if (CCS_LIM(sensor, SCALING_CAPABILITY) != CCS_SCALING_CAPABILITY_NONE || CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY) @@ -3158,7 +3158,7 @@ static int ccs_probe(struct i2c_client *client) sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN); /* prepare PLL configuration input values */ - sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2; + sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2; sensor->pll.csi2.lanes = sensor->hwcfg.lanes; sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index 07c5733b4244..8b4fa60044b2 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -190,7 +190,7 @@ static int jt8ev1_post_streamoff(struct ccs_sensor *sensor) static int jt8ev1_init(struct ccs_sensor *sensor) { - sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE; + sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE; return 0; } diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index f60d1801c469..c8a9f4ee093e 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -21,7 +21,7 @@ #include "ccs-quirk.h" #include "ccs-regs.h" #include "ccs-reg-access.h" -#include "../smiapp-pll.h" +#include "../ccs-pll.h" #include "smiapp-reg-defs.h" /* @@ -256,7 +256,7 @@ struct ccs_sensor { struct ccs_module_info minfo; - struct smiapp_pll pll; + struct ccs_pll pll; /* Is a default format supported for a given BPP? */ unsigned long *valid_link_freqs; From patchwork Wed Sep 30 15:28:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77BEE92C for ; Wed, 30 Sep 2020 15:30:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 62F08207C3 for ; Wed, 30 Sep 2020 15:30:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731143AbgI3P37 (ORCPT ); Wed, 30 Sep 2020 11:29:59 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730980AbgI3P3J (ORCPT ); Wed, 30 Sep 2020 11:29:09 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 3AD04634C8F for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 043/100] ccs: Change my e-mail address Date: Wed, 30 Sep 2020 18:28:01 +0300 Message-Id: <20200930152858.8471-44-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use my @linux.intel.com e-mail address in the CCS driver. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 4 ++-- drivers/media/i2c/ccs-pll.h | 2 +- drivers/media/i2c/ccs/ccs-core.c | 6 +++--- drivers/media/i2c/ccs/ccs-quirk.c | 2 +- drivers/media/i2c/ccs/ccs-quirk.h | 2 +- drivers/media/i2c/ccs/ccs-reg-access.c | 2 +- drivers/media/i2c/ccs/ccs-reg-access.h | 2 +- drivers/media/i2c/ccs/ccs.h | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index d2f0f7375f5c..49d5e26ace47 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #include @@ -475,6 +475,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, } EXPORT_SYMBOL_GPL(ccs_pll_calculate); -MODULE_AUTHOR("Sakari Ailus "); +MODULE_AUTHOR("Sakari Ailus "); MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 88d641ee3fa1..07f7f9e8a1cc 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #ifndef CCS_PLL_H diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 21765f98bdc4..14f74f21efd4 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2010--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus * * Based on smiapp driver by Vimarsh Zutshi * Based on jt8ev1.c by Vimarsh Zutshi @@ -1162,7 +1162,7 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor) * do not change, or if you do at least know what you're * doing. :-) * - * Sakari Ailus 2010-10-25 + * Sakari Ailus 2010-10-25 * * flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl * / EXTCLK freq [Hz]) * flash_strobe_adjustment @@ -3322,7 +3322,7 @@ static void ccs_module_cleanup(void) module_init(ccs_module_init); module_exit(ccs_module_cleanup); -MODULE_AUTHOR("Sakari Ailus "); +MODULE_AUTHOR("Sakari Ailus "); MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("smiapp"); diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index 8b4fa60044b2..4fe8c6f70579 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #include diff --git a/drivers/media/i2c/ccs/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h index 3e7779e2fc4b..6b4ec4beaba0 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.h +++ b/drivers/media/i2c/ccs/ccs-quirk.h @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #ifndef __CCS_QUIRK__ diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index 91ccbca11577..aad2727570ec 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #include diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h index 5f6ff9c57698..cfad2e520fe2 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.h +++ b/drivers/media/i2c/ccs/ccs-reg-access.h @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2011--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #ifndef SMIAPP_REGS_H diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index c8a9f4ee093e..6b07e4143ff0 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -6,7 +6,7 @@ * * Copyright (C) 2020 Intel Corporation * Copyright (C) 2010--2012 Nokia Corporation - * Contact: Sakari Ailus + * Contact: Sakari Ailus */ #ifndef __CCS_H__ From patchwork Wed Sep 30 15:28:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809569 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC0C092C for ; Wed, 30 Sep 2020 15:29:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D8A9020789 for ; Wed, 30 Sep 2020 15:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731133AbgI3P3x (ORCPT ); Wed, 30 Sep 2020 11:29:53 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44682 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730981AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 531CF634C90 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 044/100] ccs: Add support for manufacturer regs from sensor and module files Date: Wed, 30 Sep 2020 18:28:02 +0300 Message-Id: <20200930152858.8471-45-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Write manufacturer specific registers (MSRs) from file to the sensor on sensor power-on. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 23 +++++++ drivers/media/i2c/ccs/ccs-reg-access.c | 94 ++++++++++++++++++++------ drivers/media/i2c/ccs/ccs-reg-access.h | 2 + 3 files changed, 97 insertions(+), 22 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 14f74f21efd4..bc3443a9f563 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1272,6 +1272,21 @@ static int ccs_setup_flash_strobe(struct ccs_sensor *sensor) * Power management */ +static int ccs_write_msr_regs(struct ccs_sensor *sensor) +{ + int rval; + + rval = ccs_write_data_regs(sensor, + sensor->sdata.sensor_manufacturer_regs, + sensor->sdata.num_sensor_manufacturer_regs); + if (rval) + return rval; + + return ccs_write_data_regs(sensor, + sensor->mdata.module_manufacturer_regs, + sensor->mdata.num_module_manufacturer_regs); +} + static int ccs_power_on(struct device *dev) { struct v4l2_subdev *subdev = dev_get_drvdata(dev); @@ -1377,6 +1392,10 @@ static int ccs_power_on(struct device *dev) if (rval < 0) goto out_cci_addr_fail; + rval = ccs_write_msr_regs(sensor); + if (rval) + goto out_cci_addr_fail; + rval = ccs_call_quirk(sensor, post_poweron); if (rval) { dev_err(dev, "post_poweron quirks failed\n"); @@ -3206,6 +3225,10 @@ static int ccs_probe(struct i2c_client *client) if (rval < 0) goto out_media_entity_cleanup; + rval = ccs_write_msr_regs(sensor); + if (rval) + goto out_media_entity_cleanup; + pm_runtime_set_active(&client->dev); pm_runtime_get_noresume(&client->dev); pm_runtime_enable(&client->dev); diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index aad2727570ec..9fda16b221a7 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -236,12 +236,38 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val) return ccs_read_addr_raw(sensor, reg, val, false, true, false); } +static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg) +{ + unsigned int retries; + int r; + + for (retries = 0; retries < 5; retries++) { + /* + * Due to unknown reason sensor stops responding. This + * loop is a temporaty solution until the root cause + * is found. + */ + r = i2c_transfer(client->adapter, msg, 1); + if (r != 1) { + usleep_range(2000, 2000); + continue; + } + + if (retries) + dev_err(&client->dev, + "sensor i2c stall encountered. retries: %d\n", + retries); + return 0; + } + + return r; +} + int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct i2c_msg msg; unsigned char data[6]; - unsigned int retries; unsigned int len = ccs_reg_width(reg); int r; @@ -256,27 +282,11 @@ int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) put_unaligned_be16(CCS_REG_ADDR(reg), data); put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2); - for (retries = 0; retries < 5; retries++) { - /* - * Due to unknown reason sensor stops responding. This - * loop is a temporaty solution until the root cause - * is found. - */ - r = i2c_transfer(client->adapter, &msg, 1); - if (r == 1) { - if (retries) - dev_err(&client->dev, - "sensor i2c stall encountered. retries: %d\n", - retries); - return 0; - } - - usleep_range(2000, 2000); - } - - dev_err(&client->dev, - "wrote 0x%x to offset 0x%x error %d\n", val, - CCS_REG_ADDR(reg), r); + r = ccs_write_retry(client, &msg); + if (r) + dev_err(&client->dev, + "wrote 0x%x to offset 0x%x error %d\n", val, + CCS_REG_ADDR(reg), r); return r; } @@ -297,3 +307,43 @@ int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val) return ccs_write_addr_no_quirk(sensor, reg, val); } + +#define MAX_WRITE_LEN 32U + +int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs, + size_t num_regs) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + unsigned char buf[2 + MAX_WRITE_LEN]; + struct i2c_msg msg = { + .addr = client->addr, + .buf = buf, + }; + size_t i; + + for (i = 0; i < num_regs; i++, regs++) { + unsigned char *regdata = regs->value; + unsigned int j; + + for (j = 0; j < regs->len; + j += msg.len - 2, regdata += msg.len - 2) { + int rval; + + msg.len = min(regs->len - j, MAX_WRITE_LEN); + + put_unaligned_be16(regs->addr + j, buf); + memcpy(buf + 2, regdata, msg.len); + msg.len += 2; + + rval = ccs_write_retry(client, &msg); + if (rval) { + dev_err(&client->dev, + "error writing %u octets to address 0x%4.4x\n", + msg.len, regs->addr + j); + return rval; + } + } + } + + return 0; +} diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h index cfad2e520fe2..78c43f92d99a 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.h +++ b/drivers/media/i2c/ccs/ccs-reg-access.h @@ -27,6 +27,8 @@ int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val); int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val); int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val); int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val); +int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs, + size_t num_regs); unsigned int ccs_reg_width(u32 reg); u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val); From patchwork Wed Sep 30 15:28:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809589 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AB64618 for ; Wed, 30 Sep 2020 15:30:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 464A12137B for ; Wed, 30 Sep 2020 15:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731145AbgI3PaC (ORCPT ); Wed, 30 Sep 2020 11:30:02 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730984AbgI3P3J (ORCPT ); Wed, 30 Sep 2020 11:29:09 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 69F8A634C91 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 045/100] ccs: Use static data read-only registers Date: Wed, 30 Sep 2020 18:28:03 +0300 Message-Id: <20200930152858.8471-46-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Access read-only registers from CCS static data. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-reg-access.c | 64 ++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index 9fda16b221a7..02af2b0abdaf 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -198,11 +198,67 @@ static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val, return 0; } +static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs, + u32 reg, u32 *val) +{ + unsigned int width = ccs_reg_width(reg); + size_t i; + + for (i = 0; i < num_regs; i++, regs++) { + uint8_t *data; + + if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width) + continue; + + if (regs->addr > CCS_REG_ADDR(reg)) + break; + + data = ®s->value[CCS_REG_ADDR(reg) - regs->addr]; + + switch (width) { + case sizeof(uint8_t): + *val = *data; + break; + case sizeof(uint16_t): + *val = get_unaligned_be16(data); + break; + case sizeof(uint32_t): + *val = get_unaligned_be32(data); + break; + default: + WARN_ON(1); + return -EINVAL; + } + + return 0; + } + + return -ENOENT; +} + +static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val) +{ + if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs, + sensor->sdata.num_sensor_read_only_regs, + reg, val)) + return 0; + + return __ccs_read_data(sensor->mdata.module_read_only_regs, + sensor->mdata.num_module_read_only_regs, + reg, val); +} + static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, - bool force8, bool quirk, bool conv) + bool force8, bool quirk, bool conv, bool data) { int rval; + if (data) { + rval = ccs_read_data(sensor, reg, val); + if (!rval) + return 0; + } + if (quirk) { *val = 0; rval = ccs_call_quirk(sensor, reg_access, false, ®, val); @@ -223,17 +279,17 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val, int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_raw(sensor, reg, val, false, true, true); + return ccs_read_addr_raw(sensor, reg, val, false, true, true, true); } int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_raw(sensor, reg, val, true, true, true); + return ccs_read_addr_raw(sensor, reg, val, true, true, true, true); } int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val) { - return ccs_read_addr_raw(sensor, reg, val, false, true, false); + return ccs_read_addr_raw(sensor, reg, val, false, true, false, true); } static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg) From patchwork Wed Sep 30 15:28:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 794FE92C for ; Wed, 30 Sep 2020 15:29:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65B18207C3 for ; Wed, 30 Sep 2020 15:29:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728076AbgI3P35 (ORCPT ); Wed, 30 Sep 2020 11:29:57 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730986AbgI3P3J (ORCPT ); Wed, 30 Sep 2020 11:29:09 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 7D3E7634C93 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 046/100] ccs: Clean up runtime PM usage Date: Wed, 30 Sep 2020 18:28:04 +0300 Message-Id: <20200930152858.8471-47-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org If pm_runtime_get_sync() fails, there's no need to set the device active again. Also, in the same case to return the usage_count to zero, pm_runtime_put_noidle() is enough. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index bc3443a9f563..474cfc8e0c7e 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1619,8 +1619,6 @@ static int ccs_pm_get_init(struct ccs_sensor *sensor) rval = pm_runtime_get_sync(&client->dev); if (rval < 0) { - if (rval != -EBUSY && rval != -EAGAIN) - pm_runtime_set_active(&client->dev); pm_runtime_put_noidle(&client->dev); return rval; @@ -2836,9 +2834,8 @@ static int __maybe_unused ccs_suspend(struct device *dev) rval = pm_runtime_get_sync(dev); if (rval < 0) { - if (rval != -EBUSY && rval != -EAGAIN) - pm_runtime_set_active(&client->dev); - pm_runtime_put(dev); + pm_runtime_put_noidle(dev); + return -EAGAIN; } From patchwork Wed Sep 30 15:28:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809577 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DF5413B2 for ; Wed, 30 Sep 2020 15:29:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19F65207C3 for ; Wed, 30 Sep 2020 15:29:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731140AbgI3P34 (ORCPT ); Wed, 30 Sep 2020 11:29:56 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730987AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 90B3E634C94 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 047/100] ccs: Wrap long lines, unwrap short ones Date: Wed, 30 Sep 2020 18:28:05 +0300 Message-Id: <20200930152858.8471-48-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Over the years (and renaming) some lines that may well be wrapped ended up being over 80 characters, likewise there are shorter lines that can be merged. Do that. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 45 +++++++++++++------------------- 1 file changed, 18 insertions(+), 27 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 474cfc8e0c7e..4bc483db6001 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -651,8 +651,7 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_HBLANK: rval = ccs_write(sensor, LINE_LENGTH_PCK, - sensor->pixel_array->crop[ - CCS_PA_PAD_SRC].width + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width + ctrl->val); break; @@ -983,15 +982,13 @@ static void ccs_update_blanking(struct ccs_sensor *sensor) min = max_t(int, CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES), - min_fll - - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height); + min_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height); max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height; __v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min); min = max_t(int, - min_llp - - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width, + min_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width, min_lbp); max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width; @@ -1778,7 +1775,8 @@ static void ccs_get_crop_compose(struct v4l2_subdev *subdev, } else { if (crops) { for (i = 0; i < subdev->entity.num_pads; i++) - crops[i] = v4l2_subdev_get_try_crop(subdev, cfg, i); + crops[i] = v4l2_subdev_get_try_crop(subdev, + cfg, i); } if (comps) *comps = v4l2_subdev_get_try_compose(subdev, cfg, @@ -1803,8 +1801,7 @@ static void ccs_propagate(struct v4l2_subdev *subdev, comp->height = crops[CCS_PAD_SINK]->height; if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { if (ssd == sensor->scaler) { - sensor->scale_m = - CCS_LIM(sensor, SCALER_N_MIN); + sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN); sensor->scaling_mode = CCS_SCALING_MODE_NO_SCALING; } else if (ssd == sensor->binner) { @@ -2230,9 +2227,11 @@ static int ccs_set_crop(struct v4l2_subdev *subdev, if (sel->pad == ssd->sink_pad) { _r.left = 0; _r.top = 0; - _r.width = v4l2_subdev_get_try_format(subdev, cfg, sel->pad) + _r.width = v4l2_subdev_get_try_format(subdev, cfg, + sel->pad) ->width; - _r.height = v4l2_subdev_get_try_format(subdev, cfg, sel->pad) + _r.height = v4l2_subdev_get_try_format(subdev, cfg, + sel->pad) ->height; src_size = &_r; } else { @@ -2350,11 +2349,9 @@ static int ccs_set_selection(struct v4l2_subdev *subdev, sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags); sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags); - sel->r.width = max_t(unsigned int, - CCS_LIM(sensor, MIN_X_OUTPUT_SIZE), + sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE), sel->r.width); - sel->r.height = max_t(unsigned int, - CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE), + sel->r.height = max_t(unsigned int, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE), sel->r.height); switch (sel->target) { @@ -2607,8 +2604,7 @@ static int ccs_identify_module(struct ccs_sensor *sensor) dev_warn(&client->dev, "no quirks for this module; let's hope it's fully compliant\n"); - dev_dbg(&client->dev, "the sensor is called %s\n", - minfo->name); + dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name); return 0; } @@ -2628,19 +2624,15 @@ static int ccs_register_subdev(struct ccs_sensor *sensor, if (!sink_ssd) return 0; - rval = media_entity_pads_init(&ssd->sd.entity, - ssd->npads, ssd->pads); + rval = media_entity_pads_init(&ssd->sd.entity, ssd->npads, ssd->pads); if (rval) { - dev_err(&client->dev, - "media_entity_pads_init failed\n"); + dev_err(&client->dev, "media_entity_pads_init failed\n"); return rval; } - rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, - &ssd->sd); + rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, &ssd->sd); if (rval) { - dev_err(&client->dev, - "v4l2_device_register_subdev failed\n"); + dev_err(&client->dev, "v4l2_device_register_subdev failed\n"); return rval; } @@ -2648,8 +2640,7 @@ static int ccs_register_subdev(struct ccs_sensor *sensor, &sink_ssd->sd.entity, sink_pad, link_flags); if (rval) { - dev_err(&client->dev, - "media_create_pad_link failed\n"); + dev_err(&client->dev, "media_create_pad_link failed\n"); v4l2_device_unregister_subdev(&ssd->sd); return rval; } From patchwork Wed Sep 30 15:28:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809571 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B72992C for ; Wed, 30 Sep 2020 15:29:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5358320759 for ; Wed, 30 Sep 2020 15:29:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731134AbgI3P3z (ORCPT ); Wed, 30 Sep 2020 11:29:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731000AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75438C061755 for ; Wed, 30 Sep 2020 08:29:10 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A9822634CD9 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 048/100] ccs: Add device compatible identifiers for telling SMIA and CCS apart Date: Wed, 30 Sep 2020 18:28:06 +0300 Message-Id: <20200930152858.8471-49-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add device data specific to DT compatible ID to tell SMIA and CCS devices apart already in power-up. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 4bc483db6001..93c0da53f03f 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -59,6 +59,12 @@ static const struct ccs_module_ident ccs_module_idents[] = { CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk), }; +#define CCS_DEVICE_FLAG_IS_SMIA BIT(0) + +struct ccs_device { + unsigned char flags; +}; + /* * * Dynamic Capability Identification @@ -3277,9 +3283,15 @@ static int ccs_remove(struct i2c_client *client) return 0; } +static const struct ccs_device smia_device = { + .flags = CCS_DEVICE_FLAG_IS_SMIA, +}; + +static const struct ccs_device ccs_device = {}; + static const struct of_device_id ccs_of_table[] = { - { .compatible = "nokia,smia" }, - { .compatible = "mipi,ccs" }, + { .compatible = "nokia,smia", .data = &smia_device }, + { .compatible = "mipi,ccs", .data = &ccs_device }, { }, }; MODULE_DEVICE_TABLE(of, ccs_of_table); From patchwork Wed Sep 30 15:28:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6F25618 for ; Wed, 30 Sep 2020 15:29:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D466A207FB for ; Wed, 30 Sep 2020 15:29:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731142AbgI3P35 (ORCPT ); Wed, 30 Sep 2020 11:29:57 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730988AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id BD4E4634C92 for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 049/100] =?utf-8?q?ccs=3A_Use_longer_pre-I=C2=B2C_sleep_for_?= =?utf-8?q?CCS_compliant_devices?= Date: Wed, 30 Sep 2020 18:28:07 +0300 Message-Id: <20200930152858.8471-50-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Longer idle period is required on I²C bus before the first transaction after lifting xshutdown. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 93c0da53f03f..a99022e8de25 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -1300,6 +1300,7 @@ static int ccs_power_on(struct device *dev) */ struct ccs_sensor *sensor = container_of(ssd, struct ccs_sensor, ssds[0]); + const struct ccs_device *ccsdev = device_get_match_data(dev); unsigned int sleep; int rval; @@ -1320,7 +1321,11 @@ static int ccs_power_on(struct device *dev) gpiod_set_value(sensor->reset, 0); gpiod_set_value(sensor->xshutdown, 1); - sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk); + if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA) + sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk); + else + sleep = 5000; + usleep_range(sleep, sleep); /* From patchwork Wed Sep 30 15:28:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809573 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D732C13B2 for ; Wed, 30 Sep 2020 15:29:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C59CD20789 for ; Wed, 30 Sep 2020 15:29:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731139AbgI3P34 (ORCPT ); Wed, 30 Sep 2020 11:29:56 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730992AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id CD068634CDA for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 050/100] ccs-pll: Don't use div_u64 to divide a 32-bit number Date: Wed, 30 Sep 2020 18:28:08 +0300 Message-Id: <20200930152858.8471-51-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to divide it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 49d5e26ace47..ccd850a44ae4 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -445,7 +445,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, min_pre_pll_clk_div, max_pre_pll_clk_div); i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); - mul = div_u64(pll->pll_op_clk_freq_hz, i); + mul = pll->pll_op_clk_freq_hz / i; div = pll->ext_clk_freq_hz / i; dev_dbg(dev, "mul %u / div %u\n", mul, div); From patchwork Wed Sep 30 15:28:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809539 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63B8713B2 for ; Wed, 30 Sep 2020 15:29:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DBD920789 for ; Wed, 30 Sep 2020 15:29:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731026AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730993AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id DF77E634CDC for ; Wed, 30 Sep 2020 18:28:50 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 051/100] ccs-pll: Split limits and PLL configuration into front and back parts Date: Wed, 30 Sep 2020 18:28:09 +0300 Message-Id: <20200930152858.8471-52-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CCS spec supports a lot of variation in the PLL. Split the PLL in front and back parts to better prepare for supporting it. Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include "clk" in the name). Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 282 ++++++++++++++++--------------- drivers/media/i2c/ccs-pll.h | 44 +++-- drivers/media/i2c/ccs/ccs-core.c | 71 ++++---- 3 files changed, 209 insertions(+), 188 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index ccd850a44ae4..dd30949efb6b 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -53,65 +53,68 @@ static int bounds_check(struct device *dev, uint32_t val, static void print_pll(struct device *dev, struct ccs_pll *pll) { - dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); - dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); + dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div); + dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier); if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { - dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); - dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); + dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div); + dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div); } - dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); - dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); + dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div); + dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div); dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); - dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); - dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz); + dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz); + dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz); if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", - pll->op.sys_clk_freq_hz); + pll->op_bk.sys_clk_freq_hz); dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", - pll->op.pix_clk_freq_hz); + pll->op_bk.pix_clk_freq_hz); } - dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz); - dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz); + dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz); + dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz); } static int check_all_bounds(struct device *dev, - const struct ccs_pll_limits *limits, - const struct ccs_pll_branch_limits *op_limits, - struct ccs_pll *pll, struct ccs_pll_branch *op_pll) + const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_fr *op_lim_fr, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, + struct ccs_pll_branch_fr *op_pll_fr, + struct ccs_pll_branch_bk *op_pll_bk) { int rval; - rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, - limits->min_pll_ip_freq_hz, - limits->max_pll_ip_freq_hz, + rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz, + op_lim_fr->min_pll_ip_clk_freq_hz, + op_lim_fr->max_pll_ip_clk_freq_hz, "pll_ip_clk_freq_hz"); if (!rval) rval = bounds_check( - dev, pll->pll_multiplier, - limits->min_pll_multiplier, limits->max_pll_multiplier, - "pll_multiplier"); + dev, op_pll_fr->pll_multiplier, + op_lim_fr->min_pll_multiplier, + op_lim_fr->max_pll_multiplier, "pll_multiplier"); if (!rval) rval = bounds_check( - dev, pll->pll_op_clk_freq_hz, - limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, - "pll_op_clk_freq_hz"); + dev, op_pll_fr->pll_op_clk_freq_hz, + op_lim_fr->min_pll_op_clk_freq_hz, + op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz"); if (!rval) rval = bounds_check( - dev, op_pll->sys_clk_div, - op_limits->min_sys_clk_div, op_limits->max_sys_clk_div, + dev, op_pll_bk->sys_clk_div, + op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div, "op_sys_clk_div"); if (!rval) rval = bounds_check( - dev, op_pll->sys_clk_freq_hz, - op_limits->min_sys_clk_freq_hz, - op_limits->max_sys_clk_freq_hz, + dev, op_pll_bk->sys_clk_freq_hz, + op_lim_bk->min_sys_clk_freq_hz, + op_lim_bk->max_sys_clk_freq_hz, "op_sys_clk_freq_hz"); if (!rval) rval = bounds_check( - dev, op_pll->pix_clk_freq_hz, - op_limits->min_pix_clk_freq_hz, - op_limits->max_pix_clk_freq_hz, + dev, op_pll_bk->pix_clk_freq_hz, + op_lim_bk->min_pix_clk_freq_hz, + op_lim_bk->max_pix_clk_freq_hz, "op_pix_clk_freq_hz"); /* @@ -123,15 +126,15 @@ static int check_all_bounds(struct device *dev, if (!rval) rval = bounds_check( - dev, pll->vt.sys_clk_freq_hz, - limits->vt.min_sys_clk_freq_hz, - limits->vt.max_sys_clk_freq_hz, + dev, pll->vt_bk.sys_clk_freq_hz, + lim->vt_bk.min_sys_clk_freq_hz, + lim->vt_bk.max_sys_clk_freq_hz, "vt_sys_clk_freq_hz"); if (!rval) rval = bounds_check( - dev, pll->vt.pix_clk_freq_hz, - limits->vt.min_pix_clk_freq_hz, - limits->vt.max_pix_clk_freq_hz, + dev, pll->vt_bk.pix_clk_freq_hz, + lim->vt_bk.min_pix_clk_freq_hz, + lim->vt_bk.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); return rval; @@ -149,10 +152,12 @@ static int check_all_bounds(struct device *dev, * @return Zero on success, error code on error. */ static int -__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, - const struct ccs_pll_branch_limits *op_limits, - struct ccs_pll *pll, struct ccs_pll_branch *op_pll, - uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio) +__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_fr *op_lim_fr, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, + struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, + uint32_t div, uint32_t lane_op_clock_ratio) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -173,42 +178,42 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be * too high. */ - dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div); + dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); /* Don't go above max pll multiplier. */ - more_mul_max = limits->max_pll_multiplier / mul; - dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n", + more_mul_max = op_lim_fr->max_pll_multiplier / mul; + dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", more_mul_max); /* Don't go above max pll op frequency. */ more_mul_max = min_t(uint32_t, more_mul_max, - limits->max_pll_op_freq_hz - / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul)); - dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n", + op_lim_fr->max_pll_op_clk_freq_hz + / (pll->ext_clk_freq_hz / op_pll_fr->pre_pll_clk_div * mul)); + dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", more_mul_max); /* Don't go above the division capability of op sys clock divider. */ more_mul_max = min(more_mul_max, - op_limits->max_sys_clk_div * pll->pre_pll_clk_div + op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div / div); dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", more_mul_max); /* Ensure we won't go above min_pll_multiplier. */ more_mul_max = min(more_mul_max, - DIV_ROUND_UP(limits->max_pll_multiplier, mul)); + DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", more_mul_max); - /* Ensure we won't go below min_pll_op_freq_hz. */ - more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz, - pll->ext_clk_freq_hz / pll->pre_pll_clk_div - * mul); - dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n", + /* Ensure we won't go below min_pll_op_clk_freq_hz. */ + more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, + pll->ext_clk_freq_hz / + op_pll_fr->pre_pll_clk_div * mul); + dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", more_mul_min); /* Ensure we won't go below min_pll_multiplier. */ more_mul_min = max(more_mul_min, - DIV_ROUND_UP(limits->min_pll_multiplier, mul)); - dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n", + DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); + dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", more_mul_min); if (more_mul_min > more_mul_max) { @@ -217,9 +222,9 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, return -EINVAL; } - more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div; + more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); - more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div); + more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", more_mul_factor); i = roundup(more_mul_min, more_mul_factor); @@ -232,25 +237,25 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, return -EINVAL; } - pll->pll_multiplier = mul * i; - op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div; - dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div); + op_pll_fr->pll_multiplier = mul * i; + op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; + dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); - pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz - / pll->pre_pll_clk_div; + op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz + / op_pll_fr->pre_pll_clk_div; - pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz - * pll->pll_multiplier; + op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz + * op_pll_fr->pll_multiplier; /* Derive pll_op_clk_freq_hz. */ - op_pll->sys_clk_freq_hz = - pll->pll_op_clk_freq_hz / op_pll->sys_clk_div; + op_pll_bk->sys_clk_freq_hz = + op_pll_fr->pll_op_clk_freq_hz / op_pll_bk->sys_clk_div; - op_pll->pix_clk_div = pll->bits_per_pixel; - dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div); + op_pll_bk->pix_clk_div = pll->bits_per_pixel; + dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); - op_pll->pix_clk_freq_hz = - op_pll->sys_clk_freq_hz / op_pll->pix_clk_div; + op_pll_bk->pix_clk_freq_hz = + op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* No OP clocks --- VT clocks are used instead. */ @@ -264,7 +269,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, * should run at higher clock rate, so smaller divisor is used * on video timing side. */ - if (limits->min_line_length_pck_bin > limits->min_line_length_pck + if (lim->min_line_length_pck_bin > lim->min_line_length_pck / pll->binning_horizontal) vt_op_binning_div = pll->binning_horizontal; else @@ -283,28 +288,28 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, * Find absolute limits for the factor of vt divider. */ dev_dbg(dev, "scale_m: %u\n", pll->scale_m); - min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div - * pll->scale_n, + min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div + * op_pll_bk->sys_clk_div * pll->scale_n, lane_op_clock_ratio * vt_op_binning_div * pll->scale_m); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); min_vt_div = max(min_vt_div, - DIV_ROUND_UP(pll->pll_op_clk_freq_hz, - limits->vt.max_pix_clk_freq_hz)); + DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.max_pix_clk_freq_hz)); dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", min_vt_div); min_vt_div = max_t(uint32_t, min_vt_div, - limits->vt.min_pix_clk_div - * limits->vt.min_sys_clk_div); + lim->vt_bk.min_pix_clk_div + * lim->vt_bk.min_sys_clk_div); dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); - max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div; + max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); max_vt_div = min(max_vt_div, - DIV_ROUND_UP(pll->pll_op_clk_freq_hz, - limits->vt.min_pix_clk_freq_hz)); + DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", max_vt_div); @@ -312,28 +317,28 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, * Find limitsits for sys_clk_div. Not all values are possible * with all values of pix_clk_div. */ - min_sys_div = limits->vt.min_sys_clk_div; + min_sys_div = lim->vt_bk.min_sys_clk_div; dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); min_sys_div = max(min_sys_div, DIV_ROUND_UP(min_vt_div, - limits->vt.max_pix_clk_div)); + lim->vt_bk.max_pix_clk_div)); dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); min_sys_div = max(min_sys_div, - pll->pll_op_clk_freq_hz - / limits->vt.max_sys_clk_freq_hz); + op_pll_fr->pll_op_clk_freq_hz + / lim->vt_bk.max_sys_clk_freq_hz); dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); min_sys_div = clk_div_even_up(min_sys_div); dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); - max_sys_div = limits->vt.max_sys_clk_div; + max_sys_div = lim->vt_bk.max_sys_clk_div; dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); max_sys_div = min(max_sys_div, DIV_ROUND_UP(max_vt_div, - limits->vt.min_pix_clk_div)); + lim->vt_bk.min_pix_clk_div)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); max_sys_div = min(max_sys_div, - DIV_ROUND_UP(pll->pll_op_clk_freq_hz, - limits->vt.min_pix_clk_freq_hz)); + DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); /* @@ -348,13 +353,13 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, sys_div += 2 - (sys_div & 1)) { uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); - if (pix_div < limits->vt.min_pix_clk_div - || pix_div > limits->vt.max_pix_clk_div) { + if (pix_div < lim->vt_bk.min_pix_clk_div + || pix_div > lim->vt_bk.max_pix_clk_div) { dev_dbg(dev, "pix_div %u too small or too big (%u--%u)\n", pix_div, - limits->vt.min_pix_clk_div, - limits->vt.max_pix_clk_div); + lim->vt_bk.min_pix_clk_div, + lim->vt_bk.max_pix_clk_div); continue; } @@ -367,29 +372,32 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, break; } - pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); - pll->vt.pix_clk_div = best_pix_div; + pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); + pll->vt_bk.pix_clk_div = best_pix_div; - pll->vt.sys_clk_freq_hz = - pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div; - pll->vt.pix_clk_freq_hz = - pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div; + pll->vt_bk.sys_clk_freq_hz = + op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; + pll->vt_bk.pix_clk_freq_hz = + pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; out_skip_vt_calc: pll->pixel_rate_csi = - op_pll->pix_clk_freq_hz * lane_op_clock_ratio; - pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz; + op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio; + pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz; - return check_all_bounds(dev, limits, op_limits, pll, op_pll); + return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, + op_pll_bk); } -int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, +int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll *pll) { - const struct ccs_pll_branch_limits *op_limits = &limits->op; - struct ccs_pll_branch *op_pll = &pll->op; - uint16_t min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div; + const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr; + const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; + struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; + struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; + uint16_t min_op_pre_pll_clk_div; + uint16_t max_op_pre_pll_clk_div; uint32_t lane_op_clock_ratio; uint32_t mul, div; unsigned int i; @@ -401,8 +409,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, * instead. The OP values are ignored for the rest of * the PLL calculation. */ - op_limits = &limits->vt; - op_pll = &pll->vt; + op_lim_fr = &lim->vt_fr; + op_lim_bk = &lim->vt_bk; + op_pll_bk = &pll->vt_bk; } if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) @@ -417,11 +426,11 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, switch (pll->bus_type) { case CCS_PLL_BUS_TYPE_CSI2: /* CSI transfers 2 bits per clock per lane; thus times 2 */ - pll->pll_op_clk_freq_hz = pll->link_freq * 2 + op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2 * (pll->csi2.lanes / lane_op_clock_ratio); break; case CCS_PLL_BUS_TYPE_PARALLEL: - pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel + op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel / DIV_ROUND_UP(pll->bits_per_pixel, pll->parallel.bus_width); break; @@ -429,39 +438,40 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, return -EINVAL; } - /* Figure out limits for pre-pll divider based on extclk */ - dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n", - limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); - max_pre_pll_clk_div = - min_t(uint16_t, limits->max_pre_pll_clk_div, + /* Figure out limits for OP pre-pll divider based on extclk */ + dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", + op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); + max_op_pre_pll_clk_div = + min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div, clk_div_even(pll->ext_clk_freq_hz / - limits->min_pll_ip_freq_hz)); - min_pre_pll_clk_div = - max_t(uint16_t, limits->min_pre_pll_clk_div, + op_lim_fr->min_pll_ip_clk_freq_hz)); + min_op_pre_pll_clk_div = + max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div, clk_div_even_up( DIV_ROUND_UP(pll->ext_clk_freq_hz, - limits->max_pll_ip_freq_hz))); - dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n", - min_pre_pll_clk_div, max_pre_pll_clk_div); + op_lim_fr->max_pll_ip_clk_freq_hz))); + dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", + min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); - i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); - mul = pll->pll_op_clk_freq_hz / i; + i = gcd(op_pll_fr->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); + mul = op_pll_fr->pll_op_clk_freq_hz / i; div = pll->ext_clk_freq_hz / i; dev_dbg(dev, "mul %u / div %u\n", mul, div); - min_pre_pll_clk_div = - max_t(uint16_t, min_pre_pll_clk_div, + min_op_pre_pll_clk_div = + max_t(uint16_t, min_op_pre_pll_clk_div, clk_div_even_up( DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, - limits->max_pll_op_freq_hz))); - dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n", - min_pre_pll_clk_div, max_pre_pll_clk_div); - - for (pll->pre_pll_clk_div = min_pre_pll_clk_div; - pll->pre_pll_clk_div <= max_pre_pll_clk_div; - pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { - rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll, - mul, div, lane_op_clock_ratio); + op_lim_fr->max_pll_op_clk_freq_hz))); + dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", + min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); + + for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; + op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; + op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) { + rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, + op_pll_fr, op_pll_bk, mul, div, + lane_op_clock_ratio); if (rval) continue; diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 07f7f9e8a1cc..03b1d8d11423 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -20,7 +20,14 @@ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) #define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) -struct ccs_pll_branch { +struct ccs_pll_branch_fr { + uint16_t pre_pll_clk_div; + uint16_t pll_multiplier; + uint32_t pll_ip_clk_freq_hz; + uint32_t pll_op_clk_freq_hz; +}; + +struct ccs_pll_branch_bk { uint16_t sys_clk_div; uint16_t pix_clk_div; uint32_t sys_clk_freq_hz; @@ -48,18 +55,26 @@ struct ccs_pll { uint32_t ext_clk_freq_hz; /* output values */ - uint16_t pre_pll_clk_div; - uint16_t pll_multiplier; - uint32_t pll_ip_clk_freq_hz; - uint32_t pll_op_clk_freq_hz; - struct ccs_pll_branch vt; - struct ccs_pll_branch op; + struct ccs_pll_branch_fr vt_fr; + struct ccs_pll_branch_bk vt_bk; + struct ccs_pll_branch_bk op_bk; uint32_t pixel_rate_csi; uint32_t pixel_rate_pixel_array; }; -struct ccs_pll_branch_limits { +struct ccs_pll_branch_limits_fr { + uint16_t min_pre_pll_clk_div; + uint16_t max_pre_pll_clk_div; + uint32_t min_pll_ip_clk_freq_hz; + uint32_t max_pll_ip_clk_freq_hz; + uint16_t min_pll_multiplier; + uint16_t max_pll_multiplier; + uint32_t min_pll_op_clk_freq_hz; + uint32_t max_pll_op_clk_freq_hz; +}; + +struct ccs_pll_branch_limits_bk { uint16_t min_sys_clk_div; uint16_t max_sys_clk_div; uint32_t min_sys_clk_freq_hz; @@ -74,17 +89,10 @@ struct ccs_pll_limits { /* Strict PLL limits */ uint32_t min_ext_clk_freq_hz; uint32_t max_ext_clk_freq_hz; - uint16_t min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div; - uint32_t min_pll_ip_freq_hz; - uint32_t max_pll_ip_freq_hz; - uint16_t min_pll_multiplier; - uint16_t max_pll_multiplier; - uint32_t min_pll_op_freq_hz; - uint32_t max_pll_op_freq_hz; - struct ccs_pll_branch_limits vt; - struct ccs_pll_branch_limits op; + struct ccs_pll_branch_limits_fr vt_fr; + struct ccs_pll_branch_limits_bk vt_bk; + struct ccs_pll_branch_limits_bk op_bk; /* Other relevant limits */ uint32_t min_line_length_pck_bin; diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index a99022e8de25..0dc1c0e05c34 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -366,67 +366,70 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) struct ccs_pll *pll = &sensor->pll; int rval; - rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div); + rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div); if (rval < 0) return rval; - rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div); + rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div); if (rval < 0) return rval; - rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); + rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div); if (rval < 0) return rval; - rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier); + rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier); if (rval < 0) return rval; /* Lane op clock ratio does not apply here. */ rval = ccs_write(sensor, REQUESTED_LINK_RATE, - DIV_ROUND_UP(pll->op.sys_clk_freq_hz, + DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, 1000000 / 256 / 256)); if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) return rval; - rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div); + rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div); if (rval < 0) return rval; - return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div); + return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div); } static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll) { struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); struct ccs_pll_limits lim = { - .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV), - .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV), - .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ), - .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ), - .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER), - .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER), - .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ), - .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ), - - .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV), - .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV), - .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV), - .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV), - .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ), - .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ), - .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ), - .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ), - - .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV), - .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV), - .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV), - .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV), - .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ), - .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ), - .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ), - .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ), - + .vt_fr = { + .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV), + .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV), + .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ), + .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ), + .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER), + .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER), + .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ), + .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ), + }, + .op_bk = { + .min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV), + .max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV), + .min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV), + .max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV), + .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ), + .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ), + .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ), + .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ), + }, + .vt_bk = { + .min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV), + .max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV), + .min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV), + .max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV), + .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ), + .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ), + .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ), + .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ), + }, .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN), .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK), }; From patchwork Wed Sep 30 15:28:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809567 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56EC6618 for ; Wed, 30 Sep 2020 15:29:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4292E207C3 for ; Wed, 30 Sep 2020 15:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731006AbgI3P3w (ORCPT ); Wed, 30 Sep 2020 11:29:52 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730994AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 0943D634C96 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 052/100] ccs-pll: Use correct VT divisor for calculating VT SYS divisor Date: Wed, 30 Sep 2020 18:28:10 +0300 Message-Id: <20200930152858.8471-53-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the correct video timing divisor to calculate the SYS divisor. Instead of the current value, the minimum was used. This could have resulted in a too low SYS divisor. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index dd30949efb6b..a2cc961366c3 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -365,14 +365,14 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, /* Check if this one is better. */ if (pix_div * sys_div - <= roundup(min_vt_div, best_pix_div)) + <= roundup(vt_div, best_pix_div)) best_pix_div = pix_div; } if (best_pix_div < INT_MAX >> 1) break; } - pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); + pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div); pll->vt_bk.pix_clk_div = best_pix_div; pll->vt_bk.sys_clk_freq_hz = From patchwork Wed Sep 30 15:28:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D351213B2 for ; Wed, 30 Sep 2020 15:29:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BEF5120789 for ; Wed, 30 Sep 2020 15:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731131AbgI3P3v (ORCPT ); Wed, 30 Sep 2020 11:29:51 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730996AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 19EA1634CA1 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 053/100] ccs-pll: End search if there are no better values available Date: Wed, 30 Sep 2020 18:28:11 +0300 Message-Id: <20200930152858.8471-54-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The VT divisor search can be ended if we've already found the value that corresponds exactly the total divisor, as there are no better (lower) values available. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index a2cc961366c3..7ee1af198972 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -352,6 +352,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, sys_div <= max_sys_div; sys_div += 2 - (sys_div & 1)) { uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); + uint16_t rounded_div; if (pix_div < lim->vt_bk.min_pix_clk_div || pix_div > lim->vt_bk.max_pix_clk_div) { @@ -363,10 +364,15 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, continue; } + rounded_div = roundup(vt_div, best_pix_div); + /* Check if this one is better. */ - if (pix_div * sys_div - <= roundup(vt_div, best_pix_div)) + if (pix_div * sys_div <= rounded_div) best_pix_div = pix_div; + + /* Bail out if we've already found the best value. */ + if (vt_div == rounded_div) + break; } if (best_pix_div < INT_MAX >> 1) break; From patchwork Wed Sep 30 15:28:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809575 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94241618 for ; Wed, 30 Sep 2020 15:29:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77C19207C3 for ; Wed, 30 Sep 2020 15:29:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731136AbgI3P3z (ORCPT ); Wed, 30 Sep 2020 11:29:55 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730998AbgI3P3K (ORCPT ); Wed, 30 Sep 2020 11:29:10 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 28A3D634C97 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 054/100] ccs-pll: Remove parallel bus support Date: Wed, 30 Sep 2020 18:28:12 +0300 Message-Id: <20200930152858.8471-55-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The parallel bus PLL calculation has no users. Remove it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 5 ----- drivers/media/i2c/ccs-pll.h | 14 ++++---------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 7ee1af198972..61ace70852e0 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -435,11 +435,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2 * (pll->csi2.lanes / lane_op_clock_ratio); break; - case CCS_PLL_BUS_TYPE_PARALLEL: - op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel - / DIV_ROUND_UP(pll->bits_per_pixel, - pll->parallel.bus_width); - break; default: return -EINVAL; } diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 03b1d8d11423..578c9272688a 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -13,8 +13,7 @@ #define CCS_PLL_H /* CSI-2 or CCP-2 */ -#define CCS_PLL_BUS_TYPE_CSI2 0x00 -#define CCS_PLL_BUS_TYPE_PARALLEL 0x01 +#define CCS_PLL_BUS_TYPE_CSI2 0x00 /* op pix clock is for all lanes in total normally */ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) @@ -37,14 +36,9 @@ struct ccs_pll_branch_bk { struct ccs_pll { /* input values */ uint8_t bus_type; - union { - struct { - uint8_t lanes; - } csi2; - struct { - uint8_t bus_width; - } parallel; - }; + struct { + uint8_t lanes; + } csi2; unsigned long flags; uint8_t binning_horizontal; uint8_t binning_vertical; From patchwork Wed Sep 30 15:28:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90E9392C for ; Wed, 30 Sep 2020 15:29:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7ED2520789 for ; Wed, 30 Sep 2020 15:29:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731132AbgI3P3w (ORCPT ); Wed, 30 Sep 2020 11:29:52 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730999AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 396EE634CDE for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 055/100] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Date: Wed, 30 Sep 2020 18:28:13 +0300 Message-Id: <20200930152858.8471-56-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include support for C-PHY. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 2 +- drivers/media/i2c/ccs-pll.h | 3 ++- drivers/media/i2c/ccs/ccs-core.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 61ace70852e0..069f2ee821fe 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -430,7 +430,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->binning_vertical); switch (pll->bus_type) { - case CCS_PLL_BUS_TYPE_CSI2: + case CCS_PLL_BUS_TYPE_CSI2_DPHY: /* CSI transfers 2 bits per clock per lane; thus times 2 */ op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2 * (pll->csi2.lanes / lane_op_clock_ratio); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 578c9272688a..d06a80c4fc52 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -13,7 +13,8 @@ #define CCS_PLL_H /* CSI-2 or CCP-2 */ -#define CCS_PLL_BUS_TYPE_CSI2 0x00 +#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 +#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 /* op pix clock is for all lanes in total normally */ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 0dc1c0e05c34..adf9c3e06567 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3179,7 +3179,7 @@ static int ccs_probe(struct i2c_client *client) sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN); /* prepare PLL configuration input values */ - sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2; + sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY; sensor->pll.csi2.lanes = sensor->hwcfg.lanes; sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809547 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65120618 for ; Wed, 30 Sep 2020 15:29:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53BBE20789 for ; Wed, 30 Sep 2020 15:29:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731023AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731001AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 486B7634CDF for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 056/100] ccs-pll: Move the flags field down, away from 8-bit fields Date: Wed, 30 Sep 2020 18:28:14 +0300 Message-Id: <20200930152858.8471-57-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This way the struct will use less memory, with better packing and no waste due to unsigned long. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index d06a80c4fc52..1d908b23c934 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -40,12 +40,12 @@ struct ccs_pll { struct { uint8_t lanes; } csi2; - unsigned long flags; uint8_t binning_horizontal; uint8_t binning_vertical; uint8_t scale_m; uint8_t scale_n; uint8_t bits_per_pixel; + uint16_t flags; uint32_t link_freq; uint32_t ext_clk_freq_hz; From patchwork Wed Sep 30 15:28:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9217E174A for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8014020789 for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731018AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731003AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 578B8634CE0 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 057/100] ccs-pll: Document the structs in the header as well as the function Date: Wed, 30 Sep 2020 18:28:15 +0300 Message-Id: <20200930152858.8471-58-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CCS pll is used by the CCS driver at the moment, but documenting the interface makes sense. It's non-trivial and the calculator could be used elsewhere. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.h | 88 +++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 1d908b23c934..e01359f61476 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -20,6 +20,16 @@ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) #define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) +/** + * struct ccs_pll_branch_fr - CCS PLL configuration (front) + * + * A single branch front-end of the CCS PLL tree. + * + * @pre_pll_clk_div: Pre-PLL clock divisor + * @pll_multiplier: PLL multiplier + * @pll_ip_freq_hz: PLL input clock frequency + * @pll_op_freq_hz: PLL output clock frequency + */ struct ccs_pll_branch_fr { uint16_t pre_pll_clk_div; uint16_t pll_multiplier; @@ -27,6 +37,16 @@ struct ccs_pll_branch_fr { uint32_t pll_op_clk_freq_hz; }; +/** + * struct ccs_pll_branch_bk - CCS PLL configuration (back) + * + * A single branch back-end of the CCS PLL tree. + * + * @sys_clk_div: System clock divider + * @pix_clk_div: Pixel clock divider + * @sys_clk_freq_hz: System clock frequency + * @pix_clk_freq_hz: Pixel clock frequency + */ struct ccs_pll_branch_bk { uint16_t sys_clk_div; uint16_t pix_clk_div; @@ -34,6 +54,29 @@ struct ccs_pll_branch_bk { uint32_t pix_clk_freq_hz; }; +/** + * struct ccs_pll - Full CCS PLL configuration + * + * All information required to calculate CCS PLL configuration. + * + * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) + * @csi2.lanes: The number of the CSI-2 data lanes (input) + * @binning_vertical: Vertical binning factor (input) + * @binning_horizontal: Horizontal binning factor (input) + * @scale_m: Downscaling factor, M component, [16, max] (input) + * @scale_n: Downscaling factor, N component, typically 16 (input) + * @bits_per_pixel: Bits per pixel on the output data bus (input) + * @flags: CCS_PLL_FLAG_* (input) + * @link_freq: Chosen link frequency (input) + * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock + * (input) + * @vt_fr: Video timing front-end configuration (output) + * @vt_bk: Video timing back-end configuration (output) + * @op_bk: Operational timing back-end configuration (output) + * @pixel_rate_csi: Pixel rate on the output data bus (output) + * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array + * (output) + */ struct ccs_pll { /* input values */ uint8_t bus_type; @@ -58,6 +101,18 @@ struct ccs_pll { uint32_t pixel_rate_pixel_array; }; +/** + * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits + * + * @min_pre_pll_clk_div: Minimum pre-PLL clock divider + * @max_pre_pll_clk_div: Maximum pre-PLL clock divider + * @min_pll_ip_freq_hz: Minimum PLL input clock frequency + * @max_pll_ip_freq_hz: Maximum PLL input clock frequency + * @min_pll_multiplier: Minimum PLL multiplier + * @max_pll_multiplier: Maximum PLL multiplier + * @min_pll_op_freq_hz: Minimum PLL output clock frequency + * @max_pll_op_freq_hz: Maximum PLL output clock frequency + */ struct ccs_pll_branch_limits_fr { uint16_t min_pre_pll_clk_div; uint16_t max_pre_pll_clk_div; @@ -69,6 +124,18 @@ struct ccs_pll_branch_limits_fr { uint32_t max_pll_op_clk_freq_hz; }; +/** + * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits + * + * @min_sys_clk_div: Minimum system clock divider + * @max_sys_clk_div: Maximum system clock divider + * @min_sys_clk_freq_hz: Minimum system clock frequency + * @max_sys_clk_freq_hz: Maximum system clock frequency + * @min_pix_clk_div: Minimum pixel clock divider + * @max_pix_clk_div: Maximum pixel clock divider + * @min_pix_clk_freq_hz: Minimum pixel clock frequency + * @max_pix_clk_freq_hz: Maximum pixel clock frequency + */ struct ccs_pll_branch_limits_bk { uint16_t min_sys_clk_div; uint16_t max_sys_clk_div; @@ -80,6 +147,17 @@ struct ccs_pll_branch_limits_bk { uint32_t max_pix_clk_freq_hz; }; +/** + * struct ccs_pll_limits - CCS PLL limits + * + * @min_ext_clk_freq_hz: Minimum external clock frequency + * @max_ext_clk_freq_hz: Maximum external clock frequency + * @vt_fr: Video timing front-end limits + * @vt_bk: Video timing back-end limits + * @op_bk: Operational timing back-end limits + * @min_line_length_pck_bin: Minimum line length in pixels, with binning + * @min_line_length_pck: Minimum line length in pixels without binning + */ struct ccs_pll_limits { /* Strict PLL limits */ uint32_t min_ext_clk_freq_hz; @@ -96,6 +174,16 @@ struct ccs_pll_limits { struct device; +/** + * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters + * + * @dev: Device pointer, used for printing messages + * @limits: Limits specific to the sensor + * @pll: Given PLL configuration + * + * Calculate the CCS PLL configuration based on the limits as well as given + * device specific, system specific or user configured input data. + */ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, struct ccs_pll *pll); From patchwork Wed Sep 30 15:28:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809471 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CF0E92C for ; Wed, 30 Sep 2020 15:29:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48E0F20789 for ; Wed, 30 Sep 2020 15:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731032AbgI3P3N (ORCPT ); Wed, 30 Sep 2020 11:29:13 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731005AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 68462634CE1 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 058/100] ccs-pll: Use the BIT macro Date: Wed, 30 Sep 2020 18:28:16 +0300 Message-Id: <20200930152858.8471-59-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the BIT macro for setting individual bits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index e01359f61476..f772ed8ef579 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -12,13 +12,16 @@ #ifndef CCS_PLL_H #define CCS_PLL_H +#include + /* CSI-2 or CCP-2 */ #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 +/* Old SMIA and implementation specific flags */ /* op pix clock is for all lanes in total normally */ -#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) -#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) +#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) +#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) From patchwork Wed Sep 30 15:28:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7C6592C for ; Wed, 30 Sep 2020 15:29:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9D93207FB for ; Wed, 30 Sep 2020 15:29:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731113AbgI3P3o (ORCPT ); Wed, 30 Sep 2020 11:29:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730871AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57832C061755 for ; Wed, 30 Sep 2020 08:29:12 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 76EDC634CE3 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 059/100] ccs-pll: Begin calculation from OP system clock frequency Date: Wed, 30 Sep 2020 18:28:17 +0300 Message-Id: <20200930152858.8471-60-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The OP system clock frequency defines the CSI-2 bus clock frequency, not the PLL output clock frequency. Both values were overwritten in the end, but the wrong limit value was used for the OP system clock frequency, possibly leading to too high frequencies being used. Also remove now duplicated calculation of OP system clock frequency later in the PLL calculator. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 069f2ee821fe..9bcf682b40fb 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -247,10 +247,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz * op_pll_fr->pll_multiplier; - /* Derive pll_op_clk_freq_hz. */ - op_pll_bk->sys_clk_freq_hz = - op_pll_fr->pll_op_clk_freq_hz / op_pll_bk->sys_clk_div; - op_pll_bk->pix_clk_div = pll->bits_per_pixel; dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); @@ -432,7 +428,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, switch (pll->bus_type) { case CCS_PLL_BUS_TYPE_CSI2_DPHY: /* CSI transfers 2 bits per clock per lane; thus times 2 */ - op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2 + op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 * (pll->csi2.lanes / lane_op_clock_ratio); break; default: @@ -454,8 +450,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); - i = gcd(op_pll_fr->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); - mul = op_pll_fr->pll_op_clk_freq_hz / i; + i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz); + mul = op_pll_bk->sys_clk_freq_hz / i; div = pll->ext_clk_freq_hz / i; dev_dbg(dev, "mul %u / div %u\n", mul, div); @@ -463,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, max_t(uint16_t, min_op_pre_pll_clk_div, clk_div_even_up( DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, - op_lim_fr->max_pll_op_clk_freq_hz))); + op_lim_bk->max_sys_clk_freq_hz))); dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); From patchwork Wed Sep 30 15:28:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 425D3618 for ; Wed, 30 Sep 2020 15:29:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D5F320789 for ; Wed, 30 Sep 2020 15:29:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731130AbgI3P3v (ORCPT ); Wed, 30 Sep 2020 11:29:51 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730931AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 86625634CE4 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 060/100] ccs-pll: Fix condition for pre-PLL divider lower bound Date: Wed, 30 Sep 2020 18:28:18 +0300 Message-Id: <20200930152858.8471-61-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The lower bound of the pre-PLL divider was calculated based on OP SYS clock frequency which is also affected by the OP SYS clock divider. This is wrong. The right clock frequency is that of the PLL output clock. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 9bcf682b40fb..53dd440668ed 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -459,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, max_t(uint16_t, min_op_pre_pll_clk_div, clk_div_even_up( DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, - op_lim_bk->max_sys_clk_freq_hz))); + op_lim_fr->max_pll_op_clk_freq_hz))); dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); From patchwork Wed Sep 30 15:28:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C00F618 for ; Wed, 30 Sep 2020 15:29:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85C2E2087D for ; Wed, 30 Sep 2020 15:29:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731022AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731007AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 9537B634CE6 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 061/100] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search Date: Wed, 30 Sep 2020 18:28:19 +0300 Message-Id: <20200930152858.8471-62-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The external clock frequency times the PLL multiplier may exceed the value range of 32-bit unsigned integers. Instead perform the same calculation y using two divisions. The result has some potential to be different, but that's ok: this number is used to limit the range of pre-PLL divisors to find optimal values. So the effect of the rare case of a different result here would mean an invalid pre-PLL divisor is tried. That will be found out a little later in any case. Also guard against dividing by zero if the external clock frequency is higher than the maximum OP PLL output clock --- a rather improbable case. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 53dd440668ed..c132edc6a06a 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -40,6 +40,11 @@ static inline uint32_t is_one_or_even(uint32_t a) return 1; } +static inline uint32_t one_or_more(uint32_t a) +{ + return a ?: 1; +} + static int bounds_check(struct device *dev, uint32_t val, uint32_t min, uint32_t max, char *str) { @@ -458,8 +463,10 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, min_op_pre_pll_clk_div = max_t(uint16_t, min_op_pre_pll_clk_div, clk_div_even_up( - DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, - op_lim_fr->max_pll_op_clk_freq_hz))); + mul / + one_or_more( + DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz, + pll->ext_clk_freq_hz)))); dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); From patchwork Wed Sep 30 15:28:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809555 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2713D618 for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F7AD20789 for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731128AbgI3P3t (ORCPT ); Wed, 30 Sep 2020 11:29:49 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44682 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731009AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A5405634CE7 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 062/100] ccs-pll: Fix comment on check against maximum PLL multiplier Date: Wed, 30 Sep 2020 18:28:20 +0300 Message-Id: <20200930152858.8471-63-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The comment is about minimum PLL multiplier but the related check really deals with the maximum PLL multiplier. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index c132edc6a06a..0e474ca65712 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -203,7 +203,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, / div); dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", more_mul_max); - /* Ensure we won't go above min_pll_multiplier. */ + /* Ensure we won't go above max_pll_multiplier. */ more_mul_max = min(more_mul_max, DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", From patchwork Wed Sep 30 15:28:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FDD992C for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F6E5208B8 for ; Wed, 30 Sep 2020 15:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730633AbgI3P3t (ORCPT ); Wed, 30 Sep 2020 11:29:49 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730856AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id B4BCD634CE8 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 063/100] ccs-pll: Fix check for PLL multiplier upper bound Date: Wed, 30 Sep 2020 18:28:21 +0300 Message-Id: <20200930152858.8471-64-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 0e474ca65712..c4230c082078 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -204,8 +204,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", more_mul_max); /* Ensure we won't go above max_pll_multiplier. */ - more_mul_max = min(more_mul_max, - DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); + more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", more_mul_max); From patchwork Wed Sep 30 15:28:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27ECC618 for ; Wed, 30 Sep 2020 15:29:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1337620789 for ; Wed, 30 Sep 2020 15:29:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731107AbgI3P3n (ORCPT ); Wed, 30 Sep 2020 11:29:43 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731010AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id C855E634CEA for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 064/100] ccs-pll: Use explicit 32-bit unsigned type Date: Wed, 30 Sep 2020 18:28:22 +0300 Message-Id: <20200930152858.8471-65-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use uint32_t instead of unsigned int for a variable that contains explicitly 32-bit numbers. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index c4230c082078..6c77a5886954 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -177,7 +177,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, uint32_t more_mul_factor; uint32_t min_vt_div, max_vt_div, vt_div; uint32_t min_sys_div, max_sys_div; - unsigned int i; + uint32_t i; /* * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be @@ -406,7 +406,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, uint16_t max_op_pre_pll_clk_div; uint32_t lane_op_clock_ratio; uint32_t mul, div; - unsigned int i; + uint32_t i; int rval = -EINVAL; if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { From patchwork Wed Sep 30 15:28:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809541 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D328618 for ; Wed, 30 Sep 2020 15:29:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B47520888 for ; Wed, 30 Sep 2020 15:29:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731030AbgI3P3k (ORCPT ); Wed, 30 Sep 2020 11:29:40 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731012AbgI3P3N (ORCPT ); Wed, 30 Sep 2020 11:29:13 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id D8CC8634CCC for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 065/100] ccs-pll: Add support for lane speed model Date: Wed, 30 Sep 2020 18:28:23 +0300 Message-Id: <20200930152858.8471-66-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CCS PLL includes a capability to calculate the VT clocks on per-lane basis. Add support for this feature. Move calculation of the pixel rate on the CSI-2 bus early in the function as everything needed to calculate it is already available. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 36 +++++++++++++++++++++++++----------- drivers/media/i2c/ccs-pll.h | 6 ++++++ 2 files changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 6c77a5886954..c8222ee29421 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -251,11 +251,12 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz * op_pll_fr->pll_multiplier; - op_pll_bk->pix_clk_div = pll->bits_per_pixel; - dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); - + op_pll_bk->pix_clk_div = pll->bits_per_pixel + * pll->op_lanes / pll->csi2.lanes; op_pll_bk->pix_clk_freq_hz = op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; + dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* No OP clocks --- VT clocks are used instead. */ @@ -283,15 +284,16 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * divisors. One must make sure that horizontal blanking is * enough to accommodate the CSI-2 sync codes. * - * Take scaling factor into account as well. + * Take scaling factor and number of VT lanes into account as well. * * Find absolute limits for the factor of vt divider. */ dev_dbg(dev, "scale_m: %u\n", pll->scale_m); min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div - * op_pll_bk->sys_clk_div * pll->scale_n, - lane_op_clock_ratio * vt_op_binning_div - * pll->scale_m); + * op_pll_bk->sys_clk_div * pll->scale_n + * pll->vt_lanes, + pll->op_lanes * vt_op_binning_div + * pll->scale_m * lane_op_clock_ratio); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); @@ -387,9 +389,8 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; out_skip_vt_calc: - pll->pixel_rate_csi = - op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio; - pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz; + pll->pixel_rate_pixel_array = + pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, op_pll_bk); @@ -409,6 +410,13 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, uint32_t i; int rval = -EINVAL; + if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) { + pll->op_lanes = 1; + pll->vt_lanes = 1; + } + dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); + dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* * If there's no OP PLL at all, use the VT values @@ -433,12 +441,18 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, case CCS_PLL_BUS_TYPE_CSI2_DPHY: /* CSI transfers 2 bits per clock per lane; thus times 2 */ op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 - * (pll->csi2.lanes / lane_op_clock_ratio); + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + 1 : pll->csi2.lanes) / lane_op_clock_ratio; break; default: return -EINVAL; } + pll->pixel_rate_csi = + op_pll_bk->pix_clk_freq_hz + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + pll->csi2.lanes : 1) * lane_op_clock_ratio; + /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index f772ed8ef579..57308b8f3a8a 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -22,6 +22,8 @@ /* op pix clock is for all lanes in total normally */ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) +/* CCS PLL flags */ +#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) @@ -63,6 +65,8 @@ struct ccs_pll_branch_bk { * All information required to calculate CCS PLL configuration. * * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) + * @op_lanes: Number of operational lanes (input) + * @vt_lanes: Number of video timing lanes (input) * @csi2.lanes: The number of the CSI-2 data lanes (input) * @binning_vertical: Vertical binning factor (input) * @binning_horizontal: Horizontal binning factor (input) @@ -83,6 +87,8 @@ struct ccs_pll_branch_bk { struct ccs_pll { /* input values */ uint8_t bus_type; + uint8_t op_lanes; + uint8_t vt_lanes; struct { uint8_t lanes; } csi2; From patchwork Wed Sep 30 15:28:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809545 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 86C4392C for ; Wed, 30 Sep 2020 15:29:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7252720888 for ; Wed, 30 Sep 2020 15:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731106AbgI3P3l (ORCPT ); Wed, 30 Sep 2020 11:29:41 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731013AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id EDAD5634CEB for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 066/100] ccs: Add support for lane speed model Date: Wed, 30 Sep 2020 18:28:24 +0300 Message-Id: <20200930152858.8471-67-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Convey the relevant PLL flags to the PLL calculator. Also the lane speed model affects how the link rate is calculated on the CSI-2 bus, as the rate is total of all lanes. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index adf9c3e06567..3250cca45a90 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -385,7 +385,9 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) /* Lane op clock ratio does not apply here. */ rval = ccs_write(sensor, REQUESTED_LINK_RATE, DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, - 1000000 / 256 / 256)); + 1000000 / 256 / 256) * + (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + sensor->pll.csi2.lanes : 1)); if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) return rval; @@ -3181,6 +3183,13 @@ static int ccs_probe(struct i2c_client *client) /* prepare PLL configuration input values */ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY; sensor->pll.csi2.lanes = sensor->hwcfg.lanes; + if (CCS_LIM(sensor, CLOCK_CALCULATION) & + CCS_CLOCK_CALCULATION_LANE_SPEED) { + sensor->pll.vt_lanes = + CCS_LIM(sensor, NUM_OF_VT_LANES) + 1; + sensor->pll.op_lanes = sensor->pll.vt_lanes; + sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL; + } sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809535 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10CFA13B2 for ; Wed, 30 Sep 2020 15:29:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 019E920789 for ; Wed, 30 Sep 2020 15:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731043AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731014AbgI3P3N (ORCPT ); Wed, 30 Sep 2020 11:29:13 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 0C340634CEC for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 067/100] ccs-pll: Add support for decoupled OP domain calculation Date: Wed, 30 Sep 2020 18:28:25 +0300 Message-Id: <20200930152858.8471-68-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for decoupled OP domain clock calculation. This means that the number of VT and OP domain clocks are no longer dependent on the number of CSI-2 lanes in the lane speed mode. The support also replaces the existing quirk flag to calculate OP domain clocks per lane. Also support decoupled OP domain calculation in the CCS driver. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 22 +++++++--------------- drivers/media/i2c/ccs-pll.h | 1 + drivers/media/i2c/ccs/ccs-core.c | 14 +++++++++++--- drivers/media/i2c/ccs/ccs-quirk.c | 5 ++++- 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index c8222ee29421..c95a03ffce59 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -162,7 +162,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t lane_op_clock_ratio) + uint32_t div) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -194,7 +194,8 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, min_t(uint32_t, more_mul_max, op_lim_fr->max_pll_op_clk_freq_hz - / (pll->ext_clk_freq_hz / op_pll_fr->pre_pll_clk_div * mul)); + / (pll->ext_clk_freq_hz / + op_pll_fr->pre_pll_clk_div * mul)); dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", more_mul_max); /* Don't go above the division capability of op sys clock divider. */ @@ -257,7 +258,6 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); - if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { /* No OP clocks --- VT clocks are used instead. */ goto out_skip_vt_calc; @@ -293,7 +293,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * op_pll_bk->sys_clk_div * pll->scale_n * pll->vt_lanes, pll->op_lanes * vt_op_binning_div - * pll->scale_m * lane_op_clock_ratio); + * pll->scale_m); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); @@ -405,7 +405,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; uint16_t min_op_pre_pll_clk_div; uint16_t max_op_pre_pll_clk_div; - uint32_t lane_op_clock_ratio; uint32_t mul, div; uint32_t i; int rval = -EINVAL; @@ -428,12 +427,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_bk = &pll->vt_bk; } - if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) - lane_op_clock_ratio = pll->csi2.lanes; - else - lane_op_clock_ratio = 1; - dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio); - dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, pll->binning_vertical); @@ -442,7 +435,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, /* CSI transfers 2 bits per clock per lane; thus times 2 */ op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - 1 : pll->csi2.lanes) / lane_op_clock_ratio; + 1 : pll->csi2.lanes); break; default: return -EINVAL; @@ -451,7 +444,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->pixel_rate_csi = op_pll_bk->pix_clk_freq_hz * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1) * lane_op_clock_ratio; + pll->csi2.lanes : 1); /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", @@ -487,8 +480,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div, - lane_op_clock_ratio); + op_pll_fr, op_pll_bk, mul, div); if (rval) continue; diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 57308b8f3a8a..165de20af079 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -24,6 +24,7 @@ #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) /* CCS PLL flags */ #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) +#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 3250cca45a90..8b328ade055c 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3185,10 +3185,18 @@ static int ccs_probe(struct i2c_client *client) sensor->pll.csi2.lanes = sensor->hwcfg.lanes; if (CCS_LIM(sensor, CLOCK_CALCULATION) & CCS_CLOCK_CALCULATION_LANE_SPEED) { - sensor->pll.vt_lanes = - CCS_LIM(sensor, NUM_OF_VT_LANES) + 1; - sensor->pll.op_lanes = sensor->pll.vt_lanes; sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL; + if (CCS_LIM(sensor, CLOCK_CALCULATION) & + CCS_CLOCK_CALCULATION_LINK_DECOUPLED) { + sensor->pll.vt_lanes = + CCS_LIM(sensor, NUM_OF_VT_LANES) + 1; + sensor->pll.op_lanes = + CCS_LIM(sensor, NUM_OF_OP_LANES) + 1; + sensor->pll.flags |= CCS_PLL_FLAG_LINK_DECOUPLED; + } else { + sensor->pll.vt_lanes = sensor->pll.csi2.lanes; + sensor->pll.op_lanes = sensor->pll.csi2.lanes; + } } sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c index 4fe8c6f70579..e3d4c7a275bc 100644 --- a/drivers/media/i2c/ccs/ccs-quirk.c +++ b/drivers/media/i2c/ccs/ccs-quirk.c @@ -190,7 +190,10 @@ static int jt8ev1_post_streamoff(struct ccs_sensor *sensor) static int jt8ev1_init(struct ccs_sensor *sensor) { - sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE; + sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL | + CCS_PLL_FLAG_LINK_DECOUPLED; + sensor->pll.vt_lanes = 1; + sensor->pll.op_lanes = sensor->pll.csi2.lanes; return 0; } From patchwork Wed Sep 30 15:28:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809543 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F3C813B2 for ; Wed, 30 Sep 2020 15:29:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7815E20789 for ; Wed, 30 Sep 2020 15:29:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731012AbgI3P3l (ORCPT ); Wed, 30 Sep 2020 11:29:41 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731016AbgI3P3M (ORCPT ); Wed, 30 Sep 2020 11:29:12 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 24272634CED for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 068/100] ccs-pll: Add support for extended input PLL clock divider Date: Wed, 30 Sep 2020 18:28:26 +0300 Message-Id: <20200930152858.8471-69-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 4 +++- drivers/media/i2c/ccs-pll.h | 1 + drivers/media/i2c/ccs/ccs-core.c | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index c95a03ffce59..ace2c2f352a9 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -478,7 +478,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; - op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) { + op_pll_fr->pre_pll_clk_div += + (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : + 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, op_pll_bk, mul, div); if (rval) diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 165de20af079..7c2b7a85de6a 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -25,6 +25,7 @@ /* CCS PLL flags */ #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) +#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 8b328ade055c..5f361eec2006 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3198,6 +3198,9 @@ static int ccs_probe(struct i2c_client *client) sensor->pll.op_lanes = sensor->pll.csi2.lanes; } } + if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & + CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER) + sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER; sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809475 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02B7592C for ; Wed, 30 Sep 2020 15:29:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFB5E2085B for ; Wed, 30 Sep 2020 15:29:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731052AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731003AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 38B13634CA4 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 069/100] ccs-pll: Support two cycles per pixel on OP domain Date: Wed, 30 Sep 2020 18:28:27 +0300 Message-Id: <20200930152858.8471-70-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The l parameter defines the number of clock cycles to process a single pixel per OP lane. It is calculated based on a new register op_bits_per_lane. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 19 +++++++++++++------ drivers/media/i2c/ccs-pll.h | 2 ++ drivers/media/i2c/ccs/ccs-core.c | 1 + 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index ace2c2f352a9..8996f30c1e3b 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -162,7 +162,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div) + uint32_t div, uint32_t l) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -252,10 +252,15 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz * op_pll_fr->pll_multiplier; - op_pll_bk->pix_clk_div = pll->bits_per_pixel - * pll->op_lanes / pll->csi2.lanes; + if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) + op_pll_bk->pix_clk_div = pll->bits_per_pixel + * pll->op_lanes / pll->csi2.lanes / l; + else + op_pll_bk->pix_clk_div = pll->bits_per_pixel / l; + op_pll_bk->pix_clk_freq_hz = op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; + dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { @@ -291,7 +296,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "scale_m: %u\n", pll->scale_m); min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div * op_pll_bk->sys_clk_div * pll->scale_n - * pll->vt_lanes, + * pll->vt_lanes * l, pll->op_lanes * vt_op_binning_div * pll->scale_m); @@ -406,6 +411,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, uint16_t min_op_pre_pll_clk_div; uint16_t max_op_pre_pll_clk_div; uint32_t mul, div; + uint32_t l = (!pll->op_bits_per_lane || + pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; uint32_t i; int rval = -EINVAL; @@ -444,7 +451,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->pixel_rate_csi = op_pll_bk->pix_clk_freq_hz * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1); + pll->csi2.lanes : 1) / l; /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", @@ -482,7 +489,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div); + op_pll_fr, op_pll_bk, mul, div, l); if (rval) continue; diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 7c2b7a85de6a..dd97cd6dca0d 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -75,6 +75,7 @@ struct ccs_pll_branch_bk { * @scale_m: Downscaling factor, M component, [16, max] (input) * @scale_n: Downscaling factor, N component, typically 16 (input) * @bits_per_pixel: Bits per pixel on the output data bus (input) + * @op_bits_per_lane: Number of bits per OP lane (input) * @flags: CCS_PLL_FLAG_* (input) * @link_freq: Chosen link frequency (input) * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock @@ -99,6 +100,7 @@ struct ccs_pll { uint8_t scale_m; uint8_t scale_n; uint8_t bits_per_pixel; + uint8_t op_bits_per_lane; uint16_t flags; uint32_t link_freq; uint32_t ext_clk_freq_hz; diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 5f361eec2006..7ba5e7b0f2f7 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3201,6 +3201,7 @@ static int ccs_probe(struct i2c_client *client) if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER) sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER; + sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809531 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54E1A92C for ; Wed, 30 Sep 2020 15:29:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 44E8B207FB for ; Wed, 30 Sep 2020 15:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731036AbgI3P3h (ORCPT ); Wed, 30 Sep 2020 11:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731014AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from hillosipuli.retiisi.eu (hillosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::81:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F8A3C061755 for ; Wed, 30 Sep 2020 08:29:14 -0700 (PDT) Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 41DED634C98 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 070/100] ccs-pll: Add support flexible OP PLL pixel clock divider Date: Wed, 30 Sep 2020 18:28:28 +0300 Message-Id: <20200930152858.8471-71-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Flexible OP PLL pixel clock divider allows a higher OP pixel clock than what the bus can transfer. This generally makes it easier to select pixel clock dividers. This changes how the pixel rate on the bus and minimum VT divisor are calculated, as the pixel rate is no longer directly determined by the OP pixel clock and the number of the lanes. Also add a sanity check for sensors that do not support flexible OP PLL pixel clock divider. This could have caused the PLL calculator to come up with an invalid configuration for those devices. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 26 +++++++++++++++++++------- drivers/media/i2c/ccs-pll.h | 1 + drivers/media/i2c/ccs/ccs-core.c | 4 +++- 3 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 8996f30c1e3b..84f1735b8df5 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -294,11 +294,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * Find absolute limits for the factor of vt divider. */ dev_dbg(dev, "scale_m: %u\n", pll->scale_m); - min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div - * op_pll_bk->sys_clk_div * pll->scale_n - * pll->vt_lanes * l, - pll->op_lanes * vt_op_binning_div - * pll->scale_m); + min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div + * pll->scale_n * pll->vt_lanes, + (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + pll->csi2.lanes : 1) + * vt_op_binning_div * pll->scale_m); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); @@ -420,6 +420,18 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->op_lanes = 1; pll->vt_lanes = 1; } + + /* + * Make sure op_pix_clk_div will be integer --- unless flexible + * op_pix_clk_div is supported + */ + if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) && + (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) { + dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n", + pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l); + return -EINVAL; + } + dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); @@ -449,9 +461,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, } pll->pixel_rate_csi = - op_pll_bk->pix_clk_freq_hz + op_pll_bk->sys_clk_freq_hz * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1) / l; + pll->csi2.lanes : 1) / pll->bits_per_pixel / l; /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index dd97cd6dca0d..0c25c5f5d4e4 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -26,6 +26,7 @@ #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) +#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 7ba5e7b0f2f7..5d0011e51913 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -30,7 +30,6 @@ #include #include "ccs.h" -#include "ccs-limits.h" #define CCS_ALIGN_DIM(dim, flags) \ ((flags) & V4L2_SEL_FLAG_GE \ @@ -3201,6 +3200,9 @@ static int ccs_probe(struct i2c_client *client) if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER) sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER; + if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & + CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV) + sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV; sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AA40618 for ; Wed, 30 Sep 2020 15:29:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57C9920789 for ; Wed, 30 Sep 2020 15:29:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731050AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731025AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 52DF9634CA3 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 071/100] ccs-pll: Add sanity checks Date: Wed, 30 Sep 2020 18:28:29 +0300 Message-Id: <20200930152858.8471-72-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add sanity checks for fields that could cause division by zero. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 84f1735b8df5..1a4fccfc1158 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -421,6 +421,15 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->vt_lanes = 1; } + if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel || + !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m || + !op_lim_fr->min_pll_ip_clk_freq_hz || + !op_lim_fr->max_pll_ip_clk_freq_hz || + !op_lim_fr->min_pll_op_clk_freq_hz || + !op_lim_fr->max_pll_op_clk_freq_hz || + !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier) + return -EINVAL; + /* * Make sure op_pix_clk_div will be integer --- unless flexible * op_pix_clk_div is supported From patchwork Wed Sep 30 15:28:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809537 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 243A2618 for ; Wed, 30 Sep 2020 15:29:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 102F920789 for ; Wed, 30 Sep 2020 15:29:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730567AbgI3P3k (ORCPT ); Wed, 30 Sep 2020 11:29:40 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44682 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731029AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 619C4634CA5 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 072/100] ccs-pll: Add C-PHY support Date: Wed, 30 Sep 2020 18:28:30 +0300 Message-Id: <20200930152858.8471-73-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add C-PHY support for the CCS PLL calculator. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 1a4fccfc1158..52e6230c087d 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -145,6 +145,10 @@ static int check_all_bounds(struct device *dev, return rval; } +#define CPHY_CONST 7 +#define DPHY_CONST 16 +#define PHY_CONST_DIV 16 + /* * Heuristically guess the PLL tree for a given common multiplier and * divisor. Begin with the operational timing and continue to video @@ -162,7 +166,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t l) + uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -254,9 +258,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) op_pll_bk->pix_clk_div = pll->bits_per_pixel - * pll->op_lanes / pll->csi2.lanes / l; + * pll->op_lanes * phy_const + / PHY_CONST_DIV / pll->csi2.lanes / l; else - op_pll_bk->pix_clk_div = pll->bits_per_pixel / l; + op_pll_bk->pix_clk_div = + pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; op_pll_bk->pix_clk_freq_hz = op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; @@ -295,10 +301,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, */ dev_dbg(dev, "scale_m: %u\n", pll->scale_m); min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div - * pll->scale_n * pll->vt_lanes, + * pll->scale_n * pll->vt_lanes * phy_const, (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? pll->csi2.lanes : 1) - * vt_op_binning_div * pll->scale_m); + * vt_op_binning_div * pll->scale_m + * PHY_CONST_DIV); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); @@ -408,6 +415,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; + bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; + uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; uint16_t min_op_pre_pll_clk_div; uint16_t max_op_pre_pll_clk_div; uint32_t mul, div; @@ -465,14 +474,21 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 1 : pll->csi2.lanes); break; + case CCS_PLL_BUS_TYPE_CSI2_CPHY: + op_pll_bk->sys_clk_freq_hz = + pll->link_freq + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + 1 : pll->csi2.lanes); + break; default: return -EINVAL; } pll->pixel_rate_csi = - op_pll_bk->sys_clk_freq_hz - * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1) / pll->bits_per_pixel / l; + div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + pll->csi2.lanes : 1) * PHY_CONST_DIV, + phy_const * pll->bits_per_pixel * l); /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", @@ -510,7 +526,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div, l); + op_pll_fr, op_pll_bk, mul, div, l, + cphy, phy_const); if (rval) continue; From patchwork Wed Sep 30 15:28:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809533 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E58C792C for ; Wed, 30 Sep 2020 15:29:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8C43207C3 for ; Wed, 30 Sep 2020 15:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731103AbgI3P3h (ORCPT ); Wed, 30 Sep 2020 11:29:37 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731030AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 764E2634C87 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 073/100] ccs-pll: Split off VT subtree calculation Date: Wed, 30 Sep 2020 18:28:31 +0300 Message-Id: <20200930152858.8471-74-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Split off the VT sub clock tree calculation from the rest, into its own function. Also call the op_pll_fr argument pll_fr, since soon these may not be OP tree values. This paves way for additional features in the future such as dual PLL support. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 255 ++++++++++++++++++------------------ 1 file changed, 131 insertions(+), 124 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 52e6230c087d..34e372b0bb84 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -149,130 +149,18 @@ static int check_all_bounds(struct device *dev, #define DPHY_CONST 16 #define PHY_CONST_DIV 16 -/* - * Heuristically guess the PLL tree for a given common multiplier and - * divisor. Begin with the operational timing and continue to video - * timing once operational timing has been verified. - * - * @mul is the PLL multiplier and @div is the common divisor - * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL - * multiplier will be a multiple of @mul. - * - * @return Zero on success, error code on error. - */ -static int -__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, - const struct ccs_pll_branch_limits_fr *op_lim_fr, - const struct ccs_pll_branch_limits_bk *op_lim_bk, - struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, - struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) +static void +__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, + struct ccs_pll_branch_bk *op_pll_bk, bool cphy, + uint32_t phy_const) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; uint32_t vt_op_binning_div; - /* - * Higher multipliers (and divisors) are often required than - * necessitated by the external clock and the output clocks. - * There are limits for all values in the clock tree. These - * are the minimum and maximum multiplier for mul. - */ - uint32_t more_mul_min, more_mul_max; - uint32_t more_mul_factor; uint32_t min_vt_div, max_vt_div, vt_div; uint32_t min_sys_div, max_sys_div; - uint32_t i; - - /* - * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be - * too high. - */ - dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); - - /* Don't go above max pll multiplier. */ - more_mul_max = op_lim_fr->max_pll_multiplier / mul; - dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", - more_mul_max); - /* Don't go above max pll op frequency. */ - more_mul_max = - min_t(uint32_t, - more_mul_max, - op_lim_fr->max_pll_op_clk_freq_hz - / (pll->ext_clk_freq_hz / - op_pll_fr->pre_pll_clk_div * mul)); - dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", - more_mul_max); - /* Don't go above the division capability of op sys clock divider. */ - more_mul_max = min(more_mul_max, - op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div - / div); - dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", - more_mul_max); - /* Ensure we won't go above max_pll_multiplier. */ - more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); - dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", - more_mul_max); - - /* Ensure we won't go below min_pll_op_clk_freq_hz. */ - more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, - pll->ext_clk_freq_hz / - op_pll_fr->pre_pll_clk_div * mul); - dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", - more_mul_min); - /* Ensure we won't go below min_pll_multiplier. */ - more_mul_min = max(more_mul_min, - DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); - dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", - more_mul_min); - - if (more_mul_min > more_mul_max) { - dev_dbg(dev, - "unable to compute more_mul_min and more_mul_max\n"); - return -EINVAL; - } - - more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; - dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); - more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); - dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", - more_mul_factor); - i = roundup(more_mul_min, more_mul_factor); - if (!is_one_or_even(i)) - i <<= 1; - - dev_dbg(dev, "final more_mul: %u\n", i); - if (i > more_mul_max) { - dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); - return -EINVAL; - } - - op_pll_fr->pll_multiplier = mul * i; - op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; - dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); - - op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz - / op_pll_fr->pre_pll_clk_div; - - op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz - * op_pll_fr->pll_multiplier; - - if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) - op_pll_bk->pix_clk_div = pll->bits_per_pixel - * pll->op_lanes * phy_const - / PHY_CONST_DIV / pll->csi2.lanes / l; - else - op_pll_bk->pix_clk_div = - pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; - - op_pll_bk->pix_clk_freq_hz = - op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; - - dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); - - if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { - /* No OP clocks --- VT clocks are used instead. */ - goto out_skip_vt_calc; - } /* * Some sensors perform analogue binning and some do this @@ -310,7 +198,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); min_vt_div = max(min_vt_div, - DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.max_pix_clk_freq_hz)); dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", min_vt_div); @@ -322,7 +210,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); max_vt_div = min(max_vt_div, - DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", max_vt_div); @@ -338,7 +226,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, lim->vt_bk.max_pix_clk_div)); dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); min_sys_div = max(min_sys_div, - op_pll_fr->pll_op_clk_freq_hz + pll_fr->pll_op_clk_freq_hz / lim->vt_bk.max_sys_clk_freq_hz); dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); min_sys_div = clk_div_even_up(min_sys_div); @@ -351,7 +239,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, lim->vt_bk.min_pix_clk_div)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); max_sys_div = min(max_sys_div, - DIV_ROUND_UP(op_pll_fr->pll_op_clk_freq_hz, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); @@ -396,11 +284,130 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->vt_bk.pix_clk_div = best_pix_div; pll->vt_bk.sys_clk_freq_hz = - op_pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; + pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; pll->vt_bk.pix_clk_freq_hz = pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; +} + +/* + * Heuristically guess the PLL tree for a given common multiplier and + * divisor. Begin with the operational timing and continue to video + * timing once operational timing has been verified. + * + * @mul is the PLL multiplier and @div is the common divisor + * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL + * multiplier will be a multiple of @mul. + * + * @return Zero on success, error code on error. + */ +static int +__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_fr *op_lim_fr, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, + struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, + uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) +{ + /* + * Higher multipliers (and divisors) are often required than + * necessitated by the external clock and the output clocks. + * There are limits for all values in the clock tree. These + * are the minimum and maximum multiplier for mul. + */ + uint32_t more_mul_min, more_mul_max; + uint32_t more_mul_factor; + uint32_t i; + + /* + * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be + * too high. + */ + dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); + + /* Don't go above max pll multiplier. */ + more_mul_max = op_lim_fr->max_pll_multiplier / mul; + dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", + more_mul_max); + /* Don't go above max pll op frequency. */ + more_mul_max = + min_t(uint32_t, + more_mul_max, + op_lim_fr->max_pll_op_clk_freq_hz + / (pll->ext_clk_freq_hz / + op_pll_fr->pre_pll_clk_div * mul)); + dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", + more_mul_max); + /* Don't go above the division capability of op sys clock divider. */ + more_mul_max = min(more_mul_max, + op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div + / div); + dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", + more_mul_max); + /* Ensure we won't go above max_pll_multiplier. */ + more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); + dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", + more_mul_max); + + /* Ensure we won't go below min_pll_op_clk_freq_hz. */ + more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, + pll->ext_clk_freq_hz / + op_pll_fr->pre_pll_clk_div * mul); + dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", + more_mul_min); + /* Ensure we won't go below min_pll_multiplier. */ + more_mul_min = max(more_mul_min, + DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); + dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", + more_mul_min); + + if (more_mul_min > more_mul_max) { + dev_dbg(dev, + "unable to compute more_mul_min and more_mul_max\n"); + return -EINVAL; + } + + more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; + dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); + more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); + dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", + more_mul_factor); + i = roundup(more_mul_min, more_mul_factor); + if (!is_one_or_even(i)) + i <<= 1; + + dev_dbg(dev, "final more_mul: %u\n", i); + if (i > more_mul_max) { + dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); + return -EINVAL; + } + + op_pll_fr->pll_multiplier = mul * i; + op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; + dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); + + op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz + / op_pll_fr->pre_pll_clk_div; + + op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz + * op_pll_fr->pll_multiplier; + + if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) + op_pll_bk->pix_clk_div = pll->bits_per_pixel + * pll->op_lanes * phy_const + / PHY_CONST_DIV / pll->csi2.lanes / l; + else + op_pll_bk->pix_clk_div = + pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; + + op_pll_bk->pix_clk_freq_hz = + op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; + + dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); + + if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) + __ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, + op_pll_bk, cphy, phy_const); -out_skip_vt_calc: pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; From patchwork Wed Sep 30 15:28:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809527 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06E8713B2 for ; Wed, 30 Sep 2020 15:29:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4B6E20888 for ; Wed, 30 Sep 2020 15:29:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725823AbgI3P3f (ORCPT ); Wed, 30 Sep 2020 11:29:35 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731005AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 90D9B634CEF for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 074/100] ccs-pll: Check for derating and overrating, support non-derating sensors Date: Wed, 30 Sep 2020 18:28:32 +0300 Message-Id: <20200930152858.8471-75-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some sensors support derating (VT domain speed faster than OP) or overrating (VT domain speed slower than OP). While this was supported for the driver, the hardware support for the feature was never verified. Do that now, and for those devices without that support, VT and OP speeds have to match. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 84 +++++++++++++++++++++----------- drivers/media/i2c/ccs-pll.h | 2 + drivers/media/i2c/ccs/ccs-core.c | 7 +++ 3 files changed, 64 insertions(+), 29 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 34e372b0bb84..b474c7e81385 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -142,6 +142,18 @@ static int check_all_bounds(struct device *dev, lim->vt_bk.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); + if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) && + pll->pixel_rate_pixel_array > pll->pixel_rate_csi) { + dev_dbg(dev, "device does not support derating\n"); + return -EINVAL; + } + + if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) && + pll->pixel_rate_pixel_array < pll->pixel_rate_csi) { + dev_dbg(dev, "device does not support overrating\n"); + return -EINVAL; + } + return rval; } @@ -163,37 +175,51 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, uint32_t min_sys_div, max_sys_div; /* - * Some sensors perform analogue binning and some do this - * digitally. The ones doing this digitally can be roughly be - * found out using this formula. The ones doing this digitally - * should run at higher clock rate, so smaller divisor is used - * on video timing side. + * Find out whether a sensor supports derating. If it does not, VT and + * OP domains are required to run at the same pixel rate. */ - if (lim->min_line_length_pck_bin > lim->min_line_length_pck - / pll->binning_horizontal) - vt_op_binning_div = pll->binning_horizontal; - else - vt_op_binning_div = 1; - dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); + if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) { + min_vt_div = + op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div + * pll->vt_lanes * phy_const + / pll->op_lanes / PHY_CONST_DIV; + } else { + /* + * Some sensors perform analogue binning and some do this + * digitally. The ones doing this digitally can be roughly be + * found out using this formula. The ones doing this digitally + * should run at higher clock rate, so smaller divisor is used + * on video timing side. + */ + if (lim->min_line_length_pck_bin > lim->min_line_length_pck + / pll->binning_horizontal) + vt_op_binning_div = pll->binning_horizontal; + else + vt_op_binning_div = 1; + dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); - /* - * Profile 2 supports vt_pix_clk_div E [4, 10] - * - * Horizontal binning can be used as a base for difference in - * divisors. One must make sure that horizontal blanking is - * enough to accommodate the CSI-2 sync codes. - * - * Take scaling factor and number of VT lanes into account as well. - * - * Find absolute limits for the factor of vt divider. - */ - dev_dbg(dev, "scale_m: %u\n", pll->scale_m); - min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div - * pll->scale_n * pll->vt_lanes * phy_const, - (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1) - * vt_op_binning_div * pll->scale_m - * PHY_CONST_DIV); + /* + * Profile 2 supports vt_pix_clk_div E [4, 10] + * + * Horizontal binning can be used as a base for difference in + * divisors. One must make sure that horizontal blanking is + * enough to accommodate the CSI-2 sync codes. + * + * Take scaling factor and number of VT lanes into account as well. + * + * Find absolute limits for the factor of vt divider. + */ + dev_dbg(dev, "scale_m: %u\n", pll->scale_m); + min_vt_div = + DIV_ROUND_UP(pll->bits_per_pixel + * op_pll_bk->sys_clk_div * pll->scale_n + * pll->vt_lanes * phy_const, + (pll->flags & + CCS_PLL_FLAG_LANE_SPEED_MODEL ? + pll->csi2.lanes : 1) + * vt_op_binning_div * pll->scale_m + * PHY_CONST_DIV); + } /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 0c25c5f5d4e4..9ba738ea7006 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -27,6 +27,8 @@ #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5) +#define CCS_PLL_FLAG_FIFO_DERATING BIT(6) +#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 5d0011e51913..ace2844b5798 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3203,6 +3203,13 @@ static int ccs_probe(struct i2c_client *client) if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV) sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV; + if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) & + CCS_FIFO_SUPPORT_CAPABILITY_DERATING) + sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING; + if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) & + CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING) + sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING | + CCS_PLL_FLAG_FIFO_OVERRATING; sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809523 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A037C618 for ; Wed, 30 Sep 2020 15:29:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D08720789 for ; Wed, 30 Sep 2020 15:29:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731047AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731034AbgI3P3N (ORCPT ); Wed, 30 Sep 2020 11:29:13 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A80EA634CA9 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 075/100] ccs-pll: Better separate OP and VT sub-tree calculation Date: Wed, 30 Sep 2020 18:28:33 +0300 Message-Id: <20200930152858.8471-76-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Better separate OP PLL branch calculation from VT branch calculation. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 54 +++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index b474c7e81385..41e2ba72bce1 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -162,11 +162,11 @@ static int check_all_bounds(struct device *dev, #define PHY_CONST_DIV 16 static void -__ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, - const struct ccs_pll_branch_limits_bk *op_lim_bk, - struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, - struct ccs_pll_branch_bk *op_pll_bk, bool cphy, - uint32_t phy_const) +ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, + struct ccs_pll_branch_bk *op_pll_bk, bool cphy, + uint32_t phy_const) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -174,6 +174,9 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, uint32_t min_vt_div, max_vt_div, vt_div; uint32_t min_sys_div, max_sys_div; + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) + goto out_calc_pixel_rate; + /* * Find out whether a sensor supports derating. If it does not, VT and * OP domains are required to run at the same pixel rate. @@ -313,6 +316,10 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; pll->vt_bk.pix_clk_freq_hz = pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; + +out_calc_pixel_rate: + pll->pixel_rate_pixel_array = + pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; } /* @@ -327,12 +334,12 @@ __ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, * @return Zero on success, error code on error. */ static int -__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, - const struct ccs_pll_branch_limits_fr *op_lim_fr, - const struct ccs_pll_branch_limits_bk *op_lim_bk, - struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, - struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) +ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_fr *op_lim_fr, + const struct ccs_pll_branch_limits_bk *op_lim_bk, + struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, + struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, + uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) { /* * Higher multipliers (and divisors) are often required than @@ -430,15 +437,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); - if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) - __ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, - op_pll_bk, cphy, phy_const); - - pll->pixel_rate_pixel_array = - pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; - - return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr, - op_pll_bk); + return 0; } int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, @@ -558,13 +557,22 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, op_pll_fr->pre_pll_clk_div += (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (op_pll_fr->pre_pll_clk_div & 1)) { - rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div, l, - cphy, phy_const); + rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll, + op_pll_fr, op_pll_bk, mul, div, l, + cphy, phy_const); + if (rval) + continue; + + ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, + op_pll_bk, cphy, phy_const); + + rval = check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, + op_pll_fr, op_pll_bk); if (rval) continue; print_pll(dev, pll); + return 0; } From patchwork Wed Sep 30 15:28:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36DC2618 for ; Wed, 30 Sep 2020 15:29:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FEC8207FB for ; Wed, 30 Sep 2020 15:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731005AbgI3P3g (ORCPT ); Wed, 30 Sep 2020 11:29:36 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731035AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id BD4F2634C8C for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 076/100] ccs-pll: Print relevant information on PLL tree Date: Wed, 30 Sep 2020 18:28:34 +0300 Message-Id: <20200930152858.8471-77-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Print information on PLL tree configuration based on the flags. This also adds support for printing dual PLL trees, and better separates between OP and VT PLL trees. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 85 ++++++++++++++++++++++++++++--------- 1 file changed, 66 insertions(+), 19 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 41e2ba72bce1..cff6b377ed84 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -56,28 +56,75 @@ static int bounds_check(struct device *dev, uint32_t val, return -EINVAL; } -static void print_pll(struct device *dev, struct ccs_pll *pll) +#define PLL_OP 1 +#define PLL_VT 2 + +static const char *pll_string(unsigned int which) { - dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->vt_fr.pre_pll_clk_div); - dev_dbg(dev, "pll_multiplier \t%u\n", pll->vt_fr.pll_multiplier); - if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { - dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_bk.sys_clk_div); - dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_bk.pix_clk_div); + switch (which) { + case PLL_OP: + return "op"; + case PLL_VT: + return "vt"; } - dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_bk.sys_clk_div); - dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_bk.pix_clk_div); - - dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); - dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->vt_fr.pll_ip_clk_freq_hz); - dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->vt_fr.pll_op_clk_freq_hz); - if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) { - dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", - pll->op_bk.sys_clk_freq_hz); - dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", - pll->op_bk.pix_clk_freq_hz); + + return NULL; +} + +#define PLL_FL(f) CCS_PLL_FLAG_##f + +static void print_pll(struct device *dev, struct ccs_pll *pll) +{ + const struct { + struct ccs_pll_branch_fr *fr; + struct ccs_pll_branch_bk *bk; + unsigned int which; + } branches[] = { + { &pll->vt_fr, &pll->vt_bk, PLL_VT }, + { NULL, &pll->op_bk, PLL_OP } + }, *br; + unsigned int i; + + dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz); + + for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) { + const char *s = pll_string(br->which); + + if (br->which == PLL_VT) { + dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s, + br->fr->pre_pll_clk_div); + dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s, + br->fr->pll_multiplier); + + dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s, + br->fr->pll_ip_clk_freq_hz); + dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s, + br->fr->pll_op_clk_freq_hz); + } + + if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) || + br->which == PLL_VT) { + dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s, + br->bk->sys_clk_div); + dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s, + br->bk->pix_clk_div); + + dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s, + br->bk->sys_clk_freq_hz); + dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s, + br->bk->pix_clk_freq_hz); + } } - dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_bk.sys_clk_freq_hz); - dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_bk.pix_clk_freq_hz); + + dev_dbg(dev, "flags%s%s%s%s%s%s\n", + pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", + pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "", + pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ? + " ext-ip-pll-divider" : "", + pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ? + " flexible-op-pix-div" : "", + pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "", + pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : ""); } static int check_all_bounds(struct device *dev, From patchwork Wed Sep 30 15:28:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809525 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6036592C for ; Wed, 30 Sep 2020 15:29:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B75420759 for ; Wed, 30 Sep 2020 15:29:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731102AbgI3P3f (ORCPT ); Wed, 30 Sep 2020 11:29:35 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731036AbgI3P3O (ORCPT ); Wed, 30 Sep 2020 11:29:14 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id D2F11634CAA for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 077/100] ccs-pll: Rework bounds checks Date: Wed, 30 Sep 2020 18:28:35 +0300 Message-Id: <20200930152858.8471-78-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Refactor bounds checks so that the caller can decide what to check. This allows doing the checks early, when the values are available. This also adds front OP PLL configuration and limits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 148 ++++++++++++++++++++++-------------- drivers/media/i2c/ccs-pll.h | 2 + 2 files changed, 93 insertions(+), 57 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index cff6b377ed84..e1755498cd79 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -46,12 +46,14 @@ static inline uint32_t one_or_more(uint32_t a) } static int bounds_check(struct device *dev, uint32_t val, - uint32_t min, uint32_t max, char *str) + uint32_t min, uint32_t max, const char *prefix, + char *str) { if (val >= min && val <= max) return 0; - dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); + dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix, + str, val, min, max); return -EINVAL; } @@ -81,7 +83,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) unsigned int which; } branches[] = { { &pll->vt_fr, &pll->vt_bk, PLL_VT }, - { NULL, &pll->op_bk, PLL_OP } + { &pll->op_fr, &pll->op_bk, PLL_OP } }, *br; unsigned int i; @@ -127,68 +129,90 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : ""); } -static int check_all_bounds(struct device *dev, - const struct ccs_pll_limits *lim, - const struct ccs_pll_branch_limits_fr *op_lim_fr, - const struct ccs_pll_branch_limits_bk *op_lim_bk, - struct ccs_pll *pll, - struct ccs_pll_branch_fr *op_pll_fr, - struct ccs_pll_branch_bk *op_pll_bk) +static int check_fr_bounds(struct device *dev, + const struct ccs_pll_limits *lim, + struct ccs_pll *pll, unsigned int which) { + const struct ccs_pll_branch_limits_fr *lim_fr; + struct ccs_pll_branch_fr *pll_fr; + const char *s = pll_string(which); int rval; - rval = bounds_check(dev, op_pll_fr->pll_ip_clk_freq_hz, - op_lim_fr->min_pll_ip_clk_freq_hz, - op_lim_fr->max_pll_ip_clk_freq_hz, - "pll_ip_clk_freq_hz"); - if (!rval) - rval = bounds_check( - dev, op_pll_fr->pll_multiplier, - op_lim_fr->min_pll_multiplier, - op_lim_fr->max_pll_multiplier, "pll_multiplier"); - if (!rval) - rval = bounds_check( - dev, op_pll_fr->pll_op_clk_freq_hz, - op_lim_fr->min_pll_op_clk_freq_hz, - op_lim_fr->max_pll_op_clk_freq_hz, "pll_op_clk_freq_hz"); + if (which == PLL_OP) { + lim_fr = &lim->op_fr; + pll_fr = &pll->op_fr; + } else { + lim_fr = &lim->vt_fr; + pll_fr = &pll->vt_fr; + } + + rval = bounds_check(dev, pll_fr->pre_pll_clk_div, + lim_fr->min_pre_pll_clk_div, + lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div"); + if (!rval) - rval = bounds_check( - dev, op_pll_bk->sys_clk_div, - op_lim_bk->min_sys_clk_div, op_lim_bk->max_sys_clk_div, - "op_sys_clk_div"); + rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz, + lim_fr->min_pll_ip_clk_freq_hz, + lim_fr->max_pll_ip_clk_freq_hz, + s, "pll_ip_clk_freq_hz"); if (!rval) - rval = bounds_check( - dev, op_pll_bk->sys_clk_freq_hz, - op_lim_bk->min_sys_clk_freq_hz, - op_lim_bk->max_sys_clk_freq_hz, - "op_sys_clk_freq_hz"); + rval = bounds_check(dev, pll_fr->pll_multiplier, + lim_fr->min_pll_multiplier, + lim_fr->max_pll_multiplier, + s, "pll_multiplier"); if (!rval) - rval = bounds_check( - dev, op_pll_bk->pix_clk_freq_hz, - op_lim_bk->min_pix_clk_freq_hz, - op_lim_bk->max_pix_clk_freq_hz, - "op_pix_clk_freq_hz"); + rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz, + lim_fr->min_pll_op_clk_freq_hz, + lim_fr->max_pll_op_clk_freq_hz, + s, "pll_op_clk_freq_hz"); - /* - * If there are no OP clocks, the VT clocks are contained in - * the OP clock struct. - */ - if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) - return rval; + return rval; +} + +static int check_bk_bounds(struct device *dev, + const struct ccs_pll_limits *lim, + struct ccs_pll *pll, unsigned int which) +{ + const struct ccs_pll_branch_limits_bk *lim_bk; + struct ccs_pll_branch_bk *pll_bk; + const char *s = pll_string(which); + int rval; + + if (which == PLL_OP) { + if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) + return 0; + lim_bk = &lim->op_bk; + pll_bk = &pll->op_bk; + } else { + lim_bk = &lim->vt_bk; + pll_bk = &pll->vt_bk; + } + + rval = bounds_check(dev, pll_bk->sys_clk_div, + lim_bk->min_sys_clk_div, + lim_bk->max_sys_clk_div, s, "op_sys_clk_div"); + if (!rval) + rval = bounds_check(dev, pll_bk->sys_clk_freq_hz, + lim_bk->min_sys_clk_freq_hz, + lim_bk->max_sys_clk_freq_hz, + s, "sys_clk_freq_hz"); if (!rval) - rval = bounds_check( - dev, pll->vt_bk.sys_clk_freq_hz, - lim->vt_bk.min_sys_clk_freq_hz, - lim->vt_bk.max_sys_clk_freq_hz, - "vt_sys_clk_freq_hz"); + rval = bounds_check(dev, pll_bk->sys_clk_div, + lim_bk->min_sys_clk_div, + lim_bk->max_sys_clk_div, + s, "sys_clk_div"); if (!rval) - rval = bounds_check( - dev, pll->vt_bk.pix_clk_freq_hz, - lim->vt_bk.min_pix_clk_freq_hz, - lim->vt_bk.max_pix_clk_freq_hz, - "vt_pix_clk_freq_hz"); + rval = bounds_check(dev, pll_bk->pix_clk_freq_hz, + lim_bk->min_pix_clk_freq_hz, + lim_bk->max_pix_clk_freq_hz, + s, "pix_clk_freq_hz"); + + return rval; +} +static int check_ext_bounds(struct device *dev, struct ccs_pll *pll) +{ if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) && pll->pixel_rate_pixel_array > pll->pixel_rate_csi) { dev_dbg(dev, "device does not support derating\n"); @@ -201,7 +225,7 @@ static int check_all_bounds(struct device *dev, return -EINVAL; } - return rval; + return 0; } #define CPHY_CONST 7 @@ -610,11 +634,21 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (rval) continue; + rval = check_fr_bounds(dev, lim, pll, PLL_VT); + if (rval) + continue; + + rval = check_bk_bounds(dev, lim, pll, PLL_OP); + if (rval) + continue; + ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, op_pll_bk, cphy, phy_const); - rval = check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk); + rval = check_bk_bounds(dev, lim, pll, PLL_VT); + if (rval) + continue; + rval = check_ext_bounds(dev, pll); if (rval) continue; diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 9ba738ea7006..4fa3d4e459a0 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -111,6 +111,7 @@ struct ccs_pll { /* output values */ struct ccs_pll_branch_fr vt_fr; struct ccs_pll_branch_bk vt_bk; + struct ccs_pll_branch_fr op_fr; struct ccs_pll_branch_bk op_bk; uint32_t pixel_rate_csi; @@ -181,6 +182,7 @@ struct ccs_pll_limits { struct ccs_pll_branch_limits_fr vt_fr; struct ccs_pll_branch_limits_bk vt_bk; + struct ccs_pll_branch_limits_fr op_fr; struct ccs_pll_branch_limits_bk op_bk; /* Other relevant limits */ From patchwork Wed Sep 30 15:28:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809477 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BD0B618 for ; Wed, 30 Sep 2020 15:29:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A7B520789 for ; Wed, 30 Sep 2020 15:29:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731062AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731039AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id EBF5B634CF0 for ; Wed, 30 Sep 2020 18:28:52 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 078/100] ccs-pll: Make VT divisors 16-bit Date: Wed, 30 Sep 2020 18:28:36 +0300 Message-Id: <20200930152858.8471-79-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after all. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 51 ++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index e1755498cd79..c0f3f68e55d8 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -239,11 +239,11 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll_branch_bk *op_pll_bk, bool cphy, uint32_t phy_const) { - uint32_t sys_div; - uint32_t best_pix_div = INT_MAX >> 1; - uint32_t vt_op_binning_div; - uint32_t min_vt_div, max_vt_div, vt_div; - uint32_t min_sys_div, max_sys_div; + uint16_t sys_div; + uint16_t best_pix_div = SHRT_MAX >> 1; + uint16_t vt_op_binning_div; + uint16_t min_vt_div, max_vt_div, vt_div; + uint16_t min_sys_div, max_sys_div; if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) goto out_calc_pixel_rate; @@ -297,20 +297,19 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); - min_vt_div = max(min_vt_div, - DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, - lim->vt_bk.max_pix_clk_freq_hz)); + min_vt_div = max_t(uint16_t, min_vt_div, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.max_pix_clk_freq_hz)); dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", min_vt_div); - min_vt_div = max_t(uint32_t, min_vt_div, - lim->vt_bk.min_pix_clk_div - * lim->vt_bk.min_sys_clk_div); + min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div + * lim->vt_bk.min_sys_clk_div); dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); - max_vt_div = min(max_vt_div, - DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, + max_vt_div = min_t(uint16_t, max_vt_div, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", max_vt_div); @@ -321,26 +320,26 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, */ min_sys_div = lim->vt_bk.min_sys_clk_div; dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); - min_sys_div = max(min_sys_div, - DIV_ROUND_UP(min_vt_div, - lim->vt_bk.max_pix_clk_div)); + min_sys_div = max_t(uint16_t, min_sys_div, + DIV_ROUND_UP(min_vt_div, + lim->vt_bk.max_pix_clk_div)); dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); - min_sys_div = max(min_sys_div, - pll_fr->pll_op_clk_freq_hz - / lim->vt_bk.max_sys_clk_freq_hz); + min_sys_div = max_t(uint16_t, min_sys_div, + pll_fr->pll_op_clk_freq_hz + / lim->vt_bk.max_sys_clk_freq_hz); dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); min_sys_div = clk_div_even_up(min_sys_div); dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); max_sys_div = lim->vt_bk.max_sys_clk_div; dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); - max_sys_div = min(max_sys_div, - DIV_ROUND_UP(max_vt_div, - lim->vt_bk.min_pix_clk_div)); + max_sys_div = min_t(uint16_t, max_sys_div, + DIV_ROUND_UP(max_vt_div, + lim->vt_bk.min_pix_clk_div)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); - max_sys_div = min(max_sys_div, - DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, - lim->vt_bk.min_pix_clk_freq_hz)); + max_sys_div = min_t(uint16_t, max_sys_div, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); /* @@ -376,7 +375,7 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, if (vt_div == rounded_div) break; } - if (best_pix_div < INT_MAX >> 1) + if (best_pix_div < SHRT_MAX >> 1) break; } From patchwork Wed Sep 30 15:28:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809517 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDC7E13B2 for ; Wed, 30 Sep 2020 15:29:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CA8D320759 for ; Wed, 30 Sep 2020 15:29:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731099AbgI3P3b (ORCPT ); Wed, 30 Sep 2020 11:29:31 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731044AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 0E6C6634CBD for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 079/100] ccs-pll: Fix VT post-PLL divisor calculation Date: Wed, 30 Sep 2020 18:28:37 +0300 Message-Id: <20200930152858.8471-80-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The PLL calculator only searched even total divisor values apart from one, but this is wrong: the total divisor is odd in cases where system divisor is one. Fix this by including odd total PLL values where system divisor is one to the search. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index c0f3f68e55d8..52dea3894229 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -347,14 +347,16 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, * into a value which is not smaller than div, the desired * divisor. */ - for (vt_div = min_vt_div; vt_div <= max_vt_div; - vt_div += 2 - (vt_div & 1)) { - for (sys_div = min_sys_div; - sys_div <= max_sys_div; + for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) { + uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div; + + for (sys_div = min_sys_div; sys_div <= __max_sys_div; sys_div += 2 - (sys_div & 1)) { - uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); + uint16_t pix_div; uint16_t rounded_div; + pix_div = DIV_ROUND_UP(vt_div, sys_div); + if (pix_div < lim->vt_bk.min_pix_clk_div || pix_div > lim->vt_bk.max_pix_clk_div) { dev_dbg(dev, From patchwork Wed Sep 30 15:28:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4B4B618 for ; Wed, 30 Sep 2020 15:29:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE1DB20759 for ; Wed, 30 Sep 2020 15:29:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731025AbgI3P3d (ORCPT ); Wed, 30 Sep 2020 11:29:33 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731046AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 1BBAE634CF3 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 080/100] ccs-pll: Separate VT divisor limit calculation from the rest Date: Wed, 30 Sep 2020 18:28:38 +0300 Message-Id: <20200930152858.8471-81-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Separate VT divisor limit calculation from the rest of the VT PLL branch calculation. This way it can be used for dual PLL support as well. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 64 +++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 52dea3894229..d7805e61a7c0 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -228,6 +228,41 @@ static int check_ext_bounds(struct device *dev, struct ccs_pll *pll) return 0; } +static void +ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, + struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, + uint16_t min_vt_div, uint16_t max_vt_div, + uint16_t *min_sys_div, uint16_t *max_sys_div) +{ + /* + * Find limits for sys_clk_div. Not all values are possible with all + * values of pix_clk_div. + */ + *min_sys_div = lim->vt_bk.min_sys_clk_div; + dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div); + *min_sys_div = max_t(uint16_t, *min_sys_div, + DIV_ROUND_UP(min_vt_div, + lim->vt_bk.max_pix_clk_div)); + dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div); + *min_sys_div = max_t(uint16_t, *min_sys_div, + pll_fr->pll_op_clk_freq_hz + / lim->vt_bk.max_sys_clk_freq_hz); + dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div); + *min_sys_div = clk_div_even_up(*min_sys_div); + dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div); + + *max_sys_div = lim->vt_bk.max_sys_clk_div; + dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div); + *max_sys_div = min_t(uint16_t, *max_sys_div, + DIV_ROUND_UP(max_vt_div, + lim->vt_bk.min_pix_clk_div)); + dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div); + *max_sys_div = min_t(uint16_t, *max_sys_div, + DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, + lim->vt_bk.min_pix_clk_freq_hz)); + dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div); +} + #define CPHY_CONST 7 #define DPHY_CONST 16 #define PHY_CONST_DIV 16 @@ -314,33 +349,8 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", max_vt_div); - /* - * Find limitsits for sys_clk_div. Not all values are possible - * with all values of pix_clk_div. - */ - min_sys_div = lim->vt_bk.min_sys_clk_div; - dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); - min_sys_div = max_t(uint16_t, min_sys_div, - DIV_ROUND_UP(min_vt_div, - lim->vt_bk.max_pix_clk_div)); - dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); - min_sys_div = max_t(uint16_t, min_sys_div, - pll_fr->pll_op_clk_freq_hz - / lim->vt_bk.max_sys_clk_freq_hz); - dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); - min_sys_div = clk_div_even_up(min_sys_div); - dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); - - max_sys_div = lim->vt_bk.max_sys_clk_div; - dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); - max_sys_div = min_t(uint16_t, max_sys_div, - DIV_ROUND_UP(max_vt_div, - lim->vt_bk.min_pix_clk_div)); - dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); - max_sys_div = min_t(uint16_t, max_sys_div, - DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, - lim->vt_bk.min_pix_clk_freq_hz)); - dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); + ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div, + max_vt_div, &min_sys_div, &max_sys_div); /* * Find pix_div such that a legal pix_div * sys_div results From patchwork Wed Sep 30 15:28:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00858618 for ; Wed, 30 Sep 2020 15:29:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D97B420789 for ; Wed, 30 Sep 2020 15:29:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731072AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731048AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 342AD634CF4 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 081/100] ccs-pll: Add trivial dual PLL support Date: Wed, 30 Sep 2020 18:28:39 +0300 Message-Id: <20200930152858.8471-82-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for sensors that have separate VT and OP domain PLLs. This support is trivial in the sense that it aims for the same VT pixel rate than that on the CSI-2 bus. The vast majority of sensors is better supported by higher frequencies in VT domain in binned and possibly scaled configurations. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 228 +++++++++++++++++++++++++++++++----- drivers/media/i2c/ccs-pll.h | 1 + 2 files changed, 201 insertions(+), 28 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index d7805e61a7c0..62ce38efb118 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -92,7 +92,8 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) { const char *s = pll_string(br->which); - if (br->which == PLL_VT) { + if (pll->flags & CCS_PLL_FLAG_DUAL_PLL || + br->which == PLL_VT) { dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s, br->fr->pre_pll_clk_div); dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s, @@ -118,7 +119,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) } } - dev_dbg(dev, "flags%s%s%s%s%s%s\n", + dev_dbg(dev, "flags%s%s%s%s%s%s%s\n", pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "", pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ? @@ -126,7 +127,8 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ? " flexible-op-pix-div" : "", pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "", - pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : ""); + pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "", + pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : ""); } static int check_fr_bounds(struct device *dev, @@ -267,12 +269,157 @@ ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, #define DPHY_CONST 16 #define PHY_CONST_DIV 16 -static void -ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, - const struct ccs_pll_branch_limits_bk *op_lim_bk, - struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, - struct ccs_pll_branch_bk *op_pll_bk, bool cphy, - uint32_t phy_const) +static inline int +__ccs_pll_calculate_vt_tree(struct device *dev, + const struct ccs_pll_limits *lim, + struct ccs_pll *pll, uint32_t mul, uint32_t div) +{ + const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; + const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk; + struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; + struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk; + uint32_t more_mul; + uint16_t best_pix_div = SHRT_MAX >> 1, best_div; + uint16_t vt_div, min_sys_div, max_sys_div, sys_div; + + pll_fr->pll_ip_clk_freq_hz = + pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div; + + dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz); + + more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz, + pll_fr->pll_ip_clk_freq_hz * mul)); + + dev_dbg(dev, "more_mul: %u\n", more_mul); + more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul); + dev_dbg(dev, "more_mul2: %u\n", more_mul); + + pll_fr->pll_multiplier = mul * more_mul; + + if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz > + lim_fr->max_pll_op_clk_freq_hz) + return -EINVAL; + + pll_fr->pll_op_clk_freq_hz = + pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier; + + vt_div = div * more_mul; + + ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div, + &min_sys_div, &max_sys_div); + + max_sys_div = (vt_div & 1) ? 1 : max_sys_div; + + dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div); + + for (sys_div = min_sys_div; sys_div <= max_sys_div; + sys_div += 2 - (sys_div & 1)) { + uint16_t pix_div; + + if (vt_div % sys_div) + continue; + + pix_div = vt_div / sys_div; + + if (pix_div < lim_bk->min_pix_clk_div || + pix_div > lim_bk->max_pix_clk_div) { + dev_dbg(dev, + "pix_div %u too small or too big (%u--%u)\n", + pix_div, + lim_bk->min_pix_clk_div, + lim_bk->max_pix_clk_div); + continue; + } + + if (pix_div * sys_div <= best_div) { + best_pix_div = pix_div; + best_div = pix_div * sys_div; + } + } + if (best_pix_div == SHRT_MAX >> 1) + return -EINVAL; + + pll_bk->sys_clk_div = best_div / best_pix_div; + pll_bk->pix_clk_div = best_pix_div; + + pll_bk->sys_clk_freq_hz = + pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div; + pll_bk->pix_clk_freq_hz = + pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div; + + pll->pixel_rate_pixel_array = + pll_bk->pix_clk_freq_hz * pll->vt_lanes; + + return 0; +} + +static int ccs_pll_calculate_vt_tree(struct device *dev, + const struct ccs_pll_limits *lim, + struct ccs_pll *pll) +{ + const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; + struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; + uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div; + uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div; + uint32_t pre_mul, pre_div; + + pre_div = gcd(pll->pixel_rate_csi, + pll->ext_clk_freq_hz * pll->vt_lanes); + pre_mul = pll->pixel_rate_csi / pre_div; + pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div; + + /* Make sure PLL input frequency is within limits */ + max_pre_pll_clk_div = + min_t(uint16_t, max_pre_pll_clk_div, + DIV_ROUND_UP(pll->ext_clk_freq_hz, + lim_fr->min_pll_ip_clk_freq_hz)); + + min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div, + pll->ext_clk_freq_hz / + lim_fr->max_pll_ip_clk_freq_hz); + + dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n", + min_pre_pll_clk_div, max_pre_pll_clk_div); + + for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div; + pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div; + pll_fr->pre_pll_clk_div += + (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : + 2 - (pll_fr->pre_pll_clk_div & 1)) { + uint32_t mul, div; + int rval; + + div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div); + mul = pre_mul * pll_fr->pre_pll_clk_div / div; + div = pre_div / div; + + dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n", + pll_fr->pre_pll_clk_div, mul, div); + + rval = __ccs_pll_calculate_vt_tree(dev, lim, pll, + mul, div); + if (rval) + continue; + + rval = check_fr_bounds(dev, lim, pll, PLL_VT); + if (rval) + continue; + + rval = check_bk_bounds(dev, lim, pll, PLL_VT); + if (rval) + continue; + + return 0; + } + + return -EINVAL; +} + +static void ccs_pll_calculate_vt( + struct device *dev, const struct ccs_pll_limits *lim, + const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, + struct ccs_pll_branch_fr *pll_fr, struct ccs_pll_branch_bk *op_pll_bk, + bool cphy, uint32_t phy_const) { uint16_t sys_div; uint16_t best_pix_div = SHRT_MAX >> 1; @@ -525,10 +672,10 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll *pll) { - const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr; - const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; - struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; - struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; + const struct ccs_pll_branch_limits_fr *op_lim_fr; + const struct ccs_pll_branch_limits_bk *op_lim_bk; + struct ccs_pll_branch_fr *op_pll_fr; + struct ccs_pll_branch_bk *op_pll_bk; bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; uint16_t min_op_pre_pll_clk_div; @@ -544,6 +691,28 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, pll->vt_lanes = 1; } + if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) { + op_lim_fr = &lim->op_fr; + op_lim_bk = &lim->op_bk; + op_pll_fr = &pll->op_fr; + op_pll_bk = &pll->op_bk; + } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { + /* + * If there's no OP PLL at all, use the VT values + * instead. The OP values are ignored for the rest of + * the PLL calculation. + */ + op_lim_fr = &lim->vt_fr; + op_lim_bk = &lim->vt_bk; + op_pll_fr = &pll->vt_fr; + op_pll_bk = &pll->vt_bk; + } else { + op_lim_fr = &lim->vt_fr; + op_lim_bk = &lim->op_bk; + op_pll_fr = &pll->vt_fr; + op_pll_bk = &pll->op_bk; + } + if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel || !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m || !op_lim_fr->min_pll_ip_clk_freq_hz || @@ -567,17 +736,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); - if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { - /* - * If there's no OP PLL at all, use the VT values - * instead. The OP values are ignored for the rest of - * the PLL calculation. - */ - op_lim_fr = &lim->vt_fr; - op_lim_bk = &lim->vt_bk; - op_pll_bk = &pll->vt_bk; - } - dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, pll->binning_vertical); @@ -653,6 +811,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (rval) continue; + if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) + break; + ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, op_pll_bk, cphy, phy_const); @@ -663,14 +824,25 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (rval) continue; - print_pll(dev, pll); + break; + } + + if (rval) { + dev_dbg(dev, "unable to compute pre_pll divisor\n"); - return 0; + return rval; } - dev_dbg(dev, "unable to compute pre_pll divisor\n"); + if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) { + rval = ccs_pll_calculate_vt_tree(dev, lim, pll); - return rval; + if (rval) + return rval; + } + + print_pll(dev, pll); + + return 0; } EXPORT_SYMBOL_GPL(ccs_pll_calculate); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 4fa3d4e459a0..1be8f300c860 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -29,6 +29,7 @@ #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5) #define CCS_PLL_FLAG_FIFO_DERATING BIT(6) #define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) +#define CCS_PLL_FLAG_DUAL_PLL BIT(8) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) From patchwork Wed Sep 30 15:28:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61B8A618 for ; Wed, 30 Sep 2020 15:29:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B7DE20789 for ; Wed, 30 Sep 2020 15:29:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731098AbgI3P33 (ORCPT ); Wed, 30 Sep 2020 11:29:29 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44690 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731003AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 4428E634CF5 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 082/100] ccs: Dual PLL support Date: Wed, 30 Sep 2020 18:28:40 +0300 Message-Id: <20200930152858.8471-83-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for sensors that either require dual PLL or support single or dual PLL but use dual PLL as default. Use sensor default configuration for sensors that support both modes. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 9 +++++-- drivers/media/i2c/ccs/ccs-core.c | 45 +++++++++++++++++++++++++++++++- 2 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 62ce38efb118..dbb22096447d 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -331,7 +331,10 @@ __ccs_pll_calculate_vt_tree(struct device *dev, continue; } - if (pix_div * sys_div <= best_div) { + dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div, + best_pix_div); + + if (pix_div * sys_div <= best_pix_div) { best_pix_div = pix_div; best_div = pix_div * sys_div; } @@ -803,7 +806,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (rval) continue; - rval = check_fr_bounds(dev, lim, pll, PLL_VT); + rval = check_fr_bounds(dev, lim, pll, + pll->flags & CCS_PLL_FLAG_DUAL_PLL ? + PLL_OP : PLL_VT); if (rval) continue; diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index ace2844b5798..1272cfe201e3 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -394,7 +394,23 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) if (rval < 0) return rval; - return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div); + rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div); + if (rval < 0) + return rval; + + if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL)) + return 0; + + rval = ccs_write(sensor, PLL_MODE, CCS_PLL_MODE_DUAL); + if (rval < 0) + return rval; + + rval = ccs_write(sensor, OP_PRE_PLL_CLK_DIV, + pll->op_fr.pre_pll_clk_div); + if (rval < 0) + return rval; + + return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier); } static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll) @@ -411,6 +427,16 @@ static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll) .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ), .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ), }, + .op_fr = { + .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_OP_PRE_PLL_CLK_DIV), + .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_OP_PRE_PLL_CLK_DIV), + .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_IP_CLK_FREQ_MHZ), + .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_IP_CLK_FREQ_MHZ), + .min_pll_multiplier = CCS_LIM(sensor, MIN_OP_PLL_MULTIPLIER), + .max_pll_multiplier = CCS_LIM(sensor, MAX_OP_PLL_MULTIPLIER), + .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_OP_CLK_FREQ_MHZ), + .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_OP_CLK_FREQ_MHZ), + }, .op_bk = { .min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV), .max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV), @@ -3210,6 +3236,23 @@ static int ccs_probe(struct i2c_client *client) CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING) sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING | CCS_PLL_FLAG_FIFO_OVERRATING; + if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & + CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL) { + if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & + CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL) { + u32 v; + + /* Use sensor default in PLL mode selection */ + rval = ccs_read(sensor, PLL_MODE, &v); + if (rval) + goto out_cleanup; + + if (v == CCS_PLL_MODE_DUAL) + sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL; + } else { + sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL; + } + } sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); From patchwork Wed Sep 30 15:28:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809505 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F1A1E13B2 for ; Wed, 30 Sep 2020 15:29:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB93120789 for ; Wed, 30 Sep 2020 15:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731081AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44682 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731049AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 56759634CBF for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 083/100] ccs-pll: Add support for DDR OP system and pixel clocks Date: Wed, 30 Sep 2020 18:28:41 +0300 Message-Id: <20200930152858.8471-84-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for dual data rate operational system and pixel clocks. This is implemented using two PLL flags. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 64 +++++++++++++++++++++++++------------ drivers/media/i2c/ccs-pll.h | 2 ++ 2 files changed, 46 insertions(+), 20 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index dbb22096447d..cec811bb37a4 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -119,7 +119,7 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) } } - dev_dbg(dev, "flags%s%s%s%s%s%s%s\n", + dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n", pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "", pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ? @@ -128,7 +128,19 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) " flexible-op-pix-div" : "", pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "", pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "", - pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : ""); + pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "", + pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "", + pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : ""); +} + +static uint32_t op_sys_ddr(uint32_t flags) +{ + return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0; +} + +static uint32_t op_pix_ddr(uint32_t flags) +{ + return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0; } static int check_fr_bounds(struct device *dev, @@ -440,8 +452,8 @@ static void ccs_pll_calculate_vt( if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) { min_vt_div = op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div - * pll->vt_lanes * phy_const - / pll->op_lanes / PHY_CONST_DIV; + * pll->vt_lanes * phy_const / pll->op_lanes + / (PHY_CONST_DIV << op_pix_ddr(pll->flags)); } else { /* * Some sensors perform analogue binning and some do this @@ -477,7 +489,7 @@ static void ccs_pll_calculate_vt( CCS_PLL_FLAG_LANE_SPEED_MODEL ? pll->csi2.lanes : 1) * vt_op_binning_div * pll->scale_m - * PHY_CONST_DIV); + * PHY_CONST_DIV << op_pix_ddr(pll->flags)); } /* Find smallest and biggest allowed vt divisor. */ @@ -571,7 +583,8 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) + uint32_t div, uint32_t op_sys_clk_freq_hz_sdr, uint32_t l, + bool cphy, uint32_t phy_const) { /* * Higher multipliers (and divisors) are often required than @@ -657,15 +670,22 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, * op_pll_fr->pll_multiplier; if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) - op_pll_bk->pix_clk_div = pll->bits_per_pixel - * pll->op_lanes * phy_const - / PHY_CONST_DIV / pll->csi2.lanes / l; + op_pll_bk->pix_clk_div = + (pll->bits_per_pixel + * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags)) + / PHY_CONST_DIV / pll->csi2.lanes / l) + >> op_pix_ddr(pll->flags); else op_pll_bk->pix_clk_div = - pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; + (pll->bits_per_pixel + * (phy_const << op_sys_ddr(pll->flags)) + / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags); op_pll_bk->pix_clk_freq_hz = - op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; + (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags)) + / op_pll_bk->pix_clk_div; + op_pll_bk->sys_clk_freq_hz = + op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags); dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); @@ -681,6 +701,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll_branch_bk *op_pll_bk; bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; + uint32_t op_sys_clk_freq_hz_sdr; uint16_t min_op_pre_pll_clk_div; uint16_t max_op_pre_pll_clk_div; uint32_t mul, div; @@ -730,7 +751,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * op_pix_clk_div is supported */ if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) && - (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) { + (pll->bits_per_pixel * pll->op_lanes) % + (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) { dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n", pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l); return -EINVAL; @@ -745,12 +767,12 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, switch (pll->bus_type) { case CCS_PLL_BUS_TYPE_CSI2_DPHY: /* CSI transfers 2 bits per clock per lane; thus times 2 */ - op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 + op_sys_clk_freq_hz_sdr = pll->link_freq * 2 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 1 : pll->csi2.lanes); break; case CCS_PLL_BUS_TYPE_CSI2_CPHY: - op_pll_bk->sys_clk_freq_hz = + op_sys_clk_freq_hz_sdr = pll->link_freq * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 1 : pll->csi2.lanes); @@ -760,7 +782,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, } pll->pixel_rate_csi = - div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz + div_u64((uint64_t)op_sys_clk_freq_hz_sdr * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? pll->csi2.lanes : 1) * PHY_CONST_DIV, phy_const * pll->bits_per_pixel * l); @@ -780,9 +802,10 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); - i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz); - mul = op_pll_bk->sys_clk_freq_hz / i; - div = pll->ext_clk_freq_hz / i; + i = gcd(op_sys_clk_freq_hz_sdr, + pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)); + mul = op_sys_clk_freq_hz_sdr / i; + div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i; dev_dbg(dev, "mul %u / div %u\n", mul, div); min_op_pre_pll_clk_div = @@ -801,8 +824,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div, l, - cphy, phy_const); + op_pll_fr, op_pll_bk, mul, div, + op_sys_clk_freq_hz_sdr, l, cphy, + phy_const); if (rval) continue; diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 1be8f300c860..7d1e6e3eaada 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -30,6 +30,8 @@ #define CCS_PLL_FLAG_FIFO_DERATING BIT(6) #define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) #define CCS_PLL_FLAG_DUAL_PLL BIT(8) +#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9) +#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) From patchwork Wed Sep 30 15:28:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809519 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90F89618 for ; Wed, 30 Sep 2020 15:29:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B4AD20789 for ; Wed, 30 Sep 2020 15:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731101AbgI3P3c (ORCPT ); Wed, 30 Sep 2020 11:29:32 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731025AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 68FCE634CF7 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 084/100] ccs: Add support for DDR OP SYS and OP PIX clocks Date: Wed, 30 Sep 2020 18:28:42 +0300 Message-Id: <20200930152858.8471-85-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Support dual data rate operational system and pixel clocks by conveying the flags to the PLL calculator and updating how the link rate is calculated. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 1272cfe201e3..a6d5164be8a0 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -386,7 +386,8 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, 1000000 / 256 / 256) * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - sensor->pll.csi2.lanes : 1)); + sensor->pll.csi2.lanes : 1) << + (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0)); if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) return rval; @@ -3252,6 +3253,12 @@ static int ccs_probe(struct i2c_client *client) } else { sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL; } + if (CCS_LIM(sensor, CLOCK_CALCULATION) & + CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR) + sensor->pll.flags |= CCS_PLL_FLAG_OP_SYS_DDR; + if (CCS_LIM(sensor, CLOCK_CALCULATION) & + CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR) + sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_DDR; } sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; From patchwork Wed Sep 30 15:28:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809507 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13F8892C for ; Wed, 30 Sep 2020 15:29:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3B2620759 for ; Wed, 30 Sep 2020 15:29:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731069AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731054AbgI3P3P (ORCPT ); Wed, 30 Sep 2020 11:29:15 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 7C7BC634CF8 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 085/100] ccs: Print written register values Date: Wed, 30 Sep 2020 18:28:43 +0300 Message-Id: <20200930152858.8471-86-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This helps debugging register writes. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-reg-access.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index 02af2b0abdaf..2025e9ab6e91 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -338,6 +338,10 @@ int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val) put_unaligned_be16(CCS_REG_ADDR(reg), data); put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2); + dev_dbg(&client->dev, "writing reg 0x%4.4x value 0x%*.*x (%u)\n", + CCS_REG_ADDR(reg), ccs_reg_width(reg) << 1, + ccs_reg_width(reg) << 1, val, val); + r = ccs_write_retry(client, &msg); if (r) dev_err(&client->dev, From patchwork Wed Sep 30 15:28:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809515 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7899192C for ; Wed, 30 Sep 2020 15:29:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6685220759 for ; Wed, 30 Sep 2020 15:29:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728729AbgI3P3a (ORCPT ); Wed, 30 Sep 2020 11:29:30 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731056AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 8E661634CF9 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 086/100] ccs-pll: Print pixel rates Date: Wed, 30 Sep 2020 18:28:44 +0300 Message-Id: <20200930152858.8471-87-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Print pixel rates on CSI-2 bus as well as in pixel array as the variation allowed in PLL capabilities makes this non-trivial to figure out otherwise. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index cec811bb37a4..6abb6943ce3f 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -119,6 +119,11 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) } } + dev_dbg(dev, "pixel rate in pixel array:\t%u\n", + pll->pixel_rate_pixel_array); + dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n", + pll->pixel_rate_csi); + dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n", pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "", From patchwork Wed Sep 30 15:28:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809483 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D74892C for ; Wed, 30 Sep 2020 15:29:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 79D8320789 for ; Wed, 30 Sep 2020 15:29:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731085AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731057AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A23E6634CFA for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 087/100] ccs: Add support for obtaining C-PHY configuration from firmware Date: Wed, 30 Sep 2020 18:28:45 +0300 Message-Id: <20200930152858.8471-88-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Try parsing the firmware also as C-PHY. Do this only after D-PHY as older firmware may not explicitly specify bus-type in which case D-PHY is the default. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index a6d5164be8a0..00a1ea46f25a 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -2917,6 +2917,11 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev) { .bus_type = V4L2_MBUS_CCP2 }; rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); } + if (rval == -ENXIO) { + bus_cfg = (struct v4l2_fwnode_endpoint) + { .bus_type = V4L2_MBUS_CSI2_CPHY }; + rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + } if (rval) goto out_err; @@ -2925,6 +2930,10 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev) hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY; hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; break; + case V4L2_MBUS_CSI2_CPHY: + hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_CPHY; + hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; + break; case V4L2_MBUS_CCP2: hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ? SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE : From patchwork Wed Sep 30 15:28:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CF6B92C for ; Wed, 30 Sep 2020 15:29:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8910620789 for ; Wed, 30 Sep 2020 15:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731080AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731059AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id B713F634CFB for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 088/100] ccs: Add digital gain support Date: Wed, 30 Sep 2020 18:28:46 +0300 Message-Id: <20200930152858.8471-89-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CCS supports global (all-component) digital gain. Add support for it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 00a1ea46f25a..1cb46de003e5 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -669,6 +669,11 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_ANALOGUE_GAIN: rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val); + break; + + case V4L2_CID_DIGITAL_GAIN: + rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, ctrl->val); + break; case V4L2_CID_EXPOSURE: rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val); @@ -738,7 +743,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor) struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12); + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13); if (rval) return rval; @@ -752,6 +757,16 @@ static int ccs_init_controls(struct ccs_sensor *sensor) max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + CCS_LIM(sensor, DIGITAL_GAIN_MIN), + CCS_LIM(sensor, DIGITAL_GAIN_MAX), + max(CCS_LIM(sensor, DIGITAL_GAIN_STEP_SIZE), + 1U), + 0x100); + /* Exposure limits will be updated soon, use just something here. */ sensor->exposure = v4l2_ctrl_new_std( &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, From patchwork Wed Sep 30 15:28:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809495 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D858B618 for ; Wed, 30 Sep 2020 15:29:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1161208B8 for ; Wed, 30 Sep 2020 15:29:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731082AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731039AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id C9BF6634CFC for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 089/100] ccs: Add support for old-style SMIA digital gain Date: Wed, 30 Sep 2020 18:28:47 +0300 Message-Id: <20200930152858.8471-90-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org SMIA only has per-component digital gain. Add support for it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 33 +++++++++++++++++++++++-- drivers/media/i2c/ccs/smiapp-reg-defs.h | 2 ++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 1cb46de003e5..37016855df43 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -672,7 +672,34 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_DIGITAL_GAIN: - rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, ctrl->val); + if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) { + rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, + ctrl->val); + break; + } + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_GREENR, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_RED, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_BLUE, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_GREENB, + ctrl->val); break; case V4L2_CID_EXPOSURE: @@ -758,7 +785,9 @@ static int ccs_init_controls(struct ccs_sensor *sensor) CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == - CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || + CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL) v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN, CCS_LIM(sensor, DIGITAL_GAIN_MIN), diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h index e80c110ebf3a..177e3e51207a 100644 --- a/drivers/media/i2c/ccs/smiapp-reg-defs.h +++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h @@ -535,6 +535,8 @@ #define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0 #define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1 +#define SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL 1 + #define SMIAPP_BINNING_CAPABILITY_NO 0 #define SMIAPP_BINNING_CAPABILITY_YES 1 From patchwork Wed Sep 30 15:28:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C9AC618 for ; Wed, 30 Sep 2020 15:29:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C0FE20789 for ; Wed, 30 Sep 2020 15:29:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731097AbgI3P32 (ORCPT ); Wed, 30 Sep 2020 11:29:28 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44656 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731063AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id DDBCA634D07 for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 090/100] ccs: Remove analogue gain field Date: Wed, 30 Sep 2020 18:28:48 +0300 Message-Id: <20200930152858.8471-91-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The analogue gain control was stored to the device specific struct but was never used. Remove it. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 13 ++++++------- drivers/media/i2c/ccs/ccs.h | 1 - 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 37016855df43..0a59bc13ac56 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -776,13 +776,12 @@ static int ccs_init_controls(struct ccs_sensor *sensor) sensor->pixel_array->ctrl_handler.lock = &sensor->mutex; - sensor->analog_gain = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, - V4L2_CID_ANALOGUE_GAIN, - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), - max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), + max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 6b07e4143ff0..b97e55b57a69 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -262,7 +262,6 @@ struct ccs_sensor { unsigned long *valid_link_freqs; /* Pixel array controls */ - struct v4l2_ctrl *analog_gain; struct v4l2_ctrl *exposure; struct v4l2_ctrl *hflip; struct v4l2_ctrl *vflip; From patchwork Wed Sep 30 15:28:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809485 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D9E2618 for ; Wed, 30 Sep 2020 15:29:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1584F2087D for ; Wed, 30 Sep 2020 15:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731086AbgI3P3T (ORCPT ); Wed, 30 Sep 2020 11:29:19 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731064AbgI3P3Q (ORCPT ); Wed, 30 Sep 2020 11:29:16 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id F0CB4634D0D for ; Wed, 30 Sep 2020 18:28:53 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 091/100] ccs: Only add analogue gain control if the device supports it Date: Wed, 30 Sep 2020 18:28:49 +0300 Message-Id: <20200930152858.8471-92-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some devices do not implement analogue gain this way. Only add the control when a device does have the support. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 0a59bc13ac56..0b0165f5a28b 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -776,12 +776,16 @@ static int ccs_init_controls(struct ccs_sensor *sensor) sensor->pixel_array->ctrl_handler.lock = &sensor->mutex; - v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, - V4L2_CID_ANALOGUE_GAIN, - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), - max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) { + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), + max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), + 1U), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + } if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || From patchwork Wed Sep 30 15:28:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809503 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4AE1618 for ; Wed, 30 Sep 2020 15:29:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1CC220789 for ; Wed, 30 Sep 2020 15:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731094AbgI3P3Z (ORCPT ); Wed, 30 Sep 2020 11:29:25 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44648 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731065AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 100A2634D0E for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 092/100] v4l: Add user control base for CCS controls Date: Wed, 30 Sep 2020 18:28:50 +0300 Message-Id: <20200930152858.8471-93-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a control base for CCS controls, and reserve 128 controls. More are expected. Luckily these numbers are cheap. Signed-off-by: Sakari Ailus --- include/uapi/linux/v4l2-controls.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index a184c4939438..a84df4cfd03c 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -198,6 +198,12 @@ enum v4l2_colorfx { */ #define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0) +/* + * The base for MIPI CCS driver controls. + * We reserve 128 controls for this driver. + */ +#define V4L2_CID_USER_CCS_BASE (V4L2_CID_USER_BASE + 0x10e0) + /* MPEG-class control IDs */ /* The MPEG controls are applicable to all codec controls * and the 'MPEG' part of the define is historical */ From patchwork Wed Sep 30 15:28:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809487 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B30F13B2 for ; Wed, 30 Sep 2020 15:29:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 764B52087D for ; Wed, 30 Sep 2020 15:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729395AbgI3P3T (ORCPT ); Wed, 30 Sep 2020 11:29:19 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44682 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731068AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 2479C634C8D for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 093/100] v4l: uapi: Add controls for analogue gain constants Date: Wed, 30 Sep 2020 18:28:51 +0300 Message-Id: <20200930152858.8471-94-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a V4L2 controls for analogue gai constants required to control analogue gain. The values are device specific and thus need to be obtained from the driver. Signed-off-by: Sakari Ailus --- include/uapi/linux/ccs.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/uapi/linux/ccs.h diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h new file mode 100644 index 000000000000..bcdce95955b0 --- /dev/null +++ b/include/uapi/linux/ccs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only AND BSD-3-Clause */ +/* Copyright (C) 2020 Intel Corporation */ + +#ifndef __UAPI_CCS_H__ +#define __UAPI_CCS_H__ + +#include + +#define V4L2_CID_CCS_ANALOGUE_GAIN_M0 (V4L2_CID_USER_CCS_BASE + 1) +#define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2) +#define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3) +#define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4) + +#endif From patchwork Wed Sep 30 15:28:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809493 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3BD8618 for ; Wed, 30 Sep 2020 15:29:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C70AF207FB for ; Wed, 30 Sep 2020 15:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731068AbgI3P3U (ORCPT ); Wed, 30 Sep 2020 11:29:20 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44670 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731070AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 37457634CC1 for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 094/100] ccs: Add support for analogue gain coefficient controls Date: Wed, 30 Sep 2020 18:28:52 +0300 Message-Id: <20200930152858.8471-95-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add four controls for reading CCS analogue gain coefficients. The values are constants that are device specific. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 38 ++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 0b0165f5a28b..21afdf70038d 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "ccs.h" @@ -770,14 +771,46 @@ static int ccs_init_controls(struct ccs_sensor *sensor) struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 13); + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17); if (rval) return rval; sensor->pixel_array->ctrl_handler.lock = &sensor->mutex; switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) { - case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: { + struct { + const char *name; + u32 id; + s32 value; + } const gain_ctrls[] = { + { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0, + CCS_LIM(sensor, ANALOG_GAIN_M0), }, + { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0, + CCS_LIM(sensor, ANALOG_GAIN_C0), }, + { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1, + CCS_LIM(sensor, ANALOG_GAIN_M1), }, + { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1, + CCS_LIM(sensor, ANALOG_GAIN_C1), }, + }; + struct v4l2_ctrl_config ctrl_cfg = { + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &ccs_ctrl_ops, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + .step = 1, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) { + ctrl_cfg.name = gain_ctrls[i].name; + ctrl_cfg.id = gain_ctrls[i].id; + ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def = + gain_ctrls[i].value; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), @@ -786,6 +819,7 @@ static int ccs_init_controls(struct ccs_sensor *sensor) 1U), CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); } + } if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || From patchwork Wed Sep 30 15:28:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE94192C for ; Wed, 30 Sep 2020 15:29:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8D7120789 for ; Wed, 30 Sep 2020 15:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731096AbgI3P31 (ORCPT ); Wed, 30 Sep 2020 11:29:27 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44644 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731071AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 4B710634C89 for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 095/100] v4l: uapi: Add controls for CCS alternative analogue gain Date: Wed, 30 Sep 2020 18:28:53 +0300 Message-Id: <20200930152858.8471-96-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add two new controls for alternative analogue gain some CCS compliant camera sensors support. Signed-off-by: Sakari Ailus --- include/uapi/linux/ccs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h index bcdce95955b0..f22afa58b446 100644 --- a/include/uapi/linux/ccs.h +++ b/include/uapi/linux/ccs.h @@ -10,5 +10,7 @@ #define V4L2_CID_CCS_ANALOGUE_GAIN_C0 (V4L2_CID_USER_CCS_BASE + 2) #define V4L2_CID_CCS_ANALOGUE_GAIN_M1 (V4L2_CID_USER_CCS_BASE + 3) #define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4) +#define V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN (V4L2_CID_USER_CCS_BASE + 5) +#define V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN (V4L2_CID_USER_CCS_BASE + 6) #endif From patchwork Wed Sep 30 15:28:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809497 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A80FF618 for ; Wed, 30 Sep 2020 15:29:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95A4520789 for ; Wed, 30 Sep 2020 15:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731089AbgI3P3X (ORCPT ); Wed, 30 Sep 2020 11:29:23 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44690 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731076AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 5D167634CC0 for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 096/100] ccs: Add support for alternate analogue global gain Date: Wed, 30 Sep 2020 18:28:54 +0300 Message-Id: <20200930152858.8471-97-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CCS spec defines an alternative implementation for global analogue gain. Add support for that in the driver. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 55 ++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 21afdf70038d..c68c11e8e9f3 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -672,6 +672,17 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) break; + case V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN: + rval = ccs_write(sensor, ANALOG_LINEAR_GAIN_GLOBAL, ctrl->val); + + break; + + case V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN: + rval = ccs_write(sensor, ANALOG_EXPONENTIAL_GAIN_GLOBAL, + ctrl->val); + + break; + case V4L2_CID_DIGITAL_GAIN: if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) { @@ -818,6 +829,50 @@ static int ccs_init_controls(struct ccs_sensor *sensor) max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + } + break; + + case CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL: { + struct { + const char *name; + u32 id; + u16 min, max, step; + } const gain_ctrls[] = { + { + "Analogue Linear Gain", + V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN, + CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MIN), + CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MAX), + max(CCS_LIM(sensor, + ANALOG_LINEAR_GAIN_STEP_SIZE), + 1U), + }, + { + "Analogue Exponential Gain", + V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN, + CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MIN), + CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MAX), + max(CCS_LIM(sensor, + ANALOG_EXPONENTIAL_GAIN_STEP_SIZE), + 1U), + }, + }; + struct v4l2_ctrl_config ctrl_cfg = { + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &ccs_ctrl_ops, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) { + ctrl_cfg.name = gain_ctrls[i].name; + ctrl_cfg.min = ctrl_cfg.def = gain_ctrls[i].min; + ctrl_cfg.max = gain_ctrls[i].max; + ctrl_cfg.step = gain_ctrls[i].step; + ctrl_cfg.id = gain_ctrls[i].id; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } } } From patchwork Wed Sep 30 15:28:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809501 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2E89618 for ; Wed, 30 Sep 2020 15:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F7FC20789 for ; Wed, 30 Sep 2020 15:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731093AbgI3P3Y (ORCPT ); Wed, 30 Sep 2020 11:29:24 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44664 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731048AbgI3P3R (ORCPT ); Wed, 30 Sep 2020 11:29:17 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 6CF47634CBE for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 097/100] ccs: Add debug prints for MSR registers Date: Wed, 30 Sep 2020 18:28:55 +0300 Message-Id: <20200930152858.8471-98-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Also print out MSR registers written to the sensor. This isn't entirely optimal as the debug strings are produced even if they're not used but that isn't really a grave issue --- the I²C bus is very slow anyway. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-reg-access.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index 2025e9ab6e91..c600f143a1b9 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -387,12 +387,20 @@ int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs, for (j = 0; j < regs->len; j += msg.len - 2, regdata += msg.len - 2) { + char printbuf[(MAX_WRITE_LEN << 1) + 1 /* nil */] = + { 0 }; int rval; msg.len = min(regs->len - j, MAX_WRITE_LEN); + bin2hex(printbuf, regdata, msg.len); + dev_dbg(&client->dev, + "writing msr reg 0x%4.4x value 0x%s\n", + regs->addr + j, printbuf); + put_unaligned_be16(regs->addr + j, buf); memcpy(buf + 2, regdata, msg.len); + msg.len += 2; rval = ccs_write_retry(client, &msg); From patchwork Wed Sep 30 15:28:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809499 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E1A513B2 for ; Wed, 30 Sep 2020 15:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A42A20789 for ; Wed, 30 Sep 2020 15:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731092AbgI3P3Y (ORCPT ); Wed, 30 Sep 2020 11:29:24 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44636 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731074AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 7E8D6634D0F for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 098/100] v4l: uapi: Add CCS controls for correction configuration and capabilities Date: Wed, 30 Sep 2020 18:28:56 +0300 Message-Id: <20200930152858.8471-99-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add V4L2 controls for controlling CCS lens shading correction as well as conveying its capabilities. Signed-off-by: Sakari Ailus --- include/uapi/linux/ccs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/ccs.h b/include/uapi/linux/ccs.h index f22afa58b446..877229ce4a36 100644 --- a/include/uapi/linux/ccs.h +++ b/include/uapi/linux/ccs.h @@ -12,5 +12,10 @@ #define V4L2_CID_CCS_ANALOGUE_GAIN_C1 (V4L2_CID_USER_CCS_BASE + 4) #define V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN (V4L2_CID_USER_CCS_BASE + 5) #define V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN (V4L2_CID_USER_CCS_BASE + 6) +#define V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY (V4L2_CID_USER_CCS_BASE + 7) +#define V4L2_CCS_SHADING_CORRECTION_COLOUR (1U << 0) +#define V4L2_CCS_SHADING_CORRECTION_LUMINANCE (1U << 1) +#define V4L2_CID_CCS_SHADING_CORRECTION (V4L2_CID_USER_CCS_BASE + 8) +#define V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION (V4L2_CID_USER_CCS_BASE + 9) #endif From patchwork Wed Sep 30 15:28:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809491 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4466392C for ; Wed, 30 Sep 2020 15:29:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33910208B8 for ; Wed, 30 Sep 2020 15:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731077AbgI3P3V (ORCPT ); Wed, 30 Sep 2020 11:29:21 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731073AbgI3P3T (ORCPT ); Wed, 30 Sep 2020 11:29:19 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 92451634C8E for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 099/100] ccs: Add shading correction and luminance correction level controls Date: Wed, 30 Sep 2020 18:28:57 +0300 Message-Id: <20200930152858.8471-100-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add controls for supporting lens shading correction. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 74 ++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index c68c11e8e9f3..d2ffb48c9a30 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -755,6 +755,25 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_TEST_PATTERN_GREENB: rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val); + break; + case V4L2_CID_CCS_SHADING_CORRECTION: + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING | + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION))) + break; + + rval = ccs_write(sensor, SHADING_CORRECTION_EN, + ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE : + 0); + + break; + case V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION: + if (!(CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) + break; + + rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val); + break; case V4L2_CID_PIXEL_RATE: /* For v4l2_ctrl_s_ctrl_int64() used internally. */ @@ -876,6 +895,61 @@ static int ccs_init_controls(struct ccs_sensor *sensor) } } + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) { + const struct v4l2_ctrl_config ctrl_cfg = { + .name = "Shading Correction", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .id = V4L2_CID_CCS_SHADING_CORRECTION, + .ops = &ccs_ctrl_ops, + .max = 1, + .step = 1, + }; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) { + const struct v4l2_ctrl_config ctrl_cfg = { + .name = "Luminance Shading Correction", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .id = V4L2_CID_CCS_LUMINANCE_SHADING_CORRECTION, + .ops = &ccs_ctrl_ops, + .max = 255, + .step = 1, + .def = 128, + }; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING | + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) { + u32 val = + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING) ? + V4L2_CCS_SHADING_CORRECTION_COLOUR : 0) | + ((CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) ? + V4L2_CCS_SHADING_CORRECTION_LUMINANCE : 0); + const struct v4l2_ctrl_config ctrl_cfg = { + .name = "Shading Correction Capability", + .type = V4L2_CTRL_TYPE_BITMASK, + .id = V4L2_CID_CCS_SHADING_CORRECTION_CAPABILITY, + .ops = &ccs_ctrl_ops, + .max = val, + .def = val, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == From patchwork Wed Sep 30 15:28:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809489 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B65A4618 for ; Wed, 30 Sep 2020 15:29:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EA612071E for ; Wed, 30 Sep 2020 15:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730806AbgI3P3U (ORCPT ); Wed, 30 Sep 2020 11:29:20 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44680 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731077AbgI3P3S (ORCPT ); Wed, 30 Sep 2020 11:29:18 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id A734E634D10 for ; Wed, 30 Sep 2020 18:28:54 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 100/100] smiapp: Add CCS ACPI device ID Date: Wed, 30 Sep 2020 18:28:58 +0300 Message-Id: <20200930152858.8471-101-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CCS compliant sensors use device ID "MIPI0200". Use this id for ACPI device matching. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs/ccs-core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index d2ffb48c9a30..313754515165 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3596,6 +3596,12 @@ static const struct ccs_device smia_device = { static const struct ccs_device ccs_device = {}; +static const struct acpi_device_id ccs_acpi_table[] = { + { .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, ccs_acpi_table); + static const struct of_device_id ccs_of_table[] = { { .compatible = "nokia,smia", .data = &smia_device }, { .compatible = "mipi,ccs", .data = &ccs_device }, @@ -3610,6 +3616,7 @@ static const struct dev_pm_ops ccs_pm_ops = { static struct i2c_driver ccs_i2c_driver = { .driver = { + .acpi_match_table = ccs_acpi_table, .of_match_table = ccs_of_table, .name = CCS_NAME, .pm = &ccs_pm_ops,