From patchwork Sat Oct 3 03:29:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 11814953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0CC906CB for ; Sat, 3 Oct 2020 03:30:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E02122078A for ; Sat, 3 Oct 2020 03:30:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E02122078A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 607196EA28; Sat, 3 Oct 2020 03:30:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E94A6EA27 for ; Sat, 3 Oct 2020 03:30:01 +0000 (UTC) IronPort-SDR: p+PAUR7+/NfeXMWt0E64DIKcRF5icHagP6fj+k0IDCDMX8GCTFpUVdp8mAFpbeNCrW7V5FHdpD i87PZvVvlLpw== X-IronPort-AV: E=McAfee;i="6000,8403,9762"; a="163992691" X-IronPort-AV: E=Sophos;i="5.77,330,1596524400"; d="scan'208";a="163992691" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2020 20:29:59 -0700 IronPort-SDR: cEHo5H4k5HGDzBsnmUCoq5qwg43Y5B3PfJvvRf+V/l/llB569AjWGZ7qXfLLpZ/q802dq2XBHO Uv89+80JRaYQ== X-IronPort-AV: E=Sophos;i="5.77,330,1596524400"; d="scan'208";a="326022170" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2020 20:29:58 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Fri, 2 Oct 2020 20:29:50 -0700 Message-Id: <20201003032951.2730073-2-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20201003032951.2730073-1-matthew.d.roper@intel.com> References: <20201003032951.2730073-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Update gen12 forcewake table X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The bspec's forcewake page was very stale and out of date for recent platforms. The hardware team finally provided us with an updated gen12 table (which applies to TGL, RKL, and DG1) and there are a lot of changes. Bspec: 66696 Cc: Caz Yokoyama Cc: Daniele Ceraolo Spurio Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_uncore.c | 66 +++++++++++++++++------------ 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 263ffcb832b7..e14dbc1c7e22 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1124,44 +1124,58 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = { GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) }; -/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ +/* + * *Must* be sorted by offset ranges! See intel_fw_table_check(). + * + * Note that the spec lists several reserved/unused ranges that don't + * actually contain any registers. In the table below we'll combine those + * reserved ranges with either the preceding or following range to keep the + * table small and lookups fast. + */ static const struct intel_forcewake_range __gen12_fw_ranges[] = { - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ + GEN_FW_RANGE(0x0, 0x1fff, 0), GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x8180, 0x81ff, 0), + GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL), + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x9560, 0x97ff, 0), GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER), - GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), - GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xd000, 0xd7ff, 0), + GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24000, 0x2417f, 0), + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), + GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), + GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0x40000, 0x1bffff, 0), GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), - GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), + GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), - GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), - GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), - GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) }; static void From patchwork Sat Oct 3 03:29:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 11814949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D4736CB for ; Sat, 3 Oct 2020 03:30:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 76685207FB for ; Sat, 3 Oct 2020 03:30:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 76685207FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 44DF26EA25; Sat, 3 Oct 2020 03:30:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7875B6EA25 for ; Sat, 3 Oct 2020 03:30:01 +0000 (UTC) IronPort-SDR: 4Oa6E2vjAN2HaAb/aI6xJ6nsIvAiJfo+tPyfPyTC7T8glqCRVTc956UIrGZuPMYDwTCKEIR1DZ 57urTWp1U31g== X-IronPort-AV: E=McAfee;i="6000,8403,9762"; a="163992696" X-IronPort-AV: E=Sophos;i="5.77,330,1596524400"; d="scan'208";a="163992696" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2020 20:30:01 -0700 IronPort-SDR: PZ3ZhDfqoZNjRVXwn4Cm0KvJrwFflf6MjQUtXdQvyQxlJiaK7aYwE1RxkX1rC4JMlmfUdCLgKD DXVTYRYwzedQ== X-IronPort-AV: E=Sophos;i="5.77,330,1596524400"; d="scan'208";a="326022182" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2020 20:30:01 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Fri, 2 Oct 2020 20:29:51 -0700 Message-Id: <20201003032951.2730073-3-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20201003032951.2730073-1-matthew.d.roper@intel.com> References: <20201003032951.2730073-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Update gen12 multicast register ranges X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The updated bspec forcewake table also provides us with new multicast ranges that should be reflected in our workaround code. Note that there are different types of multicast registers with different styles of replication and different steering registers. The i915 MCR range lists we're updating here are only used to ensure we can verify workarounds properly (i.e., if we can't steer register reads we don't want to verify workarounds where an unsteered read might hit a fused-off instance of the unit). Because of this, we don't need to include any of the multicast ranges where all instances of the register will always present and fusing doesn't play a role. Specifically, that means that we are not including the MCR ranges designated as "SQIDI" in the bspec. Bspec: 66696 Cc: Caz Yokoyama Cc: Daniele Ceraolo Spurio Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6c580d0d9ea8..78c5480c6401 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2031,10 +2031,12 @@ create_scratch(struct i915_address_space *vm, int count) return ERR_PTR(err); } -static const struct { +struct mcr_range { u32 start; u32 end; -} mcr_ranges_gen8[] = { +}; + +static const struct mcr_range mcr_ranges_gen8[] = { { .start = 0x5500, .end = 0x55ff }, { .start = 0x7000, .end = 0x7fff }, { .start = 0x9400, .end = 0x97ff }, @@ -2043,11 +2045,25 @@ static const struct { {}, }; +static const struct mcr_range mcr_ranges_gen12[] = { + { .start = 0x8150, .end = 0x815f }, + { .start = 0x9520, .end = 0x955f }, + { .start = 0xb100, .end = 0xb3ff }, + { .start = 0xde80, .end = 0xe8ff }, + { .start = 0x24a00, .end = 0x24a7f }, + {}, +}; + static bool mcr_range(struct drm_i915_private *i915, u32 offset) { + const struct mcr_range *mcr_ranges; int i; - if (INTEL_GEN(i915) < 8) + if (INTEL_GEN(i915) >= 12) + mcr_ranges = mcr_ranges_gen12; + else if (INTEL_GEN(i915) >= 8) + mcr_ranges = mcr_ranges_gen8; + else return false; /* @@ -2055,9 +2071,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset) * which only controls CPU initiated MMIO. Routing does not * work for CS access so we cannot verify them on this path. */ - for (i = 0; mcr_ranges_gen8[i].start; i++) - if (offset >= mcr_ranges_gen8[i].start && - offset <= mcr_ranges_gen8[i].end) + for (i = 0; mcr_ranges[i].start; i++) + if (offset >= mcr_ranges[i].start && + offset <= mcr_ranges[i].end) return true; return false;