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Tue, 06 Oct 2020 00:54:15 -0700 (PDT) From: Ikjoon Jang To: Rob Herring , Mark Brown , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v5 1/4] dt-bindings: spi: add mt8192-nor compatible string Date: Tue, 6 Oct 2020 15:54:02 +0800 Message-Id: <20201006155010.v5.1.I4cd089ef1fe576535c6b6e4f1778eaab1c4441cf@changeid> X-Mailer: git-send-email 2.28.0.806.g8561365e88-goog In-Reply-To: <20201006075405.11658-1-ikjn@chromium.org> References: <20201006075405.11658-1-ikjn@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_035418_421124_83D04061 X-CRM114-Status: GOOD ( 10.76 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.7 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , linux-kernel@vger.kernel.org, Bayi Cheng , linux-mediatek@lists.infradead.org, Matthias Brugger , Chuanhong Guo , Ikjoon Jang , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add MT8192 spi-nor controller support. Signed-off-by: Ikjoon Jang Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml index 42c9205ac991..55c239446a5b 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt7622-nor - mediatek,mt7623-nor - mediatek,mt7629-nor + - mediatek,mt8192-nor - enum: - mediatek,mt8173-nor - items: From patchwork Tue Oct 6 07:54:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ikjoon Jang X-Patchwork-Id: 11818303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB2816CA for ; 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Tue, 06 Oct 2020 00:54:18 -0700 (PDT) Received: from ikjn-p920.tpe.corp.google.com ([2401:fa00:1:10:f693:9fff:fef4:a8fc]) by smtp.gmail.com with ESMTPSA id r6sm2545147pfq.11.2020.10.06.00.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 00:54:17 -0700 (PDT) From: Ikjoon Jang To: Rob Herring , Mark Brown , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v5 2/4] spi: spi-mtk-nor: use dma_alloc_coherent() for bounce buffer Date: Tue, 6 Oct 2020 15:54:03 +0800 Message-Id: <20201006155010.v5.2.I06cb65401ab5ad63ea30c4788d26633928d80f38@changeid> X-Mailer: git-send-email 2.28.0.806.g8561365e88-goog In-Reply-To: <20201006075405.11658-1-ikjn@chromium.org> References: <20201006075405.11658-1-ikjn@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_035420_906304_EA23F06F X-CRM114-Status: GOOD ( 19.62 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1042 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.7 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthias Brugger , linux-mediatek@lists.infradead.org, Ikjoon Jang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Use dma_alloc_coherent() for bounce buffer instead of kmalloc() to make sure the bounce buffer to be allocated within its DMAable range. Signed-off-by: Ikjoon Jang --- drivers/spi/spi-mtk-nor.c | 94 ++++++++++++++++++++++----------------- 1 file changed, 52 insertions(+), 42 deletions(-) diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index ea39736de291..c11bed28b952 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -97,6 +97,7 @@ struct mtk_nor { struct device *dev; void __iomem *base; u8 *buffer; + dma_addr_t buffer_dma; struct clk *spi_clk; struct clk *ctlr_clk; unsigned int spi_freq; @@ -145,6 +146,11 @@ static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op) } } +static bool need_bounce(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK); +} + static bool mtk_nor_match_read(const struct spi_mem_op *op) { int dummy = 0; @@ -238,6 +244,8 @@ static void mtk_nor_adj_prg_size(struct spi_mem_op *op) static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { + struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); + if (!op->data.nbytes) return 0; @@ -251,8 +259,7 @@ static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) || (op->data.nbytes < MTK_NOR_DMA_ALIGN)) op->data.nbytes = 1; - else if (!((ulong)(op->data.buf.in) & - MTK_NOR_DMA_ALIGN_MASK)) + else if (!need_bounce(sp, op)) op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK; else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE) op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE; @@ -325,19 +332,12 @@ static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op) mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK); } -static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, unsigned int length, - u8 *buffer) +static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length, + dma_addr_t dma_addr) { int ret = 0; ulong delay; u32 reg; - dma_addr_t dma_addr; - - dma_addr = dma_map_single(sp->dev, buffer, length, DMA_FROM_DEVICE); - if (dma_mapping_error(sp->dev, dma_addr)) { - dev_err(sp->dev, "failed to map dma buffer.\n"); - return -EINVAL; - } writel(from, sp->base + MTK_NOR_REG_DMA_FADR); writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR); @@ -362,30 +362,49 @@ static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, unsigned int length, (delay + 1) * 100); } - dma_unmap_single(sp->dev, dma_addr, length, DMA_FROM_DEVICE); if (ret < 0) dev_err(sp->dev, "dma read timeout.\n"); return ret; } -static int mtk_nor_read_bounce(struct mtk_nor *sp, u32 from, - unsigned int length, u8 *buffer) +static int mtk_nor_read_bounce(struct mtk_nor *sp, const struct spi_mem_op *op) { unsigned int rdlen; int ret; - if (length & MTK_NOR_DMA_ALIGN_MASK) - rdlen = (length + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK; + if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK) + rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK; else - rdlen = length; + rdlen = op->data.nbytes; - ret = mtk_nor_read_dma(sp, from, rdlen, sp->buffer); - if (ret) - return ret; + ret = mtk_nor_dma_exec(sp, op->addr.val, rdlen, sp->buffer_dma); - memcpy(buffer, sp->buffer, length); - return 0; + if (!ret) + memcpy(op->data.buf.in, sp->buffer, op->data.nbytes); + + return ret; +} + +static int mtk_nor_read_dma(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + int ret; + dma_addr_t dma_addr; + + if (need_bounce(sp, op)) + return mtk_nor_read_bounce(sp, op); + + dma_addr = dma_map_single(sp->dev, op->data.buf.in, + op->data.nbytes, DMA_FROM_DEVICE); + + if (dma_mapping_error(sp->dev, dma_addr)) + return -EINVAL; + + ret = mtk_nor_dma_exec(sp, op->addr.val, op->data.nbytes, dma_addr); + + dma_unmap_single(sp->dev, dma_addr, op->data.nbytes, DMA_FROM_DEVICE); + + return ret; } static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op) @@ -566,15 +585,8 @@ static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (op->data.nbytes == 1) { mtk_nor_set_addr(sp, op); return mtk_nor_read_pio(sp, op); - } else if (((ulong)(op->data.buf.in) & - MTK_NOR_DMA_ALIGN_MASK)) { - return mtk_nor_read_bounce(sp, op->addr.val, - op->data.nbytes, - op->data.buf.in); } else { - return mtk_nor_read_dma(sp, op->addr.val, - op->data.nbytes, - op->data.buf.in); + return mtk_nor_read_dma(sp, op); } } @@ -729,7 +741,6 @@ static int mtk_nor_probe(struct platform_device *pdev) struct spi_controller *ctlr; struct mtk_nor *sp; void __iomem *base; - u8 *buffer; struct clk *spi_clk, *ctlr_clk; int ret, irq; @@ -745,16 +756,6 @@ static int mtk_nor_probe(struct platform_device *pdev) if (IS_ERR(ctlr_clk)) return PTR_ERR(ctlr_clk); - buffer = devm_kmalloc(&pdev->dev, - MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN, - GFP_KERNEL); - if (!buffer) - return -ENOMEM; - - if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK) - buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) & - ~MTK_NOR_DMA_ALIGN_MASK); - ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp)); if (!ctlr) { dev_err(&pdev->dev, "failed to allocate spi controller\n"); @@ -774,13 +775,22 @@ static int mtk_nor_probe(struct platform_device *pdev) sp = spi_controller_get_devdata(ctlr); sp->base = base; - sp->buffer = buffer; sp->has_irq = false; sp->wbuf_en = false; sp->ctlr = ctlr; sp->dev = &pdev->dev; sp->spi_clk = spi_clk; sp->ctlr_clk = ctlr_clk; + sp->buffer = dmam_alloc_coherent(&pdev->dev, + MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN, + &sp->buffer_dma, GFP_KERNEL); + if (!sp->buffer) + return -ENOMEM; + + if ((uintptr_t)sp->buffer & MTK_NOR_DMA_ALIGN_MASK) { + dev_err(sp->dev, "misaligned allocation of internal buffer.\n"); + return -ENOMEM; + } irq = platform_get_irq_optional(pdev, 0); if (irq < 0) { From patchwork Tue Oct 6 07:54:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ikjoon Jang X-Patchwork-Id: 11818301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 689436CA for ; Tue, 6 Oct 2020 07:54:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE3AB20760 for ; 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Tue, 06 Oct 2020 00:54:20 -0700 (PDT) Received: from ikjn-p920.tpe.corp.google.com ([2401:fa00:1:10:f693:9fff:fef4:a8fc]) by smtp.gmail.com with ESMTPSA id r6sm2545147pfq.11.2020.10.06.00.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 00:54:20 -0700 (PDT) From: Ikjoon Jang To: Rob Herring , Mark Brown , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v5 3/4] spi: spi-mtk-nor: support 36bit dma addressing Date: Tue, 6 Oct 2020 15:54:04 +0800 Message-Id: <20201006155010.v5.3.Id1cb208392928afc7ceed4de06924243c7858cd0@changeid> X-Mailer: git-send-email 2.28.0.806.g8561365e88-goog In-Reply-To: <20201006075405.11658-1-ikjn@chromium.org> References: <20201006075405.11658-1-ikjn@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_035423_031447_9A3C39EF X-CRM114-Status: GOOD ( 17.08 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.7 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthias Brugger , linux-mediatek@lists.infradead.org, Ikjoon Jang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org This patch enables 36bit dma address support to spi-mtk-nor. Currently this is enabled only for mt8192-nor. Signed-off-by: Ikjoon Jang --- drivers/spi/spi-mtk-nor.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index c11bed28b952..e46d5c93d742 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -79,6 +79,8 @@ #define MTK_NOR_REG_DMA_FADR 0x71c #define MTK_NOR_REG_DMA_DADR 0x720 #define MTK_NOR_REG_DMA_END_DADR 0x724 +#define MTK_NOR_REG_DMA_DADR_HB 0x738 +#define MTK_NOR_REG_DMA_END_DADR_HB 0x73c #define MTK_NOR_PRG_MAX_SIZE 6 // Reading DMA src/dst addresses have to be 16-byte aligned @@ -103,6 +105,7 @@ struct mtk_nor { unsigned int spi_freq; bool wbuf_en; bool has_irq; + bool high_dma; struct completion op_done; }; @@ -343,6 +346,13 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length, writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR); writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR); + if (sp->high_dma) { + writel(upper_32_bits(dma_addr), + sp->base + MTK_NOR_REG_DMA_DADR_HB); + writel(upper_32_bits(dma_addr + length), + sp->base + MTK_NOR_REG_DMA_END_DADR_HB); + } + if (sp->has_irq) { reinit_completion(&sp->op_done); mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0); @@ -731,7 +741,8 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops = { }; static const struct of_device_id mtk_nor_match[] = { - { .compatible = "mediatek,mt8173-nor" }, + { .compatible = "mediatek,mt8192-nor", .data = (void *)36 }, + { .compatible = "mediatek,mt8173-nor", .data = (void *)32 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_nor_match); @@ -743,6 +754,7 @@ static int mtk_nor_probe(struct platform_device *pdev) void __iomem *base; struct clk *spi_clk, *ctlr_clk; int ret, irq; + unsigned long dma_bits; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -756,6 +768,12 @@ static int mtk_nor_probe(struct platform_device *pdev) if (IS_ERR(ctlr_clk)) return PTR_ERR(ctlr_clk); + dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev); + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) { + dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits); + return -EINVAL; + } + ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp)); if (!ctlr) { dev_err(&pdev->dev, "failed to allocate spi controller\n"); @@ -781,6 +799,7 @@ static int mtk_nor_probe(struct platform_device *pdev) sp->dev = &pdev->dev; sp->spi_clk = spi_clk; sp->ctlr_clk = ctlr_clk; + sp->high_dma = (dma_bits > 32); sp->buffer = dmam_alloc_coherent(&pdev->dev, MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN, &sp->buffer_dma, GFP_KERNEL); From patchwork Tue Oct 6 07:54:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ikjoon Jang X-Patchwork-Id: 11818305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DC8B6CA for ; Tue, 6 Oct 2020 07:55:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23B0020760 for ; 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Tue, 06 Oct 2020 00:54:23 -0700 (PDT) Received: from ikjn-p920.tpe.corp.google.com ([2401:fa00:1:10:f693:9fff:fef4:a8fc]) by smtp.gmail.com with ESMTPSA id r6sm2545147pfq.11.2020.10.06.00.54.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 00:54:22 -0700 (PDT) From: Ikjoon Jang To: Rob Herring , Mark Brown , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v5 4/4] spi: spi-mtk-nor: Add power management support Date: Tue, 6 Oct 2020 15:54:05 +0800 Message-Id: <20201006155010.v5.4.I68983b582d949a91866163bab588ff3c2a0d0275@changeid> X-Mailer: git-send-email 2.28.0.806.g8561365e88-goog In-Reply-To: <20201006075405.11658-1-ikjn@chromium.org> References: <20201006075405.11658-1-ikjn@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_035426_300971_B9D79624 X-CRM114-Status: GOOD ( 19.88 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.7 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthias Brugger , linux-mediatek@lists.infradead.org, Ikjoon Jang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org This patch adds dev_pm_ops to mtk-nor to support suspend/resume, auto suspend delay is set to -1 by default. Accessing registers are only permitted after its clock is enabled to deal with unknown state of operating clk at probe time. Signed-off-by: Ikjoon Jang --- drivers/spi/spi-mtk-nor.c | 98 ++++++++++++++++++++++++++++++--------- 1 file changed, 76 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index e46d5c93d742..b97f26a60cbe 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -690,22 +691,15 @@ static int mtk_nor_enable_clk(struct mtk_nor *sp) return 0; } -static int mtk_nor_init(struct mtk_nor *sp) +static void mtk_nor_init(struct mtk_nor *sp) { - int ret; - - ret = mtk_nor_enable_clk(sp); - if (ret) - return ret; - - sp->spi_freq = clk_get_rate(sp->spi_clk); + writel(0, sp->base + MTK_NOR_REG_IRQ_EN); + writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT); writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP); mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0); mtk_nor_rmw(sp, MTK_NOR_REG_CFG3, MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0); - - return ret; } static irqreturn_t mtk_nor_irq_handler(int irq, void *data) @@ -788,6 +782,7 @@ static int mtk_nor_probe(struct platform_device *pdev) ctlr->num_chipselect = 1; ctlr->setup = mtk_nor_setup; ctlr->transfer_one_message = mtk_nor_transfer_one_message; + ctlr->auto_runtime_pm = true; dev_set_drvdata(&pdev->dev, ctlr); @@ -811,12 +806,19 @@ static int mtk_nor_probe(struct platform_device *pdev) return -ENOMEM; } + ret = mtk_nor_enable_clk(sp); + if (ret < 0) + return ret; + + sp->spi_freq = clk_get_rate(sp->spi_clk); + + mtk_nor_init(sp); + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0) { dev_warn(sp->dev, "IRQ not available."); } else { - writel(MTK_NOR_IRQ_MASK, base + MTK_NOR_REG_IRQ_STAT); - writel(0, base + MTK_NOR_REG_IRQ_EN); ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0, pdev->name, sp); if (ret < 0) { @@ -827,34 +829,86 @@ static int mtk_nor_probe(struct platform_device *pdev) } } - ret = mtk_nor_init(sp); - if (ret < 0) { - kfree(ctlr); - return ret; - } + pm_runtime_set_autosuspend_delay(&pdev->dev, -1); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + + ret = devm_spi_register_controller(&pdev->dev, ctlr); + if (ret < 0) + goto err_probe; + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq); - return devm_spi_register_controller(&pdev->dev, ctlr); + return 0; + +err_probe: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + + mtk_nor_disable_clk(sp); + + return ret; } static int mtk_nor_remove(struct platform_device *pdev) { - struct spi_controller *ctlr; - struct mtk_nor *sp; + struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); + struct mtk_nor *sp = spi_controller_get_devdata(ctlr); - ctlr = dev_get_drvdata(&pdev->dev); - sp = spi_controller_get_devdata(ctlr); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + + mtk_nor_disable_clk(sp); + + return 0; +} + +static int __maybe_unused mtk_nor_runtime_suspend(struct device *dev) +{ + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct mtk_nor *sp = spi_controller_get_devdata(ctlr); mtk_nor_disable_clk(sp); return 0; } +static int __maybe_unused mtk_nor_runtime_resume(struct device *dev) +{ + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct mtk_nor *sp = spi_controller_get_devdata(ctlr); + + return mtk_nor_enable_clk(sp); +} + +static int __maybe_unused mtk_nor_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int __maybe_unused mtk_nor_resume(struct device *dev) +{ + return pm_runtime_force_resume(dev); +} + +static const struct dev_pm_ops mtk_nor_pm_ops = { + SET_RUNTIME_PM_OPS(mtk_nor_runtime_suspend, + mtk_nor_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(mtk_nor_suspend, mtk_nor_resume) +}; + static struct platform_driver mtk_nor_driver = { .driver = { .name = DRIVER_NAME, .of_match_table = mtk_nor_match, + .pm = &mtk_nor_pm_ops, }, .probe = mtk_nor_probe, .remove = mtk_nor_remove,