From patchwork Tue Oct 6 14:33:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818743 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5CB2139A for ; Tue, 6 Oct 2020 14:34:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5DD0C204EF for ; Tue, 6 Oct 2020 14:34:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5DD0C204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8854E6E49A; Tue, 6 Oct 2020 14:34:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 45BCC6E49A for ; Tue, 6 Oct 2020 14:34:08 +0000 (UTC) IronPort-SDR: /oa8BJHSc3m2sRMMlcz7MxzMTGJqH8AvAoJEUjO1MgUSXZp5sy9OrJ9WZ8AFzM17TNE9m/BofB RK2aqBrLHX0Q== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="143907279" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="143907279" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:33:54 -0700 IronPort-SDR: HaxCxXZrs74ig8wWXX50wC8aiK7Zq/ZJJEwffLVf9LAwAT1fWfYObnonUTvSWapVsWrLSSp4A5 37uRR0lE49Pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="418216921" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 06 Oct 2020 07:33:52 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:33:52 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:30 +0300 Message-Id: <20201006143349.5561-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move the DSC stuff out from the middle of the ICP HPD register definitions. The location seems to have been selected by a dice roll. SHPD_FILTER_CNT addition also went astray due to the DSC mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT(). Signed-off-by: Ville Syrjälä Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++---------------- 1 file changed, 107 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6ad9ee4243a0..efe51a4ef719 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4618,6 +4618,110 @@ enum { #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) +/* Icelake DSC Rate Control Range Parameter Registers */ +#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) +#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) +#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) +#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) +#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) +#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) +#define RC_BPG_OFFSET_SHIFT 10 +#define RC_MAX_QP_SHIFT 5 +#define RC_MIN_QP_SHIFT 0 + +#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) +#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) +#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) +#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) +#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) +#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) + +#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) +#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) +#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) +#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) +#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) +#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) + +#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) +#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) +#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) +#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) +#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) +#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) +#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) @@ -8305,117 +8409,12 @@ enum { #define SHOTPLUG_CTL_TC _MMIO(0xc4034) #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) - -#define SHPD_FILTER_CNT _MMIO(0xc4038) -#define SHPD_FILTER_CNT_500_ADJ 0x001D9 - -/* Icelake DSC Rate Control Range Parameter Registers */ -#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) -#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) -#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) -#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) -#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) -#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) -#define RC_BPG_OFFSET_SHIFT 10 -#define RC_MAX_QP_SHIFT 5 -#define RC_MIN_QP_SHIFT 0 - -#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) -#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) -#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) -#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) -#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) -#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) - -#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) -#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) -#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) -#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) -#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) -#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) - -#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) -#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) -#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) -#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) -#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) -#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) -#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) - #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) +#define SHPD_FILTER_CNT _MMIO(0xc4038) +#define SHPD_FILTER_CNT_500_ADJ 0x001D9 + #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \ From patchwork Tue Oct 6 14:33:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2377F139A for ; Tue, 6 Oct 2020 14:34:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB420204EF for ; Tue, 6 Oct 2020 14:34:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB420204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DA2E898F0; Tue, 6 Oct 2020 14:34:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 277D789864 for ; Tue, 6 Oct 2020 14:34:22 +0000 (UTC) IronPort-SDR: SjvmpNcf44lq09MBDBhJpy8Fu6OOcsBssOf2YIzXm2X+81SXQ6gl7ccup7E5Jkk/w+rwosNOmS R2B4WNCMTH9Q== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="164585314" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="164585314" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:33:57 -0700 IronPort-SDR: zGfQTFH4BQ2QBhTOoKUocP7lqvE53esZSAcQev9ko8IIkRdtPLPsGxk7qHFbpPkYKEBGLW/EvG qfUn7nm9x4Vw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="297134235" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga008.fm.intel.com with SMTP; 06 Oct 2020 07:33:55 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:33:54 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:31 +0300 Message-Id: <20201006143349.5561-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/20] drm/i915: s/PORT_TC/TC_PORT_TC/ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Make the namespacing for enum tc_port better by adding the TC_ to the actual enum values. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display.h | 14 ++-- drivers/gpu/drm/i915/display/intel_tc.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 78 ++++++++++---------- drivers/gpu/drm/i915/i915_reg.h | 60 +++++++-------- 5 files changed, 78 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 907e1d155443..32d24c60ff96 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7367,7 +7367,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) { if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) - return PORT_TC_NONE; + return TC_PORT_NONE; if (INTEL_GEN(dev_priv) >= 12) return port - PORT_D; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index d10b7c8cde3f..8c93253cbd95 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -243,14 +243,14 @@ static inline const char *port_identifier(enum port port) } enum tc_port { - PORT_TC_NONE = -1, + TC_PORT_NONE = -1, - PORT_TC1 = 0, - PORT_TC2, - PORT_TC3, - PORT_TC4, - PORT_TC5, - PORT_TC6, + TC_PORT_TC1 = 0, + TC_PORT_TC2, + TC_PORT_TC3, + TC_PORT_TC4, + TC_PORT_TC5, + TC_PORT_TC6, I915_MAX_TC_PORTS }; diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 8f67aef18b2d..1cb548d757e1 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) enum port port = dig_port->base.port; enum tc_port tc_port = intel_port_to_tc(i915, port); - if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE)) + if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) return; snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b753c77c9a77..d9438194c2f0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { }; static const u32 hpd_gen11[HPD_NUM_PINS] = { - [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), - [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), - [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), - [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), - [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5), - [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6), + [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_TC1) | GEN11_TBT_HOTPLUG(TC_PORT_TC1), + [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_TC2) | GEN11_TBT_HOTPLUG(TC_PORT_TC2), + [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_TC3) | GEN11_TBT_HOTPLUG(TC_PORT_TC3), + [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_TC4) | GEN11_TBT_HOTPLUG(TC_PORT_TC4), + [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_TC5) | GEN11_TBT_HOTPLUG(TC_PORT_TC5), + [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_TC6) | GEN11_TBT_HOTPLUG(TC_PORT_TC6), }; static const u32 hpd_icp[HPD_NUM_PINS] = { [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C), - [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1), - [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2), - [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3), - [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4), - [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5), - [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6), + [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1), + [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2), + [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3), + [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC4), + [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC5), + [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC6), }; static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -1035,17 +1035,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { case HPD_PORT_TC1: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC1); case HPD_PORT_TC2: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC2); case HPD_PORT_TC3: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC3); case HPD_PORT_TC4: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC4); case HPD_PORT_TC5: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC5); case HPD_PORT_TC6: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC6); default: return false; } @@ -1083,17 +1083,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { case HPD_PORT_TC1: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC1); case HPD_PORT_TC2: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC2); case HPD_PORT_TC3: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC3); case HPD_PORT_TC4: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC4); case HPD_PORT_TC5: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC5); case HPD_PORT_TC6: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6); + return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC6); default: return false; } @@ -1872,7 +1872,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) tc_hotplug_trigger = 0; } else if (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; - tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1); + tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_TC1); } else { drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv), "Unrecognized PCH type 0x%x\n", @@ -3238,7 +3238,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) { icp_hpd_irq_setup(dev_priv, - ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1)); + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_TC1)); } /* @@ -3257,21 +3257,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) u32 hotplug; hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6); I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } @@ -3652,7 +3652,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); } else if (HAS_PCH_MCC(dev_priv)) { icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1)); + icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_TC1)); } else { icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index efe51a4ef719..2e378d9b21c5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7865,19 +7865,19 @@ enum { #define GEN11_DE_HPD_IIR _MMIO(0x44478) #define GEN11_DE_HPD_IER _MMIO(0x4447c) #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) -#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \ - GEN11_TC_HOTPLUG(PORT_TC5) | \ - GEN11_TC_HOTPLUG(PORT_TC4) | \ - GEN11_TC_HOTPLUG(PORT_TC3) | \ - GEN11_TC_HOTPLUG(PORT_TC2) | \ - GEN11_TC_HOTPLUG(PORT_TC1)) +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_TC6) | \ + GEN11_TC_HOTPLUG(TC_PORT_TC5) | \ + GEN11_TC_HOTPLUG(TC_PORT_TC4) | \ + GEN11_TC_HOTPLUG(TC_PORT_TC3) | \ + GEN11_TC_HOTPLUG(TC_PORT_TC2) | \ + GEN11_TC_HOTPLUG(TC_PORT_TC1)) #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) -#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \ - GEN11_TBT_HOTPLUG(PORT_TC5) | \ - GEN11_TBT_HOTPLUG(PORT_TC4) | \ - GEN11_TBT_HOTPLUG(PORT_TC3) | \ - GEN11_TBT_HOTPLUG(PORT_TC2) | \ - GEN11_TBT_HOTPLUG(PORT_TC1)) +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_TC6) | \ + GEN11_TBT_HOTPLUG(TC_PORT_TC5) | \ + GEN11_TBT_HOTPLUG(TC_PORT_TC4) | \ + GEN11_TBT_HOTPLUG(TC_PORT_TC3) | \ + GEN11_TBT_HOTPLUG(TC_PORT_TC2) | \ + GEN11_TBT_HOTPLUG(TC_PORT_TC1)) #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) @@ -8320,19 +8320,19 @@ enum { #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \ SDE_DDI_HOTPLUG_ICP(PORT_A)) -#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC1)) +#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC1)) #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \ SDE_DDI_HOTPLUG_ICP(PORT_B) | \ SDE_DDI_HOTPLUG_ICP(PORT_A)) -#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC5) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ - SDE_TC_HOTPLUG_ICP(PORT_TC1)) +#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \ + SDE_TC_HOTPLUG_ICP(TC_PORT_TC1)) #define SDEISR _MMIO(0xc4000) #define SDEIMR _MMIO(0xc4004) @@ -8417,15 +8417,15 @@ enum { #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) -#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \ - ICP_TC_HPD_ENABLE(PORT_TC3) | \ - ICP_TC_HPD_ENABLE(PORT_TC2) | \ - ICP_TC_HPD_ENABLE(PORT_TC1)) +#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \ + ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \ + ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \ + ICP_TC_HPD_ENABLE(TC_PORT_TC1)) #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) -#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ - ICP_TC_HPD_ENABLE(PORT_TC5) | \ +#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \ + ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \ ICP_TC_HPD_ENABLE_MASK) #define _PCH_DPLL_A 0xc6014 @@ -10283,9 +10283,9 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_TC4 ? \ (tc_port) + 12 : \ - (tc_port) - PORT_TC4 + 21)) + (tc_port) - TC_PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) From patchwork Tue Oct 6 14:33:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818739 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 455B0112E for ; Tue, 6 Oct 2020 14:34:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05D52204EF for ; Tue, 6 Oct 2020 14:34:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05D52204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E98F26E487; Tue, 6 Oct 2020 14:34:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BD5E6E487 for ; Tue, 6 Oct 2020 14:34:06 +0000 (UTC) IronPort-SDR: uv6TMAnJdcW1I5U50C3eqdiza7vN5IK4HOUyu/Ea19ujhqvtOssraAA7uYptwj609h+QTyg5/P U8VR/mkcjypg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="249221202" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="249221202" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:00 -0700 IronPort-SDR: 3JgZU0wBLwSyMsnndI16V2EV1hPtBY3MKgxeG098qXTQsjNtSctMfwfDDaOAIzL34rLrXMshj+ 7za9h++7Dl8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="315675099" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga006.jf.intel.com with SMTP; 06 Oct 2020 07:33:58 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:33:57 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:32 +0300 Message-Id: <20201006143349.5561-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/20] drm/i915: Add PORT_TCn aliases to enum port X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3... Add the appropriate enum values for the TC DDIs to enum port. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 10 +++---- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-- drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++ 4 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4716484af62d..179029c3d3d5 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1660,17 +1660,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, }; /* - * Bspec lists the ports as A, B, C, D - however internally in our - * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the - * registers in Display Engine match the right offsets. Apply the - * mapping here to translate from VBT to internal convention. + * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D + * map to DDI A,B,TC1,TC2 respectively. */ static const int rkl_port_mapping[][3] = { [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, [PORT_C] = { -1 }, - [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, - [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, }; if (IS_ROCKETLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 6f7bd67732f2..d1e4cb04e90d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5075,8 +5075,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) { - if (port >= PORT_D) - return HPD_PORT_TC1 + port - PORT_D; + if (port >= PORT_TC1) + return HPD_PORT_TC1 + port - PORT_TC1; else return HPD_PORT_A + port - PORT_A; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 32d24c60ff96..e073b862b282 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7356,12 +7356,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if (IS_ROCKETLAKE(i915) && port >= PORT_D) - return (enum phy)port - 1; + if (IS_ROCKETLAKE(i915) && port >= PORT_TC1) + return PHY_C + port - PORT_TC1; else if (IS_ELKHARTLAKE(i915) && port == PORT_D) return PHY_A; - return (enum phy)port; + return PHY_A + port - PORT_A; } enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) @@ -7370,9 +7370,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) return TC_PORT_NONE; if (INTEL_GEN(dev_priv) >= 12) - return port - PORT_D; - - return port - PORT_C; + return TC_PORT_TC1 + port - PORT_TC1; + else + return TC_PORT_TC1 + port - PORT_C; } enum intel_display_power_domain intel_port_to_power_domain(enum port port) @@ -17104,17 +17104,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (IS_ROCKETLAKE(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + intel_ddi_init(dev_priv, PORT_TC1); + intel_ddi_init(dev_priv, PORT_TC2); } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); - intel_ddi_init(dev_priv, PORT_E); - intel_ddi_init(dev_priv, PORT_F); - intel_ddi_init(dev_priv, PORT_G); - intel_ddi_init(dev_priv, PORT_H); - intel_ddi_init(dev_priv, PORT_I); + intel_ddi_init(dev_priv, PORT_TC1); + intel_ddi_init(dev_priv, PORT_TC2); + intel_ddi_init(dev_priv, PORT_TC2); + intel_ddi_init(dev_priv, PORT_TC4); + intel_ddi_init(dev_priv, PORT_TC5); + intel_ddi_init(dev_priv, PORT_TC6); icl_dsi_init(dev_priv); } else if (IS_ELKHARTLAKE(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 8c93253cbd95..a39be3c9e0cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -207,6 +207,14 @@ enum port { PORT_H, PORT_I, + /* tgl+ */ + PORT_TC1 = PORT_D, + PORT_TC2, + PORT_TC3, + PORT_TC4, + PORT_TC5, + PORT_TC6, + I915_MAX_PORTS }; From patchwork Tue Oct 6 14:33:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FD20139A for ; Tue, 6 Oct 2020 14:34:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 088382065C for ; Tue, 6 Oct 2020 14:34:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 088382065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E47898FD; Tue, 6 Oct 2020 14:34:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id EACA46E4A5 for ; Tue, 6 Oct 2020 14:34:23 +0000 (UTC) IronPort-SDR: r+LH/0XNcMRMbC82Q0jZvGtFrk+d8bJ8bXWZKR/QcFq3XRjCeFmW1ggk7ee6nll2Fy/TYEcXob 6YjpJYv9bdqA== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="163745206" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="163745206" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:05 -0700 IronPort-SDR: I6hvJuogsvGwldg9HklVVLWpzsflXtX7KPS18dchP/MF5t829je8Fua9OmivghAAdWNKA014bI /QgCAwmkFbhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="353504923" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 06 Oct 2020 07:34:01 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:00 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:33 +0300 Message-Id: <20201006143349.5561-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/20] drm/i915: Give DDI encoders even better names X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's pimp the DDI encoder->name to reflect what the spec calls them. Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6. Also since each encoder is really a combination of the DDI and the PHY we include the PHY name as well. ICL is a bit special since it already has the two different types of DDIs (combo or TC) but it still calls them just DDI A-F regarless of the type. For that let's add an extra "(TC)" note to remind is which type of DDI it really is. The code is darn ugly, but not sure there's much we can do about it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d1e4cb04e90d..5a30bc6a6c49 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5171,8 +5171,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder = &dig_port->base; - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, - DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); + if (INTEL_GEN(dev_priv) >= 12) { + enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + DRM_MODE_ENCODER_TMDS, + "DDI %s%c/PHY %s%c", + port >= PORT_TC1 ? "TC" : "", + port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1', + tc_port != TC_PORT_NONE ? "TC" : "", + tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1'); + } else if (INTEL_GEN(dev_priv) >= 11) { + enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + DRM_MODE_ENCODER_TMDS, + "DDI %c%s/PHY %s%c", + port_name(port), + port >= PORT_C ? " (TC)" : "", + tc_port != TC_PORT_NONE ? "TC" : "", + tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_TC1 + '1'); + } else { + drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + DRM_MODE_ENCODER_TMDS, + "DDI %c/PHY %c", port_name(port), phy_name(phy)); + } mutex_init(&dig_port->hdcp_mutex); dig_port->num_hdcp_streams = 0; From patchwork Tue Oct 6 14:33:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94B1D112E for ; Tue, 6 Oct 2020 14:34:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D3E7204EF for ; Tue, 6 Oct 2020 14:34:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D3E7204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C65FF6E4A5; Tue, 6 Oct 2020 14:34:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24BF36E4A6 for ; Tue, 6 Oct 2020 14:34:24 +0000 (UTC) IronPort-SDR: PnLDW0XI41fHqKjuDNn1OpN6vM3I+PtajvFbvpWACYctrG7P2uJ0+tJUq1g51181Pkl1inM7WF yoOfKuIHpgWg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="163745210" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="163745210" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:05 -0700 IronPort-SDR: 5Dr5rSv56lzIps19t/RS0BzuIxpJ3HPngiM69eJiYH3nFlSSUbeoNAct+3URl8sUVFbaZOMwdi GxnTOM9A6T3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="354397085" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 06 Oct 2020 07:34:04 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:03 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:34 +0300 Message-Id: <20201006143349.5561-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Just like with the DDIs tgl+ renamed the AUX CHs to reflect the type of the DDI. Let's add the aliasing enum values for the type-C AUX CHs. Signed-off-by: Ville Syrjälä Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.h | 8 +++ drivers/gpu/drm/i915/display/intel_dp.c | 53 ++++++++++++++++++-- 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index a39be3c9e0cf..cba876721ea0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -290,6 +290,14 @@ enum aux_ch { AUX_CH_G, AUX_CH_H, AUX_CH_I, + + /* tgl+ */ + AUX_CH_USBC1 = AUX_CH_D, + AUX_CH_USBC2, + AUX_CH_USBC3, + AUX_CH_USBC4, + AUX_CH_USBC5, + AUX_CH_USBC6, }; #define aux_ch_name(a) ((a) + 'A') diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 239016dcd544..a73c354c920e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) case AUX_CH_D: case AUX_CH_E: case AUX_CH_F: - case AUX_CH_G: return DP_AUX_CH_CTL(aux_ch); default: MISSING_CASE(aux_ch); @@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) case AUX_CH_D: case AUX_CH_E: case AUX_CH_F: - case AUX_CH_G: + return DP_AUX_CH_DATA(aux_ch, index); + default: + MISSING_CASE(aux_ch); + return DP_AUX_CH_DATA(AUX_CH_A, index); + } +} + +static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_C: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + case AUX_CH_USBC5: + case AUX_CH_USBC6: + return DP_AUX_CH_CTL(aux_ch); + default: + MISSING_CASE(aux_ch); + return DP_AUX_CH_CTL(AUX_CH_A); + } +} + +static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_C: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + case AUX_CH_USBC5: + case AUX_CH_USBC6: return DP_AUX_CH_DATA(aux_ch, index); default: MISSING_CASE(aux_ch); @@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 12) { + intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; + intel_dp->aux_ch_data_reg = tgl_aux_data_reg; + } else if (INTEL_GEN(dev_priv) >= 9) { intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; intel_dp->aux_ch_data_reg = skl_aux_data_reg; } else if (HAS_PCH_SPLIT(dev_priv)) { From patchwork Tue Oct 6 14:33:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818763 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71EF4112E for ; Tue, 6 Oct 2020 14:34:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 549CD2065C for ; Tue, 6 Oct 2020 14:34:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 549CD2065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF2CA6E4AE; Tue, 6 Oct 2020 14:34:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E27D6E4AE for ; Tue, 6 Oct 2020 14:34:34 +0000 (UTC) IronPort-SDR: Pno6shvezU/wo7q17fDsrLzMWDzuqyZL46ERwYNEDP6C3jNygzUyJky5kJjeLyTsycBoTwLhLs e27P1nUC+2kw== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="226113627" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="226113627" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:10 -0700 IronPort-SDR: lj6IP9gODoaWPdKFNYdNAPz8W++ZcNmrdG9uC0mxYgVt8/E2eNjnRhFdcJDjNeY9+1aghrqZwu KMfs45l+rUww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="327579252" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 06 Oct 2020 07:34:06 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:35 +0300 Message-Id: <20201006143349.5561-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/20] drm/i915: Pimp AUX CH names X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's make the AUX CH names match the spec (AUX A-F for pre-tgl, AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include the full encoder name in the AUX CH name as well (as opposed to just using port_name() which wouldn't give us the right thing on tgl+). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a73c354c920e..299dc444a777 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1877,6 +1877,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; + enum aux_ch aux_ch = dig_port->aux_ch; if (INTEL_GEN(dev_priv) >= 12) { intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; @@ -1909,9 +1910,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp) drm_dp_aux_init(&intel_dp->aux); /* Failure to allocate our preferred name is not critical */ - intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c", - aux_ch_name(dig_port->aux_ch), - port_name(encoder->port)); + if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", + aux_ch - AUX_CH_USBC1 + '1', + encoder->base.name); + else + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", + aux_ch_name(aux_ch), + encoder->base.name); + intel_dp->aux.transfer = intel_dp_aux_transfer; } From patchwork Tue Oct 6 14:33:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 793F5112E for ; Tue, 6 Oct 2020 14:34:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56910204EF for ; Tue, 6 Oct 2020 14:34:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 56910204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7D3D89950; Tue, 6 Oct 2020 14:34:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A2D6898FD for ; Tue, 6 Oct 2020 14:34:23 +0000 (UTC) IronPort-SDR: ZEbhWrrarm1m7xDYSAe1SPQMmYsDOCS4Pk08vpVeEk2xWLKL8Wc8mQ9bIdMPI6pX2tV/qBU0u1 547NIS3ZsqFw== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="164585443" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="164585443" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:15 -0700 IronPort-SDR: E5kytR/42ApQtqoohr8D1LpCtyEEsrqHKgBZrd02NGet62yC2MpCmwxlKr1ySdcHX7vvLgwxgb pa+xoWtX+QHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="296983685" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 06 Oct 2020 07:34:09 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:36 +0300 Message-Id: <20201006143349.5561-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/20] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä As with the VBT DVO port, RKL uses PHY based mapping for the VBT AUX CH. Adjust the code to use the new AUX_USBCn names and add a comment to explain the situation. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 179029c3d3d5..77c86f51c36d 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2636,10 +2636,14 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, aux_ch = AUX_CH_B; break; case DP_AUX_C: - aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C; + /* + * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D + * map to DDI A,B,TC1,TC2 respectively. + */ + aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC1 : AUX_CH_C; break; case DP_AUX_D: - aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D; + aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_USBC2 : AUX_CH_D; break; case DP_AUX_E: aux_ch = AUX_CH_E; From patchwork Tue Oct 6 14:33:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20387112E for ; Tue, 6 Oct 2020 14:34:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01A6C204EF for ; Tue, 6 Oct 2020 14:34:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 01A6C204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E4626E4A7; Tue, 6 Oct 2020 14:34:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9992E6E4A7 for ; Tue, 6 Oct 2020 14:34:26 +0000 (UTC) IronPort-SDR: 4VgG/NcjIyH3KrqaavSOfbZedxj1HtgyiBxZih5OaDta/8fBmZnB3oGEkciiEYmA6SADhKew42 KQP/is6Jj/aA== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161897377" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161897377" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:17 -0700 IronPort-SDR: kAHfJmOSN511DqDDo5KkDPDTZA9/pwkkx2lgynifsxCrvLFxhk6GBi92TYx5aWgJRDDZ5Pwu2c GJIXZw4H7F7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="348503596" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 06 Oct 2020 07:34:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:11 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:37 +0300 Message-Id: <20201006143349.5561-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/20] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear these have nothing to do with DDI ports or PHYs as such. The only thing that matters is the HPD pin assignment. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------ drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d9438194c2f0..9b92b95f7a6f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { }; static const u32 hpd_bxt[HPD_NUM_PINS] = { - [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, - [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, - [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC, + [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A), + [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B), + [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C), }; static const u32 hpd_gen11[HPD_NUM_PINS] = { @@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, * For BXT invert bit has to be set based on AOB design * for HPD detection logic, update it based on VBT fields. */ - if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) hotplug |= BXT_DDIA_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) hotplug |= BXT_DDIB_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && + if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) hotplug |= BXT_DDIC_HPD_INVERT; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e378d9b21c5..72f93ec38aea 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7786,6 +7786,8 @@ enum { (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ GEN11_PIPE_PLANE5_FAULT) +#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) + #define GEN8_DE_PORT_ISR _MMIO(0x44440) #define GEN8_DE_PORT_IMR _MMIO(0x44444) #define GEN8_DE_PORT_IIR _MMIO(0x44448) @@ -7799,12 +7801,10 @@ enum { #define GEN9_AUX_CHANNEL_B (1 << 25) #define DSI1_TE (1 << 24) #define DSI0_TE (1 << 23) -#define BXT_DE_PORT_HP_DDIC (1 << 5) -#define BXT_DE_PORT_HP_DDIB (1 << 4) -#define BXT_DE_PORT_HP_DDIA (1 << 3) -#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ - BXT_DE_PORT_HP_DDIB | \ - BXT_DE_PORT_HP_DDIC) +#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) +#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \ + BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \ + BXT_DE_PORT_HP_DDI(HPD_PORT_C)) #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) #define BXT_DE_PORT_GMBUS (1 << 1) #define GEN8_AUX_CHANNEL_A (1 << 0) From patchwork Tue Oct 6 14:33:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 546B7139A for ; Tue, 6 Oct 2020 14:34:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 354C8204EF for ; Tue, 6 Oct 2020 14:34:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 354C8204EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DA376E49D; Tue, 6 Oct 2020 14:34:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E8ACB6E49D for ; Tue, 6 Oct 2020 14:34:26 +0000 (UTC) IronPort-SDR: 6lQeAh9cB2ucZN6cpHESYIlf7EhuXNUTLDkGjTdF4L9CdqsX8I3kT9aXvEfBOjQUewoddezmf1 UHnrnFC1bOng== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="164655834" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="164655834" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:20 -0700 IronPort-SDR: 9XEZvkNhqe7+rlnb5OCjgo4QkmUXbiPJS8ZuVE3IgvHnvK3xWB8u6iC+ODWmwv2DPWtGqSacfZ IKXX1P9klYOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="387898649" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 06 Oct 2020 07:34:15 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:14 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:38 +0300 Message-Id: <20201006143349.5561-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/20] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Unify the BDW/BXT hotplug bits. BDW only has port A, but that matches BXT port A so we can shar the same macro for both. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++--------- drivers/gpu/drm/i915/i915_reg.h | 10 +++++----- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9b92b95f7a6f..6b824db1424a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = { }; static const u32 hpd_bdw[HPD_NUM_PINS] = { - [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, + [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), }; static const u32 hpd_ibx[HPD_NUM_PINS] = { @@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { }; static const u32 hpd_bxt[HPD_NUM_PINS] = { - [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A), - [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B), - [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C), + [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), + [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), + [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), }; static const u32 hpd_gen11[HPD_NUM_PINS] = { @@ -2367,7 +2367,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } } else if (IS_BROADWELL(dev_priv)) { - tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; + tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK; if (tmp_mask) { ilk_hpd_irq_handler(dev_priv, tmp_mask); found = true; @@ -3391,13 +3391,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, * For BXT invert bit has to be set based on AOB design * for HPD detection logic, update it based on VBT fields. */ - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) hotplug |= BXT_DDIA_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) hotplug |= BXT_DDIB_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) hotplug |= BXT_DDIC_HPD_INVERT; @@ -3574,7 +3574,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; else if (IS_BROADWELL(dev_priv)) - de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; + de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; if (INTEL_GEN(dev_priv) >= 12) { enum transcoder trans; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 72f93ec38aea..969266e59f56 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7801,11 +7801,11 @@ enum { #define GEN9_AUX_CHANNEL_B (1 << 25) #define DSI1_TE (1 << 24) #define DSI0_TE (1 << 23) -#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) -#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \ - BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \ - BXT_DE_PORT_HP_DDI(HPD_PORT_C)) -#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) +#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) +#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) +#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) #define BXT_DE_PORT_GMBUS (1 << 1) #define GEN8_AUX_CHANNEL_A (1 << 0) #define TGL_DE_PORT_AUX_USBC6 (1 << 13) From patchwork Tue Oct 6 14:33:39 2020 Content-Type: text/plain; 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06 Oct 2020 07:34:18 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:17 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:39 +0300 Message-Id: <20201006143349.5561-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/20] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use hpd_pin instead of port in the parametrized ICP+ DDI HPD macros. Makes it clear what these refer to. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------ drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++++++----------------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6b824db1424a..b64f83f3d686 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { }; static const u32 hpd_icp[HPD_NUM_PINS] = { - [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), - [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), - [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C), + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), + [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1), [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2), [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3), @@ -1069,11 +1069,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { case HPD_PORT_A: - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A); case HPD_PORT_B: - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B); case HPD_PORT_C: - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C); default: return false; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 969266e59f56..206e8ab64bd4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8317,16 +8317,16 @@ enum { /* south display engine interrupt: ICP/TGP */ #define SDE_GMBUS_ICP (1 << 23) #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) -#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) -#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \ - SDE_DDI_HOTPLUG_ICP(PORT_A)) +#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) +#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) #define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_TC1)) -#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \ - SDE_DDI_HOTPLUG_ICP(PORT_B) | \ - SDE_DDI_HOTPLUG_ICP(PORT_A)) +#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) #define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ @@ -8400,12 +8400,12 @@ enum { */ #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) -#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port))) -#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port))) -#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port))) -#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port))) -#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port))) -#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port))) +#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) #define SHOTPLUG_CTL_TC _MMIO(0xc4034) #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) @@ -8415,15 +8415,15 @@ enum { #define SHPD_FILTER_CNT _MMIO(0xc4038) #define SHPD_FILTER_CNT_500_ADJ 0x001D9 -#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) +#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \ ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \ ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \ ICP_TC_HPD_ENABLE(TC_PORT_TC1)) -#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) +#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \ ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \ ICP_TC_HPD_ENABLE_MASK) From patchwork Tue Oct 6 14:33:40 2020 Content-Type: text/plain; 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Tue, 6 Oct 2020 14:34:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4DBB96E4B3 for ; Tue, 6 Oct 2020 14:34:51 +0000 (UTC) IronPort-SDR: Fv6DafZHtkgUbO8Gm+S5T0REvRV5yvt2mndL9cwd7Ul5xcVseoBwKf+1zm9592UuB3/9QqC8Nt T7ZcRjhBHbdQ== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161123495" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161123495" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:22 -0700 IronPort-SDR: WVTmzwcWCnDMWpd+jLH48hT6+dQZETvIusQwQdDb29GIj1SvIQ5FYFT5bcW0OVeLuQmkYPjZlt IlRYii670q2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="418217087" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 06 Oct 2020 07:34:21 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:20 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:40 +0300 Message-Id: <20201006143349.5561-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/20] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG() to make it clear what they refer to. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++----------------- drivers/gpu/drm/i915/i915_reg.h | 37 ++++++++++++------------- 2 files changed, 43 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b64f83f3d686..ac82ed3873db 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { }; static const u32 hpd_gen11[HPD_NUM_PINS] = { - [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_TC1) | GEN11_TBT_HOTPLUG(TC_PORT_TC1), - [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_TC2) | GEN11_TBT_HOTPLUG(TC_PORT_TC2), - [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_TC3) | GEN11_TBT_HOTPLUG(TC_PORT_TC3), - [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_TC4) | GEN11_TBT_HOTPLUG(TC_PORT_TC4), - [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_TC5) | GEN11_TBT_HOTPLUG(TC_PORT_TC5), - [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_TC6) | GEN11_TBT_HOTPLUG(TC_PORT_TC6), + [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), + [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), + [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), + [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), + [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), + [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), }; static const u32 hpd_icp[HPD_NUM_PINS] = { @@ -1035,17 +1035,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { case HPD_PORT_TC1: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC1); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1); case HPD_PORT_TC2: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC2); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2); case HPD_PORT_TC3: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC3); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3); case HPD_PORT_TC4: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC4); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4); case HPD_PORT_TC5: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC5); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5); case HPD_PORT_TC6: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_TC6); + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6); default: return false; } @@ -3257,21 +3257,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) u32 hotplug; hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6); + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_TC6); + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6); I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 206e8ab64bd4..ab4b31cb50f2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7787,6 +7787,7 @@ enum { GEN11_PIPE_PLANE5_FAULT) #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) +#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) #define GEN8_DE_PORT_ISR _MMIO(0x44440) #define GEN8_DE_PORT_IMR _MMIO(0x44444) @@ -7864,27 +7865,27 @@ enum { #define GEN11_DE_HPD_IMR _MMIO(0x44474) #define GEN11_DE_HPD_IIR _MMIO(0x44478) #define GEN11_DE_HPD_IER _MMIO(0x4447c) -#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) -#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_TC6) | \ - GEN11_TC_HOTPLUG(TC_PORT_TC5) | \ - GEN11_TC_HOTPLUG(TC_PORT_TC4) | \ - GEN11_TC_HOTPLUG(TC_PORT_TC3) | \ - GEN11_TC_HOTPLUG(TC_PORT_TC2) | \ - GEN11_TC_HOTPLUG(TC_PORT_TC1)) -#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) -#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_TC6) | \ - GEN11_TBT_HOTPLUG(TC_PORT_TC5) | \ - GEN11_TBT_HOTPLUG(TC_PORT_TC4) | \ - GEN11_TBT_HOTPLUG(TC_PORT_TC3) | \ - GEN11_TBT_HOTPLUG(TC_PORT_TC2) | \ - GEN11_TBT_HOTPLUG(TC_PORT_TC1)) +#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC1)) +#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) -#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) -#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) -#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) -#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) +#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) #define GEN11_GT_INTR_DW0 _MMIO(0x190018) #define GEN11_CSME (31) From patchwork Tue Oct 6 14:33:41 2020 Content-Type: text/plain; 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Tue, 6 Oct 2020 14:34:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADEF26E49D for ; Tue, 6 Oct 2020 14:34:27 +0000 (UTC) IronPort-SDR: pkMQSpz57DoAZFcy9XLvXV5eSPgu79PnoQPjVeG2X2XFG2fgwk98tJGV9/4OMNDT7PkmnCDqQL Seczh59jp7iw== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161897486" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161897486" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:25 -0700 IronPort-SDR: BVrcHnfjJZKlwe6xv4+MkvvE/4uU64QBCxItIEGN5kB21oexte+xvh1AWxJdKpIdr4UGjzgmVV PBPpZ92Cfa5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="297135808" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga008.fm.intel.com with SMTP; 06 Oct 2020 07:34:23 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:23 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:41 +0300 Message-Id: <20201006143349.5561-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/20] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Parametrize the icp+ TC HPD bits using hpd_pin rather than tc_port so it's clear what kind of an animal we're dealing with. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++------------- drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++----------------- 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ac82ed3873db..63322160e248 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = { [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), - [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC1), - [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC2), - [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC3), - [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC4), - [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC5), - [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_TC6), + [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), + [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), + [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), + [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), + [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), + [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), }; static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -1083,17 +1083,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { case HPD_PORT_TC1: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC1); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1); case HPD_PORT_TC2: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC2); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2); case HPD_PORT_TC3: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC3); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3); case HPD_PORT_TC4: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC4); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4); case HPD_PORT_TC5: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC5); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5); case HPD_PORT_TC6: - return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_TC6); + return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6); default: return false; } @@ -1872,7 +1872,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) tc_hotplug_trigger = 0; } else if (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; - tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_TC1); + tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1); } else { drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv), "Unrecognized PCH type 0x%x\n", @@ -3238,7 +3238,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) { icp_hpd_irq_setup(dev_priv, - ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_TC1)); + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1)); } /* @@ -3652,7 +3652,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); } else if (HAS_PCH_MCC(dev_priv)) { icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_TC1)); + icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1)); } else { icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab4b31cb50f2..b3ae002bf628 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8317,23 +8317,23 @@ enum { /* south display engine interrupt: ICP/TGP */ #define SDE_GMBUS_ICP (1 << 23) -#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) +#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) -#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC1)) +#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) -#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_TC6) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC5) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC4) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC3) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC2) | \ - SDE_TC_HOTPLUG_ICP(TC_PORT_TC1)) +#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) #define SDEISR _MMIO(0xc4000) #define SDEIMR _MMIO(0xc4004) @@ -8409,24 +8409,24 @@ enum { #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) #define SHOTPLUG_CTL_TC _MMIO(0xc4034) -#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) -#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) -#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) +#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) #define SHPD_FILTER_CNT _MMIO(0xc4038) #define SHPD_FILTER_CNT_500_ADJ 0x001D9 #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) -#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC4) | \ - ICP_TC_HPD_ENABLE(TC_PORT_TC3) | \ - ICP_TC_HPD_ENABLE(TC_PORT_TC2) | \ - ICP_TC_HPD_ENABLE(TC_PORT_TC1)) +#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \ + ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \ + ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \ + ICP_TC_HPD_ENABLE(HPD_PORT_TC1)) #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) -#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_TC6) | \ - ICP_TC_HPD_ENABLE(TC_PORT_TC5) | \ +#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \ + ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \ ICP_TC_HPD_ENABLE_MASK) #define _PCH_DPLL_A 0xc6014 From patchwork Tue Oct 6 14:33:42 2020 Content-Type: text/plain; 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06 Oct 2020 07:34:26 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:25 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:42 +0300 Message-Id: <20201006143349.5561-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/20] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of the file so we can use them in more places. No functional changes. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++++----------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 63322160e248..87ccc82bf21d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1196,6 +1196,31 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, } +static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, + const u32 hpd[HPD_NUM_PINS]) +{ + struct intel_encoder *encoder; + u32 enabled_irqs = 0; + + for_each_intel_encoder(&dev_priv->drm, encoder) + if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) + enabled_irqs |= hpd[encoder->hpd_pin]; + + return enabled_irqs; +} + +static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, + const u32 hpd[HPD_NUM_PINS]) +{ + struct intel_encoder *encoder; + u32 hotplug_irqs = 0; + + for_each_intel_encoder(&dev_priv->drm, encoder) + hotplug_irqs |= hpd[encoder->hpd_pin]; + + return hotplug_irqs; +} + static void gmbus_irq_handler(struct drm_i915_private *dev_priv) { wake_up_all(&dev_priv->gmbus_wait_queue); @@ -3131,31 +3156,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } -static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, - const u32 hpd[HPD_NUM_PINS]) -{ - struct intel_encoder *encoder; - u32 enabled_irqs = 0; - - for_each_intel_encoder(&dev_priv->drm, encoder) - if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) - enabled_irqs |= hpd[encoder->hpd_pin]; - - return enabled_irqs; -} - -static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, - const u32 hpd[HPD_NUM_PINS]) -{ - struct intel_encoder *encoder; - u32 hotplug_irqs = 0; - - for_each_intel_encoder(&dev_priv->drm, encoder) - hotplug_irqs |= hpd[encoder->hpd_pin]; - - return hotplug_irqs; -} - static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; From patchwork Tue Oct 6 14:33:43 2020 Content-Type: text/plain; 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06 Oct 2020 07:34:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:28 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:43 +0300 Message-Id: <20201006143349.5561-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/20] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä No reason to stuff both type-c and tbt into the same function. Let's split this so we may more easily handle platforms that lack the tbt spefific bits. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 87ccc82bf21d..0886369e3890 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3252,7 +3252,7 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) TGP_DDI_HPD_ENABLE_MASK, 0); } -static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) +static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -3264,6 +3264,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); +} + +static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) +{ + u32 hotplug; hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | @@ -3289,7 +3294,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) I915_WRITE(GEN11_DE_HPD_IMR, val); POSTING_READ(GEN11_DE_HPD_IMR); - gen11_hpd_detection_setup(dev_priv); + gen11_tc_hpd_detection_setup(dev_priv); + gen11_tbt_hpd_detection_setup(dev_priv); if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) icp_hpd_irq_setup(dev_priv, @@ -3612,7 +3618,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); - gen11_hpd_detection_setup(dev_priv); + gen11_tc_hpd_detection_setup(dev_priv); + gen11_tbt_hpd_detection_setup(dev_priv); } else if (IS_GEN9_LP(dev_priv)) { bxt_hpd_detection_setup(dev_priv); } else if (IS_BROADWELL(dev_priv)) { From patchwork Tue Oct 6 14:33:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818775 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BDC6139A for ; Tue, 6 Oct 2020 14:34:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 634052065C for ; Tue, 6 Oct 2020 14:34:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 634052065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD3286E4B3; Tue, 6 Oct 2020 14:34:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2438389864 for ; Tue, 6 Oct 2020 14:34:53 +0000 (UTC) IronPort-SDR: UCxYmQiXtZYwNyzVM6tJ8SMKJWo6rZD5Y3k/vdfwuecJieEQWPAx2bj9kF1QqJuq3MP2qb+0Lw tFlNlHNHF0mg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="226113794" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="226113794" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:34 -0700 IronPort-SDR: a0eChOtoku93PXSDYmhZOAMqg+y1+4re7QlyZGncUU3HLmWm88viiNRUfeAfz3JrWgnIAjYhcV +1DJnBRRTBgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="354397191" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 06 Oct 2020 07:34:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:44 +0300 Message-Id: <20201006143349.5561-16-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/20] drm/i915: Don't enable hpd detection logic from irq_postinstall() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä No reason that I can see why we should enable the hpd detection logic already during irq postinstall phase. We don't even do this on all the platforms. We just need it before we actually enable the hotplug interrupts in .hpd_irq_setup(), and in fact we already do it there as well. Let's just eliminate the redundant early setup. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 38 +++------------------------------ 1 file changed, 3 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0886369e3890..b1c56a29376c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3378,8 +3378,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) ibx_hpd_irq_setup(dev_priv); } -static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, - u32 enabled_irqs) +static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, + u32 enabled_irqs) { u32 hotplug; @@ -3410,11 +3410,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, I915_WRITE(PCH_PORT_HOTPLUG, hotplug); } -static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) -{ - __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); -} - static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; @@ -3424,7 +3419,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); - __bxt_hpd_detection_setup(dev_priv, enabled_irqs); + bxt_hpd_detection_setup(dev_priv, enabled_irqs); } static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3443,12 +3438,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); - - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || - HAS_PCH_LPT(dev_priv)) - ibx_hpd_detection_setup(dev_priv); - else - spt_hpd_detection_setup(dev_priv); } static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3485,8 +3474,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) gen5_gt_irq_postinstall(&dev_priv->gt); - ilk_hpd_detection_setup(dev_priv); - ibx_irq_postinstall(dev_priv); if (IS_IRONLAKE_M(dev_priv)) { @@ -3618,12 +3605,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); - gen11_tc_hpd_detection_setup(dev_priv); - gen11_tbt_hpd_detection_setup(dev_priv); - } else if (IS_GEN9_LP(dev_priv)) { - bxt_hpd_detection_setup(dev_priv); - } else if (IS_BROADWELL(dev_priv)) { - ilk_hpd_detection_setup(dev_priv); } } @@ -3651,19 +3632,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); - - if (HAS_PCH_TGP(dev_priv)) { - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); - icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK); - } else if (HAS_PCH_JSP(dev_priv)) { - icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); - } else if (HAS_PCH_MCC(dev_priv)) { - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1)); - } else { - icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); - icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK); - } } static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) From patchwork Tue Oct 6 14:33:45 2020 Content-Type: text/plain; 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Tue, 6 Oct 2020 14:34:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C051C6E4B3 for ; Tue, 6 Oct 2020 14:34:52 +0000 (UTC) IronPort-SDR: Xyk53pDrMA5R8efEIBV1NwYRP4NPmFct9XLliD19cBtyPyKEtJMExC5fPHL61V+KSC3FS4pDcY KOqeAqhp2yCg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="143907604" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="143907604" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:37 -0700 IronPort-SDR: 3wtYRwmt6ZHkTlgj9mZpoblklJe+u8mKQb+GvpLmOx+O/unkr4fKSyu95yehUiseqkh5qSNp8X gwXRrNWkJHxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="327579445" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 06 Oct 2020 07:34:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:45 +0300 Message-Id: <20201006143349.5561-17-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/20] drm/i915: Rename 'tmp_mask' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace this silly tmp_mask with hotplug_trigger/te_trigger where appropriate. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b1c56a29376c..1fa880272d88 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2374,7 +2374,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (master_ctl & GEN8_DE_PORT_IRQ) { iir = I915_READ(GEN8_DE_PORT_IIR); if (iir) { - u32 tmp_mask; bool found = false; I915_WRITE(GEN8_DE_PORT_IIR, iir); @@ -2386,15 +2385,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } if (IS_GEN9_LP(dev_priv)) { - tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; - if (tmp_mask) { - bxt_hpd_irq_handler(dev_priv, tmp_mask); + u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; + + if (hotplug_trigger) { + bxt_hpd_irq_handler(dev_priv, hotplug_trigger); found = true; } } else if (IS_BROADWELL(dev_priv)) { - tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK; - if (tmp_mask) { - ilk_hpd_irq_handler(dev_priv, tmp_mask); + u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; + + if (hotplug_trigger) { + ilk_hpd_irq_handler(dev_priv, hotplug_trigger); found = true; } } @@ -2405,9 +2406,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } if (INTEL_GEN(dev_priv) >= 11) { - tmp_mask = iir & (DSI0_TE | DSI1_TE); - if (tmp_mask) { - gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask); + u32 te_trigger = iir & (DSI0_TE | DSI1_TE); + + if (te_trigger) { + gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); found = true; } } From patchwork Tue Oct 6 14:33:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818765 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13436139A for ; Tue, 6 Oct 2020 14:34:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFF892065C for ; Tue, 6 Oct 2020 14:34:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFF892065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6578589A44; Tue, 6 Oct 2020 14:34:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76DE189A44 for ; Tue, 6 Oct 2020 14:34:41 +0000 (UTC) IronPort-SDR: /gOhg35HpSkCzlYEvk8AYDThP4xTP0B3hag8ZcHOy0pZFdFWqCQqAUhsZSl18yoHFv1qrziHbX 15HaaeJYA1bQ== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161897641" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161897641" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:41 -0700 IronPort-SDR: 6663seuuIK4BZyGfHvTA8va//JME8kUPuF6ua+MGkI03eFZlCBDFEqeMhI/iaYC+vQ47AY3Vlq LPIUFTZ2ypPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="296983874" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 06 Oct 2020 07:34:37 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:46 +0300 Message-Id: <20201006143349.5561-18-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/20] drm/i915: Remove the per-plaform IIR HPD masking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We no longer unmask all HPD irqs, so we can drop the ugly per-platform HPD IIR masking. IMR will prevent unsupported bits from appearing in IIR. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 21 ++------------------- drivers/gpu/drm/i915/i915_reg.h | 10 ++-------- 2 files changed, 4 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1fa880272d88..dd6a8d2690f6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1886,27 +1886,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) { - u32 ddi_hotplug_trigger, tc_hotplug_trigger; + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; u32 pin_mask = 0, long_mask = 0; - if (HAS_PCH_TGP(dev_priv)) { - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; - tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; - } else if (HAS_PCH_JSP(dev_priv)) { - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; - tc_hotplug_trigger = 0; - } else if (HAS_PCH_MCC(dev_priv)) { - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; - tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1); - } else { - drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv), - "Unrecognized PCH type 0x%x\n", - INTEL_PCH_TYPE(dev_priv)); - - ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; - tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; - } - if (ddi_hotplug_trigger) { u32 dig_hotplug_reg; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b3ae002bf628..d2175faf7d34 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8319,16 +8319,10 @@ enum { #define SDE_GMBUS_ICP (1 << 23) #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) -#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ - SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) -#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ - SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ - SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ - SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) -#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ +#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) -#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ +#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ From patchwork Tue Oct 6 14:33:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 01ADC139A for ; Tue, 6 Oct 2020 14:35:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D24282065C for ; Tue, 6 Oct 2020 14:35:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D24282065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B5776E4B7; Tue, 6 Oct 2020 14:35:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 23FE96E4B7 for ; Tue, 6 Oct 2020 14:35:04 +0000 (UTC) IronPort-SDR: yn97CBFg/vTj9o4Dmsm7XtXTMRXjASttLTBWAZAzuaMPAYOaKIdCrzNqvc6IrKXsx4q+pGm9N4 5gWh7KTJhWpQ== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="161123647" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="161123647" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:43 -0700 IronPort-SDR: vr4t8o7U6NnKm1Kh+i1qflpjgx5zNmhQVKL1SAylTE8Vx/6v41Te6VC6QNCEDmK6dWQYIBEo4s 6/+y3sWi+QFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="348503720" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 06 Oct 2020 07:34:41 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:40 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:47 +0300 Message-Id: <20201006143349.5561-19-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 18/20] drm/i915: Enable hpd logic only for ports that are present X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's enable the hardware hpd logic only for the ports we can actually use. In theory this may save some miniscule amounts of power, and more importantly it eliminates a lot if platform specific codepaths since the generic thing can now deal with any combination of ports being present on each SKU. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 301 ++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_reg.h | 13 -- 2 files changed, 205 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index dd6a8d2690f6..222d2e6d7ee4 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -61,6 +61,8 @@ */ typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); +typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915, + enum hpd_pin pin); static const u32 hpd_ilk[HPD_NUM_PINS] = { [HPD_PORT_A] = DE_DP_A_HOTPLUG, @@ -1221,6 +1223,18 @@ static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, return hotplug_irqs; } +static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, + hotplug_enables_func hotplug_enables) +{ + struct intel_encoder *encoder; + u32 hotplug = 0; + + for_each_intel_encoder(&i915->drm, encoder) + hotplug |= hotplug_enables(i915, encoder->hpd_pin); + + return hotplug; +} + static void gmbus_irq_handler(struct drm_i915_private *dev_priv) { wake_up_all(&dev_priv->gmbus_wait_queue); @@ -3141,6 +3155,31 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } +static u32 ibx_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_A: + /* + * When CPU and PCH are on the same package, port A + * HPD must be enabled in both north and south. + */ + return HAS_PCH_LPT_LP(i915) ? + PORTA_HOTPLUG_ENABLE : 0; + case HPD_PORT_B: + return PORTB_HOTPLUG_ENABLE | + PORTB_PULSE_DURATION_2ms; + case HPD_PORT_C: + return PORTC_HOTPLUG_ENABLE | + PORTC_PULSE_DURATION_2ms; + case HPD_PORT_D: + return PORTD_HOTPLUG_ENABLE | + PORTD_PULSE_DURATION_2ms; + default: + return 0; + } +} + static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -3151,18 +3190,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) * The pulse duration bits are reserved on LPT+. */ hotplug = I915_READ(PCH_PORT_HOTPLUG); - hotplug &= ~(PORTB_PULSE_DURATION_MASK | + hotplug &= ~(PORTA_HOTPLUG_ENABLE | + PORTB_HOTPLUG_ENABLE | + PORTC_HOTPLUG_ENABLE | + PORTD_HOTPLUG_ENABLE | + PORTB_PULSE_DURATION_MASK | PORTC_PULSE_DURATION_MASK | PORTD_PULSE_DURATION_MASK); - hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; - hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; - hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; - /* - * When CPU and PCH are on the same package, port A - * HPD must be enabled in both north and south. - */ - if (HAS_PCH_LPT_LP(dev_priv)) - hotplug |= PORTA_HOTPLUG_ENABLE; + hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables); I915_WRITE(PCH_PORT_HOTPLUG, hotplug); } @@ -3178,28 +3213,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) ibx_hpd_detection_setup(dev_priv); } -static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv, - u32 enable_mask) +static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_A: + case HPD_PORT_B: + case HPD_PORT_C: + return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin); + default: + return 0; + } +} + +static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_TC1: + case HPD_PORT_TC2: + case HPD_PORT_TC3: + case HPD_PORT_TC4: + case HPD_PORT_TC5: + case HPD_PORT_TC6: + return ICP_TC_HPD_ENABLE(pin); + default: + return 0; + } +} + +static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; hotplug = I915_READ(SHOTPLUG_CTL_DDI); - hotplug |= enable_mask; + hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) | + SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | + SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C)); + hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables); I915_WRITE(SHOTPLUG_CTL_DDI, hotplug); } -static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv, - u32 enable_mask) +static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; hotplug = I915_READ(SHOTPLUG_CTL_TC); - hotplug |= enable_mask; + hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) | + ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | + ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | + ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | + ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | + ICP_TC_HPD_ENABLE(HPD_PORT_TC6)); + hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables); I915_WRITE(SHOTPLUG_CTL_TC, hotplug); } -static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, - u32 ddi_enable_mask, u32 tc_enable_mask) +static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; @@ -3211,30 +3281,24 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); - icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask); - if (tc_enable_mask) - icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask); + icp_ddi_hpd_detection_setup(dev_priv); + icp_tc_hpd_detection_setup(dev_priv); } -/* - * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the - * equivalent of SDE. - */ -static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) +static u32 gen11_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) { - icp_hpd_irq_setup(dev_priv, - ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1)); -} - -/* - * JSP behaves exactly the same as MCC above except that port C is mapped to - * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's - * masks & tables rather than ICP's masks & tables. - */ -static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) -{ - icp_hpd_irq_setup(dev_priv, - TGP_DDI_HPD_ENABLE_MASK, 0); + switch (pin) { + case HPD_PORT_TC1: + case HPD_PORT_TC2: + case HPD_PORT_TC3: + case HPD_PORT_TC4: + case HPD_PORT_TC5: + case HPD_PORT_TC6: + return GEN11_HOTPLUG_CTL_ENABLE(pin); + default: + return 0; + } } static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) @@ -3242,12 +3306,13 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) u32 hotplug; hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6); + hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); + hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); } @@ -3256,12 +3321,13 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) u32 hotplug; hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); - hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | - GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6); + hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); + hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } @@ -3282,12 +3348,36 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) gen11_tc_hpd_detection_setup(dev_priv); gen11_tbt_hpd_detection_setup(dev_priv); - if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) - icp_hpd_irq_setup(dev_priv, - TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) - icp_hpd_irq_setup(dev_priv, - ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK); + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + icp_hpd_irq_setup(dev_priv); +} + +static u32 spt_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_A: + return PORTA_HOTPLUG_ENABLE; + case HPD_PORT_B: + return PORTB_HOTPLUG_ENABLE; + case HPD_PORT_C: + return PORTC_HOTPLUG_ENABLE; + case HPD_PORT_D: + return PORTD_HOTPLUG_ENABLE; + default: + return 0; + } +} + +static u32 spt_hotplug2_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_E: + return PORTE_HOTPLUG_ENABLE; + default: + return 0; + } } static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) @@ -3304,14 +3394,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) /* Enable digital hotplug on the PCH */ hotplug = I915_READ(PCH_PORT_HOTPLUG); - hotplug |= PORTA_HOTPLUG_ENABLE | - PORTB_HOTPLUG_ENABLE | - PORTC_HOTPLUG_ENABLE | - PORTD_HOTPLUG_ENABLE; + hotplug &= ~(PORTA_HOTPLUG_ENABLE | + PORTB_HOTPLUG_ENABLE | + PORTC_HOTPLUG_ENABLE | + PORTD_HOTPLUG_ENABLE); + hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables); I915_WRITE(PCH_PORT_HOTPLUG, hotplug); hotplug = I915_READ(PCH_PORT_HOTPLUG2); - hotplug |= PORTE_HOTPLUG_ENABLE; + hotplug &= ~PORTE_HOTPLUG_ENABLE; + hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables); I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); } @@ -3330,6 +3422,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) spt_hpd_detection_setup(dev_priv); } +static u32 ilk_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + switch (pin) { + case HPD_PORT_A: + return DIGITAL_PORTA_HOTPLUG_ENABLE | + DIGITAL_PORTA_PULSE_DURATION_2ms; + default: + return 0; + } +} + static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -3340,9 +3444,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) * The pulse duration bits are reserved on HSW+. */ hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); - hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; - hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | - DIGITAL_PORTA_PULSE_DURATION_2ms; + hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE | + DIGITAL_PORTA_PULSE_DURATION_MASK); + hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables); I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); } @@ -3363,35 +3467,44 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) ibx_hpd_irq_setup(dev_priv); } -static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, - u32 enabled_irqs) +static u32 bxt_hotplug_enables(struct drm_i915_private *i915, + enum hpd_pin pin) +{ + u32 hotplug; + + switch (pin) { + case HPD_PORT_A: + hotplug = PORTA_HOTPLUG_ENABLE; + if (intel_bios_is_port_hpd_inverted(i915, PORT_A)) + hotplug |= BXT_DDIA_HPD_INVERT; + return hotplug; + case HPD_PORT_B: + hotplug = PORTB_HOTPLUG_ENABLE; + if (intel_bios_is_port_hpd_inverted(i915, PORT_B)) + hotplug |= BXT_DDIB_HPD_INVERT; + return hotplug; + case HPD_PORT_C: + hotplug = PORTC_HOTPLUG_ENABLE; + if (intel_bios_is_port_hpd_inverted(i915, PORT_C)) + hotplug |= BXT_DDIC_HPD_INVERT; + return hotplug; + default: + return 0; + } +} + +static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; hotplug = I915_READ(PCH_PORT_HOTPLUG); - hotplug |= PORTA_HOTPLUG_ENABLE | - PORTB_HOTPLUG_ENABLE | - PORTC_HOTPLUG_ENABLE; - - drm_dbg_kms(&dev_priv->drm, - "Invert bit setting: hp_ctl:%x hp_port:%x\n", - hotplug, enabled_irqs); - hotplug &= ~BXT_DDI_HPD_INVERT_MASK; - - /* - * For BXT invert bit has to be set based on AOB design - * for HPD detection logic, update it based on VBT fields. - */ - if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) && - intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) - hotplug |= BXT_DDIA_HPD_INVERT; - if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) && - intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) - hotplug |= BXT_DDIB_HPD_INVERT; - if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) && - intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) - hotplug |= BXT_DDIC_HPD_INVERT; - + hotplug &= ~(PORTA_HOTPLUG_ENABLE | + PORTB_HOTPLUG_ENABLE | + PORTC_HOTPLUG_ENABLE | + BXT_DDIA_HPD_INVERT | + BXT_DDIB_HPD_INVERT | + BXT_DDIC_HPD_INVERT); + hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables); I915_WRITE(PCH_PORT_HOTPLUG, hotplug); } @@ -3404,7 +3517,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); - bxt_hpd_detection_setup(dev_priv, enabled_irqs); + bxt_hpd_detection_setup(dev_priv); } static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) @@ -4122,11 +4235,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; } else { - if (HAS_PCH_JSP(dev_priv)) - dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; - else if (HAS_PCH_MCC(dev_priv)) - dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; - else if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_GEN(dev_priv) >= 11) dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; else if (IS_GEN9_LP(dev_priv)) dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d2175faf7d34..75c45fda0f85 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8410,19 +8410,6 @@ enum { #define SHPD_FILTER_CNT _MMIO(0xc4038) #define SHPD_FILTER_CNT_500_ADJ 0x001D9 -#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) -#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \ - ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \ - ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \ - ICP_TC_HPD_ENABLE(HPD_PORT_TC1)) -#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \ - SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A)) -#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \ - ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \ - ICP_TC_HPD_ENABLE_MASK) - #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) From patchwork Tue Oct 6 14:33:48 2020 Content-Type: text/plain; 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Tue, 6 Oct 2020 14:34:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08AB06E4B1 for ; Tue, 6 Oct 2020 14:34:47 +0000 (UTC) IronPort-SDR: UYprnP3kkMkl33+wJcIdSjXgIYv8VHt+yUxitXCLIBFmD9CnPrwjPX5buC7cru+Gl2uP5VAfh9 Rzsp/QLt86Jw== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="164585729" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="164585729" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:46 -0700 IronPort-SDR: qgKhtp+2LxMJ26+JPV8IjelFpMT0ERyzU/xjuQI1cR0tWZS0XHEIjEyRqSHKP1/FffI0edLP5n 5ONdWnsIIObQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="387898770" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 06 Oct 2020 07:34:44 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:43 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:48 +0300 Message-Id: <20201006143349.5561-20-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 19/20] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä No reason not to use GEN3_IRQ_INIT() on icp+. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 222d2e6d7ee4..63ae60ec2324 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3722,14 +3722,10 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) static void icp_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; u32 mask = SDE_GMBUS_ICP; - drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0); - I915_WRITE(SDEIER, 0xffffffff); - POSTING_READ(SDEIER); - - gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); - I915_WRITE(SDEIMR, ~mask); + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); } static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) From patchwork Tue Oct 6 14:33:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11818779 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F066112E for ; Tue, 6 Oct 2020 14:35:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00AE62065C for ; Tue, 6 Oct 2020 14:35:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00AE62065C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28EB26E4B6; Tue, 6 Oct 2020 14:35:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF3C56E4B6 for ; Tue, 6 Oct 2020 14:35:00 +0000 (UTC) IronPort-SDR: pl+mdRDQtunjDiGLn33VOaogxiVpTQEQQGbKznM4vWQN9giTrIVERBYLzvtD4LFg3JZAYDinp0 T/auJarG6FMA== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="143907662" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="143907662" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 07:34:49 -0700 IronPort-SDR: oxUAjbei/k7LAJBh542Ay8riFdgjY1uNbf45CA3uYM3diBeug3HOKIlOSLbf2c9Xqy3rGj8jHC 9/IN5urPrBgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="343796436" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 06 Oct 2020 07:34:47 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 17:34:46 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Oct 2020 17:33:49 +0300 Message-Id: <20201006143349.5561-21-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201006143349.5561-1-ville.syrjala@linux.intel.com> References: <20201006143349.5561-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 20/20] drm/i915: Get rid of ibx_irq_pre_postinstall() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä ibx_irq_pre_postinstall() looks totally pointless. We can just init both SDEIMR and SDEIER at the same time before enabling the master intererupt. It's equally racy as the other order due to doing all of this from the postinstall stage with the interrupt handler already in place. That is, safe with MSI but racy with shared legacy interrupts. Fortunately we should have MSI on all ilk+. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++--------------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 63ae60ec2324..39927b71982e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2901,24 +2901,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv) I915_WRITE(SERR_INT, 0xffffffff); } -/* - * SDEIER is also touched by the interrupt handler to work around missed PCH - * interrupts. Hence we can't update it after the interrupt handler is enabled - - * instead we unconditionally enable all PCH interrupt sources here, but then - * only unmask them as needed with SDEIMR. - * - * This function needs to be called before interrupts are enabled. - */ -static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv) -{ - if (HAS_PCH_NOP(dev_priv)) - return; - - drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0); - I915_WRITE(SDEIER, 0xffffffff); - POSTING_READ(SDEIER); -} - static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -3520,8 +3502,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) bxt_hpd_detection_setup(dev_priv); } +/* + * SDEIER is also touched by the interrupt handler to work around missed PCH + * interrupts. Hence we can't update it after the interrupt handler is enabled - + * instead we unconditionally enable all PCH interrupt sources here, but then + * only unmask them as needed with SDEIMR. + * + * Note that we currently do this after installing the interrupt handler, + * but before we enable the master interrupt. That should be sufficient + * to avoid races with the irq handler, assuming we have MSI. Shared legacy + * interrupts could still race. + */ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; u32 mask; if (HAS_PCH_NOP(dev_priv)) @@ -3534,8 +3528,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) else mask = SDE_GMBUS_CPT; - gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); - I915_WRITE(SDEIMR, ~mask); + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); } static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3565,15 +3558,13 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->irq_mask = ~display_mask; - ibx_irq_pre_postinstall(dev_priv); + ibx_irq_postinstall(dev_priv); GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, display_mask | extra_mask); gen5_gt_irq_postinstall(&dev_priv->gt); - ibx_irq_postinstall(dev_priv); - if (IS_IRONLAKE_M(dev_priv)) { /* Enable PCU event interrupts * @@ -3708,15 +3699,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) { - if (HAS_PCH_SPLIT(dev_priv)) - ibx_irq_pre_postinstall(dev_priv); - - gen8_gt_irq_postinstall(&dev_priv->gt); - gen8_de_irq_postinstall(dev_priv); - if (HAS_PCH_SPLIT(dev_priv)) ibx_irq_postinstall(dev_priv); + gen8_gt_irq_postinstall(&dev_priv->gt); + gen8_de_irq_postinstall(dev_priv); + gen8_master_intr_enable(dev_priv->uncore.regs); }