From patchwork Tue Oct 6 20:18:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11819195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A24A14D5 for ; Tue, 6 Oct 2020 20:19:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 241042083B for ; Tue, 6 Oct 2020 20:19:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OsrnxJuO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 241042083B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hmagdE+rb+eiGglwioKu0W6dJx1XAbe5a52sAgm8f7M=; b=OsrnxJuOqDpew4FN9tG0UYZzIu v3RjfxOC9Ux22kME0RemJFFR98EeeZOSRaf0E/lQhM9juaofOcOlNzX/wAQ1NOv7YZ7hci8OMaS8w oIL8CWYThOmtdvanQMTWijtppiQv4/RxOnTjmSKvryelnufrGrEIRXyTBH0E5or6pY0qT+V2JRMBG 0S6yyiT8CUoM83Z8E+oRY5Y1aaIBw/V16vGBD0VsKN1qeLcgKf+aTxqjQnzfEbmmK+vpxZYfLFmmr pACIOrVuUoyWmpZzyJH11SOmWJRl3F9mgeC2KYF1Ajx4mcEEvK8YIOWcD64YdlOYy62UzN0HT5aTW fNf4oX9Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPtQF-0007aP-EH; Tue, 06 Oct 2020 20:18:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPtQB-0007ZG-Qd for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2020 20:18:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 947001500; Tue, 6 Oct 2020 13:18:49 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 276FA3F71F; Tue, 6 Oct 2020 13:18:48 -0700 (PDT) From: Andre Przywara To: Catalin Marinas , Will Deacon Subject: [PATCH 1/2] firmware: smccc: Add SMCCC TRNG function call IDs Date: Tue, 6 Oct 2020 21:18:07 +0100 Message-Id: <20201006201808.37665-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201006201808.37665-1-andre.przywara@arm.com> References: <20201006201808.37665-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_161851_919966_B51B5C4B X-CRM114-Status: GOOD ( 12.51 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Lorenzo Pieralisi , Richard Henderson , linux-kernel@vger.kernel.org, Mark Brown , Sudeep Holla , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Ard Biesheuvel The ARM architected TRNG firmware interface, described in ARM spec DEN0098[1], defines an ARM SMCCC based interface to a true random number generator, provided by firmware. Add the definitions of the SMCCC function IDs, as defined by the spec. [1] https://developer.arm.com/documentation/den0098/latest/ Signed-off-by: Ard Biesheuvel Signed-off-by: Andre Przywara --- include/linux/arm-smccc.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 15c706fb0a37..95aae50eaab4 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -99,6 +99,37 @@ ARM_SMCCC_OWNER_STANDARD_HYP, \ 0x21) +/* TRNG entropy source calls (defined by ARM DEN0098) */ +#define ARM_SMCCC_TRNG_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x50) + +#define ARM_SMCCC_TRNG_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x51) + +#define ARM_SMCCC_TRNG_GET_UUID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x52) + +#define ARM_SMCCC_TRNG_RND32 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + +#define ARM_SMCCC_TRNG_RND64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C From patchwork Tue Oct 6 20:18:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11819199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A286714D5 for ; Tue, 6 Oct 2020 20:20:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 660F42083B for ; Tue, 6 Oct 2020 20:20:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vzN+YtkJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 660F42083B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Tue, 06 Oct 2020 20:18:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D47B113E; Tue, 6 Oct 2020 13:18:51 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6A993F71F; Tue, 6 Oct 2020 13:18:49 -0700 (PDT) From: Andre Przywara To: Catalin Marinas , Will Deacon Subject: [PATCH 2/2] arm64: Add support for SMCCC TRNG firmware interface Date: Tue, 6 Oct 2020 21:18:08 +0100 Message-Id: <20201006201808.37665-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201006201808.37665-1-andre.przywara@arm.com> References: <20201006201808.37665-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_161852_656687_C2DAAE5B X-CRM114-Status: GOOD ( 23.14 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Lorenzo Pieralisi , Richard Henderson , linux-kernel@vger.kernel.org, Mark Brown , Sudeep Holla , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ARM architected TRNG firmware interface, described in ARM spec DEN0098[1], defines an ARM SMCCC based interface to a true random number generator, provided by firmware. This can be discovered via the SMCCC >=v1.1 interface, and provides up to 192 bits of entropy per call. Hook this SMC call into arm64's arch_get_random_*() implementation, coming to the rescue when the CPU does not implement the ARM v8.5 RNG system registers. For the detection, we piggy back on the PSCI/SMCCC discovery (which gives us the conduit to use: hvc or smc), then try to call the ARM_SMCCC_TRNG_VERSION function, which returns -1 if this interface is not implemented. [1] https://developer.arm.com/documentation/den0098/latest/ Signed-off-by: Andre Przywara Reviewed-by: Mark Brown --- arch/arm64/include/asm/archrandom.h | 83 +++++++++++++++++++++++++---- 1 file changed, 73 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrandom.h index ffb1a40d5475..b6c291c42a48 100644 --- a/arch/arm64/include/asm/archrandom.h +++ b/arch/arm64/include/asm/archrandom.h @@ -7,6 +7,13 @@ #include #include #include +#include + +static enum smc_trng_status { + SMC_TRNG_UNKNOWN, + SMC_TRNG_NOT_SUPPORTED, + SMC_TRNG_SUPPORTED +} smc_trng_status = SMC_TRNG_UNKNOWN; static inline bool __arm64_rndr(unsigned long *v) { @@ -26,6 +33,36 @@ static inline bool __arm64_rndr(unsigned long *v) return ok; } +static inline bool __check_smc_trng(void) +{ + struct arm_smccc_res res; + + if (smc_trng_status == SMC_TRNG_UNKNOWN) { + /* + * The variable behind the get_version() call is initialised + * as ARM_SMCCC_VERSION_1_0, so getting this could mean: + * a) not checked yet (early at boot, before PSCI init), or + * b) not implemented by firmware. + * Since we don't know which one it is, we return false, but + * don't fix the answer yet. + */ + if (arm_smccc_get_version() <= ARM_SMCCC_VERSION_1_0) + return false; + + /* + * With the knowledge at having at least SMCCC v1.1, we + * can now test the existence of the interface. + */ + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, &res); + if ((int)res.a0 < 0) + smc_trng_status = SMC_TRNG_NOT_SUPPORTED; + else + smc_trng_status = SMC_TRNG_SUPPORTED; + } + + return smc_trng_status == SMC_TRNG_SUPPORTED; +} + static inline bool __must_check arch_get_random_long(unsigned long *v) { return false; @@ -38,26 +75,52 @@ static inline bool __must_check arch_get_random_int(unsigned int *v) static inline bool __must_check arch_get_random_seed_long(unsigned long *v) { + struct arm_smccc_res res; + /* - * Only support the generic interface after we have detected - * the system wide capability, avoiding complexity with the - * cpufeature code and with potential scheduling between CPUs + * Try the ARMv8.5-A RNDR instruction first, but only after + * we have detected the system wide capability, avoiding complexity + * with the cpufeature code and with potential scheduling between CPUs * with and without the feature. */ - if (!cpus_have_const_cap(ARM64_HAS_RNG)) - return false; + if (cpus_have_const_cap(ARM64_HAS_RNG)) + return __arm64_rndr(v); - return __arm64_rndr(v); -} + if (__check_smc_trng()) { + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, &res); + if ((int)res.a0 < 0) + return false; + *v = res.a3; + return true; + } + + return false; +} static inline bool __must_check arch_get_random_seed_int(unsigned int *v) { + struct arm_smccc_res res; unsigned long val; - bool ok = arch_get_random_seed_long(&val); - *v = val; - return ok; + if (cpus_have_const_cap(ARM64_HAS_RNG)) { + if (arch_get_random_seed_long(&val)) { + *v = val; + return true; + } + return false; + } + + if (__check_smc_trng()) { + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 32, &res); + if ((int)res.a0 < 0) + return false; + + *v = res.a3 & GENMASK(31, 0); + return true; + } + + return false; } static inline bool __init __early_cpu_has_rndr(void)