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Signed-off-by: Miquel Raynal Reviewed-by: Hans de Goede --- drivers/ata/ahci_mvebu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index d4bba3ace45d..43bb2db59698 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -30,7 +30,7 @@ struct ahci_mvebu_plat_data { int (*plat_config)(struct ahci_host_priv *hpriv); - unsigned int flags; + unsigned int host_flags; }; static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv, @@ -196,7 +196,7 @@ static int ahci_mvebu_probe(struct platform_device *pdev) if (IS_ERR(hpriv)) return PTR_ERR(hpriv); - hpriv->flags |= pdata->flags; + hpriv->flags |= pdata->host_flags; hpriv->plat_data = (void *)pdata; rc = ahci_platform_enable_resources(hpriv); @@ -227,7 +227,7 @@ static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = { static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = { .plat_config = ahci_mvebu_armada_3700_config, - .flags = AHCI_HFLAG_SUSPEND_PHYS, + .host_flags = AHCI_HFLAG_SUSPEND_PHYS, }; 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Signed-off-by: Miquel Raynal Reviewed-by: Hans de Goede --- drivers/ata/ahci_mvebu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index 43bb2db59698..1cdc126882eb 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -96,6 +96,11 @@ static int ahci_mvebu_armada_3700_config(struct ahci_host_priv *hpriv) return 0; } +static int ahci_mvebu_armada_8k_config(struct ahci_host_priv *hpriv) +{ + return 0; +} + /** * ahci_mvebu_stop_engine * @@ -230,6 +235,10 @@ static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = { .host_flags = AHCI_HFLAG_SUSPEND_PHYS, }; +static const struct ahci_mvebu_plat_data ahci_mvebu_armada_8k_plat_data = { + .plat_config = ahci_mvebu_armada_8k_config, +}; + static const struct of_device_id ahci_mvebu_of_match[] = { { .compatible = "marvell,armada-380-ahci", @@ -239,6 +248,10 @@ static const struct of_device_id ahci_mvebu_of_match[] = { .compatible = "marvell,armada-3700-ahci", .data = &ahci_mvebu_armada_3700_plat_data, }, + { + .compatible = "marvell,armada-8k-ahci", + .data = &ahci_mvebu_armada_8k_plat_data, + }, { }, }; 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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: MWXrW09F/IQUzpkumraXBN3TeCumLSvmbaBtb99aKIpU+vGDegnvYobERtiKonZzgHGgRtje8Uzu9qI+vFlXTKCU/zDLFhfJiJkOWc0Vo6u1tmFNybsN0rQgKDIz5w0NrJnUInwb/VAy/KwEgnwtJ6oBNL6oz7VquYEDyeDPXTxPIMrmn11pGtwhkG7VCJbI51aUHjpNbCnM/NuVNLYGKTS9i6rmhrWscYPKFCB3Ip9XSobAZWQDGlhhXJDcq3oCe3Tl9QHAhCTuydSlc/bpSKFNgW2uEsUWAk/fMd7Djje0PTPs3IaOV3ueIIRshQrhSuSdIa5nK51l6+rLBswcRXKZ1aU7RgQKYHuOX8tVS8tpoe8EYDg6vg3dvWTJy5UwC+/lE1bW7oRBNGd+c84iUvc8ZC40GGo6Q2RH8nIwEvcoGHV72K+0QUgMhTZDl41t7sGWJ8xc4fsQNJ1VhkhqxDOiS74OVz/DEHHLxR4IPi6CNiv1PhAYVdhxUmr8Ru5tm1xM9vhiOHIeBYcSVZUFkmQCX8YW6rW1wgtD+P6NJDlEUkKfIpxpM69klVL8RE7FGYuEMcW59vAIfipXJIPkKNRJZBx8TJo7ZqBa32RgB2v4rjaOfvs029kQy/+jY8ev098Z75Lg6aYkWKmPoxIvxw== X-OriginatorOrg: voleatech.de X-MS-Exchange-CrossTenant-Network-Message-Id: 9a91ad0c-5c66-4d37-5666-08d86ad816cc X-MS-Exchange-CrossTenant-AuthSource: AM8PR05MB7251.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2020 15:46:00.2458 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b82a99f6-7981-4a72-9534-4d35298f847b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mP2s/CBUJAfv10wXMPOPLHjzB7R7c/oaRasCIAwl/yHi/Q78GuzkdoFUVXaU9Ey2x29haaaMfBxNBFXHsv7hPnF4OJcKPyZ8QZQmMYxysu4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4018 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201007_114605_922278_A43E2C49 X-CRM114-Status: GOOD ( 25.73 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.8.125 listed in wl.mailspike.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.8.125 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@lunn.ch, jason@lakedaemon.net, devicetree@vger.kernel.org, antoine.tenart@bootlin.com, viresh.kumar@linaro.org, rjw@rjwysocki.net, maxime.chevallier@bootlin.com, linux-ide@vger.kernel.org, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sven Auhagen The CP110 SATA unit has 2 ports, and a dedicated ICU entry per port. In the past, the AHCI SATA driver only supported one interrupt per SATA unit. To solve this conflict, the 2 SATA wired interrupts in the South-Bridge got configured as 1 GIC interrupt in the North-Bridge, regardless of the number of SATA ports actually enabled/in use, and the DT bindings only referenced the interrupt of one port. Since then, this limitation has been addressed and this patch ensures backward compatibility with old DTs not describing SATA ports correctly directly from the AHCI MVEBU driver. This way, we will be able to drop the hack from the ICU driver. IOW, when the A8k compatible string is used and there is no sub-nodes in the DT, we fake the creation and mapping of the second (missing) interrupt. Signed-off-by: Sven Auhagen Signed-off-by: Miquel Raynal --- drivers/ata/ahci.h | 3 + drivers/ata/ahci_mvebu.c | 235 ++++++++++++++++++++++++++++++++- drivers/ata/libahci.c | 3 +- drivers/ata/libahci_platform.c | 3 + include/linux/ahci_platform.h | 1 + 5 files changed, 239 insertions(+), 6 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index d991dd46e89c..8cb256eec86b 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -407,6 +407,9 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class, int ahci_do_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline, bool *online); +void ahci_handle_port_interrupt(struct ata_port *ap, + void __iomem *port_mmio, u32 status); + unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); int ahci_stop_engine(struct ata_port *ap); void ahci_start_fis_rx(struct ata_port *ap); diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index 1cdc126882eb..62e9b94e2bba 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "ahci.h" @@ -28,9 +29,14 @@ #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) +#define ICU_SATA0_ICU_ID 109 +#define ICU_SATA1_ICU_ID 107 + struct ahci_mvebu_plat_data { int (*plat_config)(struct ahci_host_priv *hpriv); unsigned int host_flags; + unsigned int resource_flags; + unsigned int port_irq[2]; }; static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv, @@ -96,6 +102,213 @@ static int ahci_mvebu_armada_3700_config(struct ahci_host_priv *hpriv) return 0; } +static int ahci_get_per_port_irq_armada8k(struct ata_host *host, int port) +{ + struct ahci_host_priv *hpriv = host->private_data; + struct ahci_mvebu_plat_data *pdata = hpriv->plat_data; + + return pdata->port_irq[port]; +} + +static irqreturn_t ahci_multi_irqs_intr_hard_armada8k(int irq, void *dev_instance) +{ + struct ata_port *ap = dev_instance; + struct ata_host *host = ap->host; + struct ahci_host_priv *hpriv = host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + void __iomem *mmio = hpriv->mmio; + u32 status; + + VPRINTK("ENTER\n"); + + status = readl(port_mmio + PORT_IRQ_STAT); + writel(status, port_mmio + PORT_IRQ_STAT); + + spin_lock(ap->lock); + ahci_handle_port_interrupt(ap, port_mmio, status); + spin_unlock(ap->lock); + + writel(BIT(ap->port_no), mmio + HOST_IRQ_STAT); + + VPRINTK("EXIT\n"); + + return IRQ_HANDLED; +} + +static int ahci_host_activate_multi_irqs_armada8k(struct ata_host *host, + struct scsi_host_template *sht) +{ + struct ahci_host_priv *hpriv = host->private_data; + int i, rc; + + rc = ata_host_start(host); + if (rc) + return rc; + /* + * Requests IRQs one per port + */ + for (i = 0; i < host->n_ports; i++) { + struct ahci_port_priv *pp = host->ports[i]->private_data; + int irq = hpriv->get_irq_vector(host, i); + + /* Do not receive interrupts sent by dummy ports */ + if (!pp) { + disable_irq(irq); + continue; + } + + rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard_armada8k, + 0, pp->irq_desc, host->ports[i]); + + if (rc) + return rc; + ata_port_desc(host->ports[i], "irq %d", irq); + } + + return ata_host_register(host, sht); +} + +static int ahci_mvebu_armada_8k_irq_backwards(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct device_node *np = of_irq_find_parent(dev->of_node); + struct ahci_mvebu_plat_data *pdata = hpriv->plat_data; + struct irq_data *irqd = irq_get_irq_data(pdata->port_irq[0]); + int host_irq = irqd ? irqd_to_hwirq(irqd) : 0; + int missing_irq = (host_irq == ICU_SATA1_ICU_ID) ? + ICU_SATA0_ICU_ID : ICU_SATA1_ICU_ID; + struct irq_fwspec fwspec = { + .fwnode = of_node_to_fwnode(np), + .param_count = 2, + .param = {missing_irq, IRQ_TYPE_LEVEL_HIGH}, + }; + + if (of_get_child_count(dev->of_node)) + return 0; + + pdata->port_irq[1] = irq_create_fwspec_mapping(&fwspec); + if (pdata->port_irq[1]) + hpriv->mask_port_map = GENMASK(1, 0); + + return 0; +} + +static int ahci_platform_init_host_armada8k(struct platform_device *pdev, + struct ahci_host_priv *hpriv, + const struct ata_port_info *pi_template, + struct scsi_host_template *sht) +{ + struct ahci_mvebu_plat_data *pdata = hpriv->plat_data; + struct device *dev = &pdev->dev; + struct ata_port_info pi = *pi_template; + const struct ata_port_info *ppi[] = { &pi, NULL }; + struct device_node *child; + struct ata_host *host; + int i, port_irq, n_ports, rc, child_nodes, port = 0; + + /* Get IRQs per port */ + child_nodes = of_get_child_count(dev->of_node); + if (child_nodes) { + for_each_child_of_node(dev->of_node, child) { + + port_irq = of_irq_get(child, 0); + if (!port_irq) + port_irq = -EINVAL; + if (port_irq < 0) { + rc = port_irq; + return rc; + } + + pdata->port_irq[port] = port_irq; + port++; + } + } else { + /* Backwards Compatibility Check */ + port_irq = platform_get_irq(pdev, 0); + if (port_irq > 0) { + pdata->port_irq[0] = port_irq; + ahci_mvebu_armada_8k_irq_backwards(hpriv, dev); + } else { + dev_err(dev, "no irq\n"); + return -EINVAL; + } + } + + hpriv->get_irq_vector = ahci_get_per_port_irq_armada8k; + + /* prepare host */ + pi.private_data = (void *)(unsigned long)hpriv->flags; + + ahci_save_initial_config(dev, hpriv); + + if (hpriv->cap & HOST_CAP_NCQ) + pi.flags |= ATA_FLAG_NCQ; + + if (hpriv->cap & HOST_CAP_PMP) + pi.flags |= ATA_FLAG_PMP; + + ahci_set_em_messages(hpriv, &pi); + + /* CAP.NP sometimes indicate the index of the last enabled + * port, at other times, that of the last possible port, so + * determining the maximum port number requires looking at + * both CAP.NP and port_map. + */ + n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); + + host = ata_host_alloc_pinfo(dev, ppi, n_ports); + if (!host) + return -ENOMEM; + + host->private_data = hpriv; + + if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) + host->flags |= ATA_HOST_PARALLEL_SCAN; + else + dev_info(dev, "SSS flag set, parallel bus scan disabled\n"); + + if (pi.flags & ATA_FLAG_EM) + ahci_reset_em(host); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + + ata_port_desc(ap, "mmio %pR", + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); + + /* set enclosure management message type */ + if (ap->flags & ATA_FLAG_EM) + ap->em_message_type = hpriv->em_msg_type; + + /* disabled/not-implemented port */ + if (!(hpriv->port_map & (1 << i))) + ap->ops = &ata_dummy_port_ops; + } + + if (hpriv->cap & HOST_CAP_64) { + rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); + if (rc) { + rc = dma_coerce_mask_and_coherent(dev, + DMA_BIT_MASK(32)); + if (rc) { + dev_err(dev, "Failed to enable 64-bit DMA.\n"); + return rc; + } + dev_warn(dev, "Enable 32-bit DMA instead of 64-bit.\n"); + } + } + + rc = ahci_reset_controller(host); + if (rc) + return rc; + + ahci_init_controller(host); + ahci_print_info(host, "platform"); + + return ahci_host_activate_multi_irqs_armada8k(host, sht); +} + static int ahci_mvebu_armada_8k_config(struct ahci_host_priv *hpriv) { return 0; @@ -189,15 +402,22 @@ static struct scsi_host_template ahci_platform_sht = { static int ahci_mvebu_probe(struct platform_device *pdev) { - const struct ahci_mvebu_plat_data *pdata; + const struct ahci_mvebu_plat_data *pdata_plat; + struct ahci_mvebu_plat_data *pdata; struct ahci_host_priv *hpriv; int rc; - pdata = of_device_get_match_data(&pdev->dev); - if (!pdata) + pdata_plat = of_device_get_match_data(&pdev->dev); + if (!pdata_plat) return -EINVAL; - hpriv = ahci_platform_get_resources(pdev, 0); + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + memcpy(pdata, pdata_plat, sizeof(*pdata)); + + hpriv = ahci_platform_get_resources(pdev, pdata->resource_flags); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); @@ -214,7 +434,11 @@ static int ahci_mvebu_probe(struct platform_device *pdev) if (rc) goto disable_resources; - rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info, + if (pdata->resource_flags & AHCI_PLATFORM_A8K_QUIRK) + rc = ahci_platform_init_host_armada8k(pdev, hpriv, &ahci_mvebu_port_info, + &ahci_platform_sht); + else + rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info, &ahci_platform_sht); if (rc) goto disable_resources; @@ -237,6 +461,7 @@ static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = { static const struct ahci_mvebu_plat_data ahci_mvebu_armada_8k_plat_data = { .plat_config = ahci_mvebu_armada_8k_config, + .resource_flags = AHCI_PLATFORM_A8K_QUIRK, }; static const struct of_device_id ahci_mvebu_of_match[] = { diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index ea5bf5f4cbed..0e6eaa2e03a9 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -1799,7 +1799,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) ata_port_abort(ap); } -static void ahci_handle_port_interrupt(struct ata_port *ap, +void ahci_handle_port_interrupt(struct ata_port *ap, void __iomem *port_mmio, u32 status) { struct ata_eh_info *ehi = &ap->link.eh_info; @@ -1882,6 +1882,7 @@ static void ahci_handle_port_interrupt(struct ata_port *ap, ata_port_freeze(ap); } } +EXPORT_SYMBOL_GPL(ahci_handle_port_interrupt); static void ahci_port_intr(struct ata_port *ap) { diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 129556fcf6be..21332a33f766 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -464,6 +464,9 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, if (!child_nodes) hpriv->nports = 1; + if (!child_nodes && flags & AHCI_PLATFORM_A8K_QUIRK) + hpriv->nports = 2; + hpriv->phys = devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GFP_KERNEL); if (!hpriv->phys) { rc = -ENOMEM; diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h index 49e5383d4222..b31972e0bfbf 100644 --- a/include/linux/ahci_platform.h +++ b/include/linux/ahci_platform.h @@ -42,5 +42,6 @@ int ahci_platform_suspend(struct device *dev); int ahci_platform_resume(struct device *dev); #define AHCI_PLATFORM_GET_RESETS 0x01 +#define AHCI_PLATFORM_A8K_QUIRK 0x02 #endif /* _AHCI_PLATFORM_H */ From patchwork Wed Oct 7 15:45:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Auhagen X-Patchwork-Id: 11820853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BB02618 for ; Wed, 7 Oct 2020 15:48:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A40A20782 for ; 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Now that this limitation has been addressed and the hack moved in the (historically) responsible SATA driver, ahci_{platform,mvebu}.c, let's clean this driver section. Signed-off-by: Miquel Raynal Acked-by: Marc Zyngier Reviewed-by: Hans de Goede --- drivers/irqchip/irq-mvebu-icu.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c index 91adf771f185..3e29f8d5b33b 100644 --- a/drivers/irqchip/irq-mvebu-icu.c +++ b/drivers/irqchip/irq-mvebu-icu.c @@ -38,8 +38,6 @@ /* ICU definitions */ #define ICU_MAX_IRQS 207 -#define ICU_SATA0_ICU_ID 109 -#define ICU_SATA1_ICU_ID 107 struct mvebu_icu_subset_data { unsigned int icu_group; @@ -111,22 +109,6 @@ static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) } writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); - - /* - * The SATA unit has 2 ports, and a dedicated ICU entry per - * port. The ahci sata driver supports only one irq interrupt - * per SATA unit. To solve this conflict, we configure the 2 - * SATA wired interrupts in the south bridge into 1 GIC - * interrupt in the north bridge. Even if only a single port - * is enabled, if sata node is enabled, both interrupts are - * configured (regardless of which port is actually in use). - */ - if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { - writel_relaxed(icu_int, - icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); - writel_relaxed(icu_int, - icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); - } } static struct irq_chip mvebu_icu_nsr_chip = { From patchwork Wed Oct 7 15:45:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Auhagen X-Patchwork-Id: 11820847 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B22D8618 for ; Wed, 7 Oct 2020 15:46:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6262A20782 for ; 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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: zpvAfBnNVYFcnzuxivrRDkhmT3DYk08r0eodYte5oGy2vQKPl1k+Kuj/SHCVqi+ZG2cB5cMOQ/1mtEEPdnGwTSckUBneoempS3XwZR1Jb8YP3fixqf+LbhIjjrlbvlp4m9M6iRFUp/71Xub6kKRCfEi9XhuAecIng5NjYgr7kOfum2m1/TL5cRWQzFoHGZYCwgsOjhk+GARmBB/ZOkbR2aYWU4giQQflhTsFTylgofUYGLrR/SNfCsoKoYAvq0B2YbtzpJCYWvUvcSqeXFzIcqQUKJmfyTIMM3uz2wc/JcTnqNpkNMrMwiD7+/ZTQZ0cFHA25CXLv0lVEicU99xmuRZSPpxraEnY889td8nRAfK6RLiF93qOzUd7Kx9cuCPkO/8qSsCJdc75wodskWXko3+l9wY88ZuE9tLQjj0OsSbvKkIkUBg6YQnUb4TzxMXHJnXpVf5yeglK7BS2rmM9MuGc9mwbgaePn7KdHXbQdZDCbGT8W7Wvapm+Mb4jkmUIjnGqHftC1ePJgF1+Ia6jlmXTK/LzwUgpCDyIyZNYSs7Lx1IHO9kxf+piHZ/36O4CS/RfGMiED92OSUo4QpEhfGMG8+gVb20Vm9ZUKM9kqkLjjvVRLA0y3i/Ti0UrAz/ple2h13TDye+nXapD9euiOw== X-OriginatorOrg: voleatech.de X-MS-Exchange-CrossTenant-Network-Message-Id: 1cdcf0be-ea50-42dd-732c-08d86ad81829 X-MS-Exchange-CrossTenant-AuthSource: AM8PR05MB7251.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2020 15:46:02.6045 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b82a99f6-7981-4a72-9534-4d35298f847b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VsoHfRkCc+xe/p4Wojng8bHCVax8IRPVkrADs77dIlGgfF+QF04zqcY/1ui+d+LFRircOzIwD4bl1evtUhQwsm9pPFVlToKVJ30tymWEVvk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4018 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201007_114609_953709_D1DE895F X-CRM114-Status: GOOD ( 11.26 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.8.97 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [40.107.8.97 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@lunn.ch, jason@lakedaemon.net, devicetree@vger.kernel.org, antoine.tenart@bootlin.com, viresh.kumar@linaro.org, rjw@rjwysocki.net, maxime.chevallier@bootlin.com, linux-ide@vger.kernel.org, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Miquel Raynal Update bindings to reflect the fact that a SATA IP can either have: - only one interrupt: in this case an 'interrupts' property is declared at the root of the node; or - each SATA port can have their own interrupt: in this case there is one 'interrupts' property per port/sub-node and none at the root. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Reviewed-by: Hans de Goede --- Documentation/devicetree/bindings/ata/ahci-platform.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index 77091a277642..83d715cbcecd 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -49,6 +49,12 @@ And at least one of the following properties: - phys : reference to the SATA PHY node - target-supply : regulator for SATA target power +Sub-nodes optional properties: +- interrupts : , please + note that either the root SATA node has the + interrupts property, or there is one per SATA + port, but not both at the same time. + Examples: sata@ffe08000 { compatible = "snps,spear-ahci"; From patchwork Wed Oct 7 15:45:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Auhagen X-Patchwork-Id: 11820855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC3B41580 for ; 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Wed, 7 Oct 2020 15:46:03 +0000 From: sven.auhagen@voleatech.de To: axboe@kernel.dk, hdegoede@redhat.com, robh+dt@kernel.org, tglx@linutronix.de, maz@kernel.org, gregory.clement@bootlin.com Subject: [PATCH 6/7] dt-bindings: ata: Update ahci_mvebu bindings Date: Wed, 7 Oct 2020 17:45:53 +0200 Message-Id: <20201007154554.66650-7-sven.auhagen@voleatech.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20201007154554.66650-1-sven.auhagen@voleatech.de> References: <20201007154554.66650-1-sven.auhagen@voleatech.de> X-Originating-IP: [109.193.235.168] X-ClientProxiedBy: AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) To AM8PR05MB7251.eurprd05.prod.outlook.com (2603:10a6:20b:1d4::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from svensmacbookair.sven.lan (109.193.235.168) by AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.21 via Frontend Transport; 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Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Reviewed-by: Hans de Goede --- Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index 83d715cbcecd..78d9d413a5c6 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -15,6 +15,7 @@ Required properties: - "ibm,476gtr-ahci" - "marvell,armada-380-ahci" - "marvell,armada-3700-ahci" + - "marvell,armada-8k-ahci" - "snps,dwc-ahci" - "snps,spear-ahci" - "generic-ahci" From patchwork Wed Oct 7 15:45:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Auhagen X-Patchwork-Id: 11820849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0E9A618 for ; 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Wed, 7 Oct 2020 15:46:04 +0000 From: sven.auhagen@voleatech.de To: axboe@kernel.dk, hdegoede@redhat.com, robh+dt@kernel.org, tglx@linutronix.de, maz@kernel.org, gregory.clement@bootlin.com Subject: [PATCH 7/7] arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts Date: Wed, 7 Oct 2020 17:45:54 +0200 Message-Id: <20201007154554.66650-8-sven.auhagen@voleatech.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20201007154554.66650-1-sven.auhagen@voleatech.de> References: <20201007154554.66650-1-sven.auhagen@voleatech.de> X-Originating-IP: [109.193.235.168] X-ClientProxiedBy: AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) To AM8PR05MB7251.eurprd05.prod.outlook.com (2603:10a6:20b:1d4::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from svensmacbookair.sven.lan (109.193.235.168) by AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.21 via Frontend Transport; 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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: 6GFO0XovvrfLyMr13wnE0PPqSfxJJBxoHuW/w5dmN6bhBLwY+vqJ4EqvhDHcMxLNuSWwjcOfnxDUrwuYTg1dVarf6qa8nVoLxcEgPV2utF5go1VlsSltDCw8cGD232Xk+1wjhSe8ebZ+jHgjE/AaGAOBp7Wc4dpJ3e2sFpeUQ26ionI6MTC9YrmU5Lop69b/svcbNGonkAvFGhm99tpy7hbdCaVRTEcGcfcFG2xcCIwRG+V62Mhvsl/6VL+JauKuuSpDdGgS6Zx1+7Gldxutu49j+xAnGQ4JViqSZt9q6w5VDzhq63d5ToQ6oo7Bx9LjUD3u1flp7O8Y7Mzd/d1QiP04x3hDieUhteaIFTmEZpdtwFraIeNMC6zJeE4XeFvyWWglfHtTOZGEvmQQVTmRht4LcV5bY9aURJzUre+nNu0T+XqCgQLAUxZ9evR28njb5o6bg7EWrG4MILcyWynN53IXUpdtYB8/6l+9QJdQVCuDkm5BexvWtFCthSf9rvm6Mo2LgbiF6pbGEj1uRk6Z9ZfpulgPushPOG6nmsu2V/cAIEUTWdZ2Pdy2L1DvlOz5mcPYw8gJbEKWPj2A6OqFKDHftVQ18cW/gHNTws2sEdZ4oyhX+vnbLJ1S/9vFtuWXblbB/KnMLh8fnaF0jpDhww== X-OriginatorOrg: voleatech.de X-MS-Exchange-CrossTenant-Network-Message-Id: 3018760e-2727-4a5e-e5d8-08d86ad81959 X-MS-Exchange-CrossTenant-AuthSource: AM8PR05MB7251.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2020 15:46:04.5559 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b82a99f6-7981-4a72-9534-4d35298f847b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PM+2pHr8+/YViTeaHy39g2v34ZtqR9zjTtc1sBRggnY/fax7gLjmQ7SW/xnfDsSbn0E5NKxaFByFlCXFTQlrM7BIQEcjKa4zlDrqSVrnOkE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4018 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201007_114613_333508_A2603957 X-CRM114-Status: GOOD ( 10.55 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.8.97 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [40.107.8.97 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@lunn.ch, jason@lakedaemon.net, devicetree@vger.kernel.org, antoine.tenart@bootlin.com, viresh.kumar@linaro.org, rjw@rjwysocki.net, maxime.chevallier@bootlin.com, linux-ide@vger.kernel.org, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sven Auhagen There are two SATA ports per CP110. Each of them has a dedicated interrupt. Describe the real hardware by adding two SATA ports to the CP110 SATA node. Signed-off-by: Sven Auhagen Signed-off-by: Thomas Petazzoni Signed-off-by: Miquel Raynal Reviewed-by: Hans de Goede --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16beabf5..ec27294f097b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -300,11 +300,9 @@ }; CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; + compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; dma-coherent; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP11X_LABEL(clk) 1 15>, <&CP11X_LABEL(clk) 1 16>; #address-cells = <1>; @@ -312,10 +310,12 @@ status = "disabled"; sata-port@0 { + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; reg = <0>; }; sata-port@1 { + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; reg = <1>; }; };