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Thu, 8 Oct 2020 07:16:30 +0000 (GMT) From: Maninder Singh To: linux@armlinux.org.uk, ndesaulniers@google.com, caij2003@gmail.com, tglx@linutronix.de, bigeasy@linutronix.de, maz@kernel.org, valentin.schneider@arm.com, vincent.whitchurch@axis.com, nhuck@google.com, akpm@linux-foundation.org, 0x7f454c46@gmail.com, will@kernel.org Subject: [PATCH 1/3] arm: introduce self pointer in thread info Date: Thu, 8 Oct 2020 12:45:31 +0530 Message-Id: <1602141333-17822-2-git-send-email-maninder1.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEKsWRmVeSWpSXmKPExsWy7bCmpq7S3rp4gy+ThC0mTHvBYnFxd6rF nPVr2CymXZzEbLFy3k5Gi02Pr7FaXN41h83i0NS9jBaH57exWOycc5LV4sOE/0wWmw9/YrHY vGkqs8Whk3MZLbbP/8lscX6bv0XLHVMHQY8189Ywely+dpHZ4/q6AI+ds+6yeyzYVOqxaVUn m8e7c+fYPU7M+M3isXlJvUffllWMHp83yQVwR3HZpKTmZJalFunbJXBlrF/7grHggWLFhRkr mBoYW6W7GDk5JARMJA6en84OYgsJ7GaUaJpc3cXIBWR/YpRYfWUTC4TzjVHiUdMiZpiOtve3 oRJ7GSVuzXvLBuF8ZZRoXnCfFaSKTUBPYtWuPWBVIgJTmCTmfV0O5jALLGKUmHOxnxGkSljA XuLMn09gNouAqsSZB9eYQGxeAXeJmfeaWSD2yUncPNcJtJuDg1PAQ+LvR02QORICezgktlyZ wgpR4yIxcd5OqPuEJV4d38IOYUtJvOxvY4doaGaU+LRvLSOEM4VRYunFj1Dd9hKvmxuYQDYw C2hKrN+lDxGWlZh6ah3YQcwCfBK9v58wQcR5JXbMg7FVJVpuboAaIy3x+eNHqKM9JM6cWMYM CZfZjBLb125nmcAoNwthxQJGxlWMkqkFxbnpqcWmBUZ5qeV6xYm5xaV56XrJ+bmbGMHJSstr B+PDBx/0DjEycTAeYpTgYFYS4U33rokX4k1JrKxKLcqPLyrNSS0+xCjNwaIkzqv040yckEB6 YklqdmpqQWoRTJaJg1OqgWnN/fW3jPdvEbunnBqyuL9MKsNwVe6nyf0J7FKG3qt9l7owfTr8 beX+vzVL2T2n5Nzz6Fx84YH+UoeNz4zXJeS7Ojy+flbXtJlzyRa5nHTdZddOBkYzt8Sees0X X7732uLVrtcrNsv9Cbm+/WeNxacX5+dt49HryLkZdGRJ92veCOnjm53iolRC1zo8dLGql35X mPLfzmGn+PYw4Rlne/fGM24wDtm/b4lUdWGd5+nFmp78bn672UuMjr1tSS+I3smct+XmhLku Tz3jw1v/Hy67duPXox2+XCKijkfKrC07P9R3FS7e8fjdZYnwy+JxZ8QKHkf6Z4i5zGxeb3mC V/vHplRO3ofzF70MavG4n67EUpyRaKjFXFScCADEoZI3xQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWy7bCSnO7FPXXxBjv7RCwmTHvBYnFxd6rF nPVr2CymXZzEbLFy3k5Gi02Pr7FaXN41h83i0NS9jBaH57exWOycc5LV4sOE/0wWmw9/YrHY vGkqs8Whk3MZLbbP/8lscX6bv0XLHVMHQY8189Ywely+dpHZ4/q6AI+ds+6yeyzYVOqxaVUn m8e7c+fYPU7M+M3isXlJvUffllWMHp83yQVwR3HZpKTmZJalFunbJXBlrF/7grHggWLFhRkr mBoYW6W7GDk5JARMJNre32bpYuTiEBLYzSjx8/86NoiEtMTPf+9ZIGxhiZX/nrNDFH1mlDi0 ai87SIJNQE9i1a49YN0iAkuYJI5emswK4jALLGOUaP+7lhWkSljAXuLMn0+MIDaLgKrEmQfX mEBsXgF3iZn3mqFWyEncPNfJ3MXIwcEp4CHx96MmSFgIqGRi113WCYx8CxgZVjFKphYU56bn FhsWGOallusVJ+YWl+al6yXn525iBEeDluYOxu2rPugdYmTiYDzEKMHBrCTCm+5dEy/Em5JY WZValB9fVJqTWnyIUZqDRUmc90bhwjghgfTEktTs1NSC1CKYLBMHp1QDk0vwpoYMqY9XKg29 DuWaTclY9/7X3NlbhBXe3NP9kc69PFvx2blHv3OYtLQnJCWzGjqVlTdO1z7C+kz+kpnrTkft dZ8DLprX7tWVd2JOX7aVVzFyJ8cmi30JxZvr1K4eaZTYcCXm8sxfdZ/li7suxsqobb+8REC/ jaNi25SC4JcCd98d3co961luTYNeSnZNqEASs3TKyZn3DTbMqvD01bnXdOne49hYXVuToNBr f9XVlscYcv1Ol/q5cqv7cnUtv6m2lqbHf8sJvbLTXm6VP3XCr9VLI7U+X/KpMD4om9m/um6Z 0dypUX+jsw+ynZObyWB80bP6ai7/h5TkvadeMDtuP+2acteAZZGPidROJZbijERDLeai4kQA vSWzoPUCAAA= X-CMS-MailID: 20201008071633epcas5p20f5c533ac67ab235997e7e4a8ad3022b X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20201008071633epcas5p20f5c533ac67ab235997e7e4a8ad3022b References: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_031800_443644_B068BCE1 X-CRM114-Status: GOOD ( 23.30 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [203.254.224.24 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: v.narang@samsung.com, Maninder Singh , a.sahrawat@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org self pointer to thread info is added in thread info. It is base change required for IRQ stack on ARM. both stacks will have pointer to thread_info at bottom. Co-developed-by: Vaneet Narang Signed-off-by: Vaneet Narang Signed-off-by: Maninder Singh --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/include/asm/assembler.h | 3 +++ arch/arm/include/asm/thread_info.h | 27 +++++++++++++++++++++++++++ include/linux/thread_info.h | 4 ++++ kernel/fork.c | 1 + 5 files changed, 45 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe2f17eb2..434442f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1667,6 +1667,16 @@ config STACKPROTECTOR_PER_TASK Enable this option to switch to a different method that uses a different canary value for each task. +config IRQ_STACK + bool "use separate stacks for Interrupts" + default n + depends on FRAME_POINTER && !CC_IS_CLANG + help + Select this option to use separate stacks for Interrupt handling code. + It will add latency in fetching thread info of one more derefer operation + and add latency in Interrupt serve at time as for each Interrupt, thread_info + pointer needs to be stored at bottom of interrupt stack. + endmenu menu "Boot options" diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index fce52eed..8512bdc 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -207,6 +207,9 @@ THUMB( mov \rd, sp ) THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT +#ifdef CONFIG_IRQ_STACK + ldr \rd, [\rd] +#endif .endm /* diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 536b6b9..a4d5f76 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -44,6 +44,9 @@ struct cpu_context_save { * __switch_to() assumes cpu_context follows immediately after cpu_domain. */ struct thread_info { +#ifdef CONFIG_IRQ_STACK + void *tinfo_ptr; /* pointer to self thread_info */ +#endif unsigned long flags; /* low level flags */ int preempt_count; /* 0 => preemptable, <0 => bug */ mm_segment_t addr_limit; /* address limit */ @@ -67,14 +70,33 @@ struct thread_info { #endif }; + +#ifdef CONFIG_IRQ_STACK +#define INIT_THREAD_SELF_PTR \ + .tinfo_ptr = &init_thread_union.thread_info, +#else +#define INIT_THREAD_SELF_PTR +#endif + #define INIT_THREAD_INFO(tsk) \ { \ + INIT_THREAD_SELF_PTR \ .task = &tsk, \ .flags = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ .addr_limit = KERNEL_DS, \ } + +#ifdef CONFIG_IRQ_STACK +#define TASK_THREAD_SELF_POINTER(tsk) \ +{ \ + struct thread_info *ti = task_thread_info(tsk); \ + \ + ti->tinfo_ptr = ti; \ +} +#endif + /* * how to get the thread information struct from C */ @@ -82,8 +104,13 @@ struct thread_info { static inline struct thread_info *current_thread_info(void) { +#ifdef CONFIG_IRQ_STACK + return (struct thread_info *) + (*((unsigned long *)(current_stack_pointer & ~(THREAD_SIZE - 1)))); +#else return (struct thread_info *) (current_stack_pointer & ~(THREAD_SIZE - 1)); +#endif } #define thread_saved_pc(tsk) \ diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h index e93e249..ddf7b43 100644 --- a/include/linux/thread_info.h +++ b/include/linux/thread_info.h @@ -43,6 +43,10 @@ enum { #define THREAD_ALIGN THREAD_SIZE #endif +#ifndef TASK_THREAD_SELF_POINTER +#define TASK_THREAD_SELF_POINTER(tsk) +#endif + #define THREADINFO_GFP (GFP_KERNEL_ACCOUNT | __GFP_ZERO) /* diff --git a/kernel/fork.c b/kernel/fork.c index 7ef3eb3..d53f5eb 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -901,6 +901,7 @@ static struct task_struct *dup_task_struct(struct task_struct *orig, int node) #endif setup_thread_stack(tsk, orig); + TASK_THREAD_SELF_POINTER(tsk); clear_user_return_notifier(tsk); clear_tsk_need_resched(tsk); set_task_stack_end_magic(tsk); From patchwork Thu Oct 8 07:15:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maninder Singh X-Patchwork-Id: 11822253 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org 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[182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 7F.9A.08745.6DCBE7F5; Thu, 8 Oct 2020 16:16:38 +0900 (KST) Received: from localhost.localdomain (unknown [107.109.224.135]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201008071635epsmtip1811c5c403afefee620d73e8ea180e363~78xxYtWLM1815718157epsmtip17; Thu, 8 Oct 2020 07:16:35 +0000 (GMT) From: Maninder Singh To: linux@armlinux.org.uk, ndesaulniers@google.com, caij2003@gmail.com, tglx@linutronix.de, bigeasy@linutronix.de, maz@kernel.org, valentin.schneider@arm.com, vincent.whitchurch@axis.com, nhuck@google.com, akpm@linux-foundation.org, 0x7f454c46@gmail.com, will@kernel.org Subject: [PATCH 2/3] arm: introduce IRQ stacks Date: Thu, 8 Oct 2020 12:45:32 +0530 Message-Id: <1602141333-17822-3-git-send-email-maninder1.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-Brightmail-Tracker: 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Singh , a.sahrawat@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds code for switching to IRQ stack. IRQ stack and Kernel SVC stack have below design. IRQ STACK:- ------------ IRQ stack top | | ------------ . . . . . . ------------ | sp | <- irq_stack_base + 0x8 ------------ | fp | <- irq_stack_base + 0x4 ------------ |tinfo_ptr | /* pointer to thread info */ irq_stack_ptr --> ------------ IRQ stack base Kernel SVC stack:- ------------ Kernel stack top | | ------------ . . . . . . ------------ | | | | ------------ |tinfo_ptr | /* pointer to thread info */ ------------ Kernel stack base Co-developed-by: Vaneet Narang Signed-off-by: Vaneet Narang Signed-off-by: Maninder Singh --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/irq.h | 6 ++++++ arch/arm/kernel/entry-armv.S | 41 +++++++++++++++++++++++++++++++++++++++- arch/arm/kernel/irq.c | 24 +++++++++++++++++++++++ 4 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 8512bdc..82ee6ee 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -212,6 +212,14 @@ #endif .endm + .macro this_cpu_ptr, sym, reg, tmp + ldr \reg, =\sym +#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6) + mrc p15, 0, \tmp, cr13, c0, 4 + add \reg, \reg, \tmp +#endif + .endm + /* * Increment/decrement the preempt count. */ diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 46d4114..f3299ab 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -22,10 +22,16 @@ #define NO_IRQ ((unsigned int)(-1)) #endif +#define IRQ_STACK_SIZE THREAD_SIZE + #ifndef __ASSEMBLY__ struct irqaction; struct pt_regs; +#ifdef CONFIG_IRQ_STACK +DECLARE_PER_CPU(unsigned long *, irq_stack_ptr); +#endif + extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 55a47df..13a5889 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -32,6 +32,43 @@ #include "entry-header.S" #include #include +#ifdef CONFIG_IRQ_STACK +#include +#endif + + .macro irq_stack_entry +#ifdef CONFIG_IRQ_STACK + mov r6, sp /* preserve sp */ + + this_cpu_ptr irq_stack_ptr, r7, r8 + ldr r7, [r7] + mov r8, r7 + + /* + * Compare sp with base of IRQ stack. + * if the top ~(#THREAD_SIZE_ORDER + PAGE_SHIFT) bits match, + * we are on a irq stack. + */ + eor r8, r8, sp + lsrs r8, #THREAD_SIZE_ORDER + PAGE_SHIFT + beq 9998f + + /* + * store thread info pointer on IRQ stack and + * switch to the irq stack. + */ + get_thread_info r8 + stm r7, {r8, fp, sp} + add sp, r7, #IRQ_STACK_SIZE +9998: +#endif + .endm + + .macro irq_stack_exit +#ifdef CONFIG_IRQ_STACK + mov sp, r6 /* restore sp */ +#endif + .endm /* * Interrupt handling. @@ -41,11 +78,13 @@ ldr r1, =handle_arch_irq mov r0, sp badr lr, 9997f + irq_stack_entry ldr pc, [r1] +9997: + irq_stack_exit #else arch_irq_handler_default #endif -9997: .endm .macro pabt_helper diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 698b6f6..79872e5 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -43,6 +43,15 @@ unsigned long irq_err_count; +#ifdef CONFIG_IRQ_STACK +DEFINE_PER_CPU(unsigned long *, irq_stack_ptr); + +/* + * irq_stack must be IRQ_STACK_SIZE(THREAD_SIZE) aligned, + */ +DEFINE_PER_CPU(unsigned long [IRQ_STACK_SIZE/sizeof(long)], irq_stack) __aligned(IRQ_STACK_SIZE); +#endif + int arch_show_interrupts(struct seq_file *p, int prec) { #ifdef CONFIG_FIQ @@ -55,6 +64,20 @@ int arch_show_interrupts(struct seq_file *p, int prec) return 0; } +#ifdef CONFIG_IRQ_STACK +static void init_irq_stacks(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu); +} +#else +static inline void init_irq_stacks(void) +{ +} +#endif + /* * handle_IRQ handles all hardware IRQ's. Decoded IRQs should * not come via this function. Instead, they should provide their @@ -79,6 +102,7 @@ void __init init_IRQ(void) { int ret; + init_irq_stacks(); if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) irqchip_init(); else From patchwork Thu Oct 8 07:15:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maninder Singh X-Patchwork-Id: 11822261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D2911580 for ; Thu, 8 Oct 2020 07:19:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC4A520739 for ; Thu, 8 Oct 2020 07:19:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FlbBPPo9"; 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Thu, 8 Oct 2020 07:16:40 +0000 (GMT) From: Maninder Singh To: linux@armlinux.org.uk, ndesaulniers@google.com, caij2003@gmail.com, tglx@linutronix.de, bigeasy@linutronix.de, maz@kernel.org, valentin.schneider@arm.com, vincent.whitchurch@axis.com, nhuck@google.com, akpm@linux-foundation.org, 0x7f454c46@gmail.com, will@kernel.org Subject: [PATCH 3/3] arm: Modify stack trace and dump for use with irq stack Date: Thu, 8 Oct 2020 12:45:33 +0530 Message-Id: <1602141333-17822-4-git-send-email-maninder1.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEKsWRmVeSWpSXmKPExsWy7bCmhq703rp4g7f3JS0mTHvBYnFxd6rF nPVr2CymXZzEbLFy3k5Gi02Pr7FaXN41h83i0NS9jBaH57exWOycc5LV4sOE/0wWmw9/YrHY vGkqs8Whk3MZLbbP/8lscX6bv0XLHVMHQY8189Ywely+dpHZ4/q6AI+ds+6yeyzYVOqxaVUn m8e7c+fYPU7M+M3isXlJvUffllWMHp83yQVwR3HZpKTmZJalFunbJXBl7Gt8w1yw2bBi+8aF LA2MKzW6GDk5JARMJA5uPsfWxcjFISSwm1FizZEpLBDOJ0aJ+a1rWSGcz4wSR/f9YYVp+X5y PRNEYhejxO/eU8wQzldGieUX/7OAVLEJ6Ems2rUHbJaIwBQmiXlfl4M5zAKLGCXmXOxnBKkS FvCRuPNnCRuIzSKgKvHh+DcmEJtXwF1i1bOHLBD75CRunusEWsHBwSngIfH3oybIHAmBPRwS t3p+MkHUuEi0TT4CZQtLvDq+hR3ClpL4/G4vG0RDM6PEp31rGSGcKYwSSy9+hPrIXuJ1cwMT yAZmAU2J9bv0IcKyElNPrQMbyizAJ9H7+wnUAl6JHfNgbFWJlpsboMZIS3z++JEFZIwE0KHn 7vJCgmU2o8TKvUvZJzDKzULYsICRcRWjZGpBcW56arFpgVFearlecWJucWleul5yfu4mRnCy 0vLawfjwwQe9Q4xMHIyHGCU4mJVEeNO9a+KFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8yr9OBMn JJCeWJKanZpakFoEk2Xi4JRqYCo3/mN5rdKZsU0udeXMoGX1p4p+eR8VX/N6okSSrbfA0qj3 S7ncVBVDjjv8UBS41bjjrefEGW8lMndbrb3/Na35+O68L5f7VvztC7xRsuVCFdPrK09ZneWm RymsE+mcEhHDmdGw4G56UdJUro1H/tzS1l7y4HnzEqEcm0z+XEvxY1kv2ppfm5lWfuh7dSt6 6dO0BHHZP8/X568PLKmKK5iU031b95BMYLLw/82nV4ouf5y95GTn3Cny87913Lo2ifOnY3LS gUPGR9gOfpPsVltcWvtQT3TW/gW+D5q/fbobdukU97kz/y0Szxe5z/93QqHFqnHn8xV7MoI+ PuvMO3WtVLDN/pEEa9nkvU22XUuUWIozEg21mIuKEwFFH7yWxQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWy7bCSnO7tPXXxBlMuG1tMmPaCxeLi7lSL OevXsFlMuziJ2WLlvJ2MFpseX2O1uLxrDpvFoal7GS0Oz29jsdg55ySrxYcJ/5ksNh/+xGKx edNUZotDJ+cyWmyf/5PZ4vw2f4uWO6YOgh5r5q1h9Lh87SKzx/V1AR47Z91l91iwqdRj06pO No93586xe5yY8ZvFY/OSeo++LasYPT5vkgvgjuKySUnNySxLLdK3S+DK2Nf4hrlgs2HF9o0L WRoYV2p0MXJySAiYSHw/uZ6pi5GLQ0hgB6PEpUermSES0hI//71ngbCFJVb+e84OUfSZUWLK zU6wBJuAnsSqXXtYQBIiAkuYJI5emswK4jALLGOUaP+7lhWkSljAR+LOnyVsIDaLgKrEh+Pf mEBsXgF3iVXPHkKtkJO4ea4TaDUHB6eAh8Tfj5ogYSGgkoldd1knMPItYGRYxSiZWlCcm55b bFhglJdarlecmFtcmpeul5yfu4kRHA1aWjsY96z6oHeIkYmD8RCjBAezkghvundNvBBvSmJl VWpRfnxRaU5q8SFGaQ4WJXHer7MWxgkJpCeWpGanphakFsFkmTg4pRqYEmwypnH7/qud8Eso 52LP/uo+Zvm5IqVvokXtTVe8XdYysbo78UVQ3AzVn5HLdd58qv/y5OhL26/vMq8WvxaWtFh7 fN0a+zilNvWozX9DjhWf95Blc3FkmjF584+oxUurUudrHrHXC4888dth6QSR3WuPO5/4KCIl b8S8ban/xs7eSWd5ryf/3rO3QcbQXV+qIkDlW/3p0laNrzkt31dOq0oR70gIlLnxdN/sO2fO Lpv7qEI2t6Ff4sO36YXtHkdM955PirmWkiIbX2I799/Cd8vKjb+/u3r70uVKaa65th+nrxPd liHn8NguynoN+9SHqRcC7q2IDngyeZL495Wt+09Xl+mldBzK6b63i835uhJLcUaioRZzUXEi ANKZDK71AgAA X-CMS-MailID: 20201008071644epcas5p1f5c220b5f58fd4251695af147325b7c4 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20201008071644epcas5p1f5c220b5f58fd4251695af147325b7c4 References: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_031756_212508_12BA7E52 X-CRM114-Status: GOOD ( 25.63 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [203.254.224.25 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: v.narang@samsung.com, Maninder Singh , a.sahrawat@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch allows unwind_frame() to traverse from interrupt stack to task stack correctly. A similar approach is taken to modify dump_backtrace_entry(), which expects to find struct pt_regs underneath any call to functions marked __exception. When on an irq_stack, the struct pt_regs is stored on the old task stack. c_backtrace() is also modified on same logic, when traversing from last IRQ frame, update fp with SVC mode fp. Co-developed-by: Vaneet Narang Signed-off-by: Vaneet Narang Signed-off-by: Maninder Singh --- arch/arm/include/asm/irq.h | 7 +++++++ arch/arm/kernel/stacktrace.c | 21 ++++++++++++++++++++ arch/arm/kernel/traps.c | 47 +++++++++++++++++++++++++++++++++++++++++--- arch/arm/lib/backtrace.S | 18 +++++++++++++++++ 4 files changed, 90 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index f3299ab..d4c66e9 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -30,6 +30,13 @@ #ifdef CONFIG_IRQ_STACK DECLARE_PER_CPU(unsigned long *, irq_stack_ptr); + +#define IRQ_STACK_BASE_PTR (unsigned long)(raw_cpu_read(irq_stack_ptr)) +#define IRQ_STACK_TOP_PTR (unsigned long)(raw_cpu_read(irq_stack_ptr) + IRQ_STACK_SIZE) + +#define IRQ_STACK_TO_TASK_FRAME(ptr) (*((unsigned long *)(ptr + 0x4))) +#define IRQ_STACK_TO_TASK_STACK(ptr) (*((unsigned long *)(ptr + 0x8))) + #endif extern void asm_do_IRQ(unsigned int, struct pt_regs *); diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 76ea417..65b9634 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -7,6 +7,9 @@ #include #include #include +#ifdef CONFIG_IRQ_STACK +#include +#endif #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) /* @@ -42,6 +45,13 @@ int notrace unwind_frame(struct stackframe *frame) { unsigned long high, low; unsigned long fp = frame->fp; +#ifdef CONFIG_IRQ_STACK + unsigned long irq_stack_base_p; + unsigned long irq_stack_p; + + irq_stack_base_p = IRQ_STACK_BASE_PTR; + irq_stack_p = irq_stack_base_p + IRQ_STACK_SIZE; +#endif /* only go to a higher address on the stack */ low = frame->sp; @@ -67,6 +77,17 @@ int notrace unwind_frame(struct stackframe *frame) frame->pc = *(unsigned long *)(fp - 4); #endif +#ifdef CONFIG_IRQ_STACK + /* + * Check whether we are going to walk through from interrupt stack + * to task stack. + * If we reach the end of the stack - and its an interrupt stack, + * read the original task stack pointer base + 4 of IRQ stack. + */ + if (frame->sp == irq_stack_p) + frame->sp = IRQ_STACK_TO_TASK_STACK(irq_stack_base_p); +#endif + return 0; } #endif diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 17d5a78..36b0cda 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -65,8 +65,20 @@ static int __init user_debug_setup(char *str) void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame, const char *loglvl) { - unsigned long end = frame + 4 + sizeof(struct pt_regs); + unsigned long end; +#ifdef CONFIG_IRQ_STACK + unsigned long irq_stack_base_p; + unsigned long irq_stack_p; + + irq_stack_base_p = IRQ_STACK_BASE_PTR; + irq_stack_p = irq_stack_base_p + IRQ_STACK_SIZE; + + if (frame < irq_stack_p && (frame + sizeof(struct pt_regs)) > irq_stack_p) + frame = IRQ_STACK_TO_TASK_STACK(irq_stack_base_p) - 4; +#endif + + end = frame + 4 + sizeof(struct pt_regs); #ifdef CONFIG_KALLSYMS printk("%s[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", loglvl, where, (void *)where, from, (void *)from); @@ -113,6 +125,35 @@ static int verify_stack(unsigned long sp) return 0; } + +#ifdef CONFIG_IRQ_STACK +static int fp_underflow(unsigned long fp, struct task_struct *tsk) +{ + unsigned long end = (unsigned long)end_of_stack(tsk); + unsigned long irq_stack_base_p; + unsigned long irq_stack_p; + + irq_stack_base_p = IRQ_STACK_BASE_PTR; + irq_stack_p = irq_stack_base_p + IRQ_STACK_SIZE; + + + if (fp > end && fp < end + THREAD_SIZE) + return 0; + + if (fp > irq_stack_base_p && fp < irq_stack_p) + return 0; + + return 1; +} +#else +static int fp_underflow(unsigned long fp, struct task_struct *tsk) +{ + if (fp < (unsigned long)end_of_stack(tsk)) + return 1; + + return 0; +} +#endif #endif /* @@ -238,7 +279,7 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk, } else if (verify_stack(fp)) { pr_cont("invalid frame pointer 0x%08x", fp); ok = 0; - } else if (fp < (unsigned long)end_of_stack(tsk)) + } else if (fp_underflow(fp, tsk)) pr_cont("frame pointer underflow"); pr_cont("\n"); @@ -292,7 +333,7 @@ static int __die(const char *str, int err, struct pt_regs *regs) if (!user_mode(regs) || in_interrupt()) { dump_mem(KERN_EMERG, "Stack: ", regs->ARM_sp, - THREAD_SIZE + (unsigned long)task_stack_page(tsk)); + THREAD_SIZE + (unsigned long)(regs->ARM_sp & ~(THREAD_SIZE - 1))); dump_backtrace(regs, tsk, KERN_EMERG); dump_instr(KERN_EMERG, regs); } diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S index 872f658..1a8e645 100644 --- a/arch/arm/lib/backtrace.S +++ b/arch/arm/lib/backtrace.S @@ -9,6 +9,9 @@ #include #include #include +#ifdef CONFIG_IRQ_STACK +#include +#endif .text @ fp is 0 or stack frame @@ -96,6 +99,21 @@ for_each_frame: tst frame, mask @ Check for address exceptions teq sv_fp, #0 @ zero saved fp means beq no_frame @ no further frames +#ifdef CONFIG_IRQ_STACK + /* + * check if it is swtiching from IRQ to SVC, + * then update frame accordingly. + */ + this_cpu_ptr irq_stack_ptr r2 r3 + ldr r3, [r2] + add r2, r3, #IRQ_STACK_SIZE + ldr r0, [frame, #-8] + cmp r2, r0 + ldreq sv_fp, [r3, #4] + moveq frame, sv_fp + beq for_each_frame +#endif + cmp sv_fp, frame @ next frame must be mov frame, sv_fp @ above the current frame bhi for_each_frame