From patchwork Tue Oct 13 23:01:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBE53921 for ; Tue, 13 Oct 2020 22:58:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3D9B20B1F for ; Tue, 13 Oct 2020 22:58:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3D9B20B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D1A66E13A; Tue, 13 Oct 2020 22:58:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0166D6E13A for ; Tue, 13 Oct 2020 22:58:02 +0000 (UTC) IronPort-SDR: dQlpx1tZPyBomFIRCZxswzrUnGGf0xEDox/8Dsm/sfdHU5BjdDPo4HASBrYYXiaNxPFpkfNyxj TyOb0E5+hPrA== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315610" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315610" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: egybVm0Qs1mspSaZy3NsCnVdiyDHVZPST36DEysO4Tu8KCqJl3MgA80vpYnWm5w8JZByGt2WSX bFEyQ6d/VOAQ== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976707" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:01 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:16 -0700 Message-Id: <20201013230121.331595-1-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/display/psr: Calculate selective fetch plane registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the calculations to set plane selective fetch registers depending in the value of the area damaged. It is still using the whole plane area as damaged but that will change in next patches. BSpec: 55229 Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- .../drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_psr.c | 22 ++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0b5df8e44966..aeceb378bca3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -603,6 +603,8 @@ struct intel_plane_state { u32 planar_slave; struct drm_intel_sprite_colorkey ckey; + + struct drm_rect psr2_sel_fetch_area; }; struct intel_initial_plane_config { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a591a475f148..773a5b5fa078 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1173,6 +1173,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, { struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; + const struct drm_rect *clip; u32 val; if (!crtc_state->enable_psr2_sel_fetch) @@ -1184,16 +1185,20 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, if (!val || plane->id == PLANE_CURSOR) return; - val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1; + clip = &plane_state->psr2_sel_fetch_area; + + val = (clip->y1 + plane_state->uapi.dst.y1) << 16; + val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - val = plane_state->color_plane[color_plane].y << 16; + /* TODO: consider tiling and auxiliary surfaces */ + val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; val |= plane_state->color_plane[color_plane].x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); /* Sizes are 0 based */ - val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16; + val = (drm_rect_height(clip) - 1) << 16; val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); } @@ -1267,7 +1272,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { - struct drm_rect temp; + struct drm_rect *sel_fetch_area, temp; if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) continue; @@ -1290,8 +1295,13 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, * For now doing a selective fetch in the whole plane area, * optimizations will come in the future. */ - temp.y1 = new_plane_state->uapi.dst.y1; - temp.y2 = new_plane_state->uapi.dst.y2; + sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16; + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16; + + temp = *sel_fetch_area; + temp.y1 += new_plane_state->uapi.dst.y1 >> 16; + temp.y2 += new_plane_state->uapi.dst.y1 >> 16; clip_area_update(&pipe_clip, &temp); } From patchwork Tue Oct 13 23:01:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836147 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50053921 for ; Tue, 13 Oct 2020 22:58:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2ED1320B1F for ; Tue, 13 Oct 2020 22:58:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2ED1320B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72AE26E150; Tue, 13 Oct 2020 22:58:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 266D96E150 for ; Tue, 13 Oct 2020 22:58:03 +0000 (UTC) IronPort-SDR: 4n36cEFky8eBpTvXmdqWKAMYhkjnGGoPiIePgCnYV7i2gdJEhq2zqJ8QF5GGfjOhW7I7Nv1Qgn +R3IwUWFn0Gw== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315611" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315611" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: eLhdBoPP0q/uNeKFgFUP1pP2KKh+sfGIBjRKNaVsxFW+z9Jgta1TpkdL6CSyUiFXddMpWGhSIL Iakt1TEx3GKQ== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976709" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:01 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:17 -0700 Message-Id: <20201013230121.331595-2-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013230121.331595-1-jose.souza@intel.com> References: <20201013230121.331595-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/display/psr: Use plane damage clips to calculate damaged area X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now using plane damage clips property to calcualte the damaged area. Selective fetch only supports one region to be fetched so software needs to calculate a bounding box around all damage clips. Cc: Ville Syrjälä Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++++++++++++++++--- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 773a5b5fa078..0f1e9f0fa57f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1273,6 +1273,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { struct drm_rect *sel_fetch_area, temp; + struct drm_mode_rect *damaged_clips; + u32 num_clips; + int j; if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) continue; @@ -1291,13 +1294,54 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (!new_plane_state->uapi.visible) continue; + sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; + sel_fetch_area->y1 = -1; + + damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi); + num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); + /* - * For now doing a selective fetch in the whole plane area, - * optimizations will come in the future. + * If plane moved, mark the whole plane area as damaged as it + * needs to be complete redraw in the new position. */ - sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; - sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16; - sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16; + if (!drm_rect_equals(&new_plane_state->uapi.dst, + &old_plane_state->uapi.dst)) { + num_clips = 0; + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16; + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16; + } else if (!num_clips && new_plane_state->uapi.fb != + old_plane_state->uapi.fb) { + /* + * If the plane don't have damage areas but the + * framebuffer changed, mark the whole plane area as + * damaged. + */ + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16; + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16; + } + + for (j = 0; j < num_clips; j++) { + struct drm_rect damage_area; + + damage_area.y1 = damaged_clips[j].y1; + damage_area.y2 = damaged_clips[j].y2; + clip_area_update(sel_fetch_area, &damage_area); + } + + /* + * No page flip, no plane moviment or no damage areas, so don't + * fetch any pixel from memory for this plane + */ + if (sel_fetch_area->y1 == -1) { + sel_fetch_area->y1 = 0; + sel_fetch_area->y2 = 0; + } + + /* Don't need to redraw plane damaged areas outside of screen */ + j = sel_fetch_area->y2 + (new_plane_state->uapi.dst.y1 >> 16); + j = crtc_state->uapi.adjusted_mode.crtc_vdisplay - j; + if (j < 0) + sel_fetch_area->y2 += j; temp = *sel_fetch_area; temp.y1 += new_plane_state->uapi.dst.y1 >> 16; From patchwork Tue Oct 13 23:01:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9AD32921 for ; Tue, 13 Oct 2020 22:58:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 794A320B1F for ; Tue, 13 Oct 2020 22:58:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 794A320B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C259E6E97F; Tue, 13 Oct 2020 22:58:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B6B26E13A for ; Tue, 13 Oct 2020 22:58:03 +0000 (UTC) IronPort-SDR: XNezwT458FjWbZgE7LVuqwOngOD6SreWNm+y+2d/SjV5IVgv/jznNTKxuy9cslUA7I88hyFqii S6VomXWwKkjQ== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315612" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315612" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: RD+NahmNb6+Yi4fe1coVKaN1Ki/YCvvrYyA22GWhs8K+wToidl32CDTTpcdvnOaot8KY1dMzCD Xgp9+B33yZkw== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976712" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:01 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:18 -0700 Message-Id: <20201013230121.331595-3-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013230121.331595-1-jose.souza@intel.com> References: <20201013230121.331595-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/display/psr: Consider other planes to damaged area calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Planes can individually have transparent, move or have visibility changed if any of those happens, planes bellow it will be visible or have more pixels of it visible than before. This patch is taking care of this case for selective fetch by adding to each plane damaged area all the intersections of planes above it that matches with the characteristics described above. There still some room from improvements here but at least this initial version will take care of display what is expected saving some memory reads. Cc: Ville Syrjälä Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0f1e9f0fa57f..91ba97bf609b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1253,11 +1253,38 @@ static void clip_area_update(struct drm_rect *overlap_damage_area, overlap_damage_area->y2 = damage_area->y2; } +/* Update plane damage area if planes above moved or have alpha */ +static void pipe_dirty_areas_set(struct intel_plane_state *plane_state, + struct intel_plane *plane, + const struct drm_rect *pipe_dirty_areas, + struct drm_rect *sel_fetch_area) +{ + enum plane_id i; + + for (i = PLANE_CURSOR; i > plane->id; i--) { + int j; + + for (j = 0; j < 2; j++) { + struct drm_rect r = pipe_dirty_areas[i * 2 + j]; + + if (!drm_rect_width(&r)) + continue; + if (!drm_rect_intersect(&r, &plane_state->uapi.dst)) + continue; + + r.y1 -= plane_state->uapi.dst.y1; + r.y2 -= plane_state->uapi.dst.y1; + clip_area_update(sel_fetch_area, &r); + } + } +} + int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_plane_state *new_plane_state, *old_plane_state; + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = {}; struct drm_rect pipe_clip = { .y1 = -1 }; struct intel_plane *plane; bool full_update = false; @@ -1270,6 +1297,38 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (ret) return ret; + /* + * Mark all the areas where there is a plane that matches one of this: + * - transparent + * - moved + * - visibility changed + * In all those cases, planes bellow it will need to be redraw. + */ + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, + new_plane_state, i) { + bool alpha, flip, dirty; + + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) + continue; + + alpha = new_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE; + alpha |= old_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE; + flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb; + dirty = alpha && flip; + + dirty |= !drm_rect_equals(&new_plane_state->uapi.dst, + &old_plane_state->uapi.dst); + dirty |= new_plane_state->uapi.visible != + old_plane_state->uapi.visible; + if (!dirty) + continue; + + if (old_plane_state->uapi.visible) + pipe_dirty_areas[plane->id * 2] = old_plane_state->uapi.dst; + if (new_plane_state->uapi.visible) + pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst; + } + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { struct drm_rect *sel_fetch_area, temp; @@ -1337,6 +1396,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, sel_fetch_area->y2 = 0; } + pipe_dirty_areas_set(new_plane_state, plane, pipe_dirty_areas, + sel_fetch_area); + /* Don't need to redraw plane damaged areas outside of screen */ j = sel_fetch_area->y2 + (new_plane_state->uapi.dst.y1 >> 16); j = crtc_state->uapi.adjusted_mode.crtc_vdisplay - j; From patchwork Tue Oct 13 23:01:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E64B5921 for ; Tue, 13 Oct 2020 22:58:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C169820B1F for ; Tue, 13 Oct 2020 22:58:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C169820B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 16B316E8D2; Tue, 13 Oct 2020 22:58:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 708336E150 for ; Tue, 13 Oct 2020 22:58:03 +0000 (UTC) IronPort-SDR: wEjRBolXm53fzxIdZssft9cR0OVr+U3s8eS2r5VpWmnsbT+ujdMDSezsCYtbviazV2KNviACF4 6xQX+Vjpybtg== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315613" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315613" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: GX6m/2MYBMK1aQUnnrFCRtoquCRlwR0d0zwZcrf5BsanIvKyPsfwYnjU7+vlIyzbKJHN+xwrzW yujfuTOaF4VA== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976715" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:19 -0700 Message-Id: <20201013230121.331595-4-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013230121.331595-1-jose.souza@intel.com> References: <20201013230121.331595-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The calculation the offsets of the main surface will be needed by PSR2 selective fetch code so here splitting and exporting it. No functional changes were done here. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 95 ++++++++++++-------- drivers/gpu/drm/i915/display/intel_display.h | 2 + 2 files changed, 59 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cf1417ff54d7..64242ecb8610 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3889,6 +3889,56 @@ intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) return y; } +int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, + int *x, int *y, u32 *offset) +{ + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + const int aux_plane = intel_main_to_aux_plane(fb, 0); + const u32 aux_offset = plane_state->color_plane[aux_plane].offset; + const u32 alignment = intel_surf_alignment(fb, 0); + const int w = drm_rect_width(&plane_state->uapi.src) >> 16; + + intel_add_fb_offsets(x, y, plane_state, 0); + *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); + if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) + return -EINVAL; + + /* + * AUX surface offset is specified as the distance from the + * main surface offset, and it must be non-negative. Make + * sure that is what we will get. + */ + if (aux_plane && *offset > aux_offset) + *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, + *offset, + aux_offset & ~(alignment - 1)); + + /* + * When using an X-tiled surface, the plane blows up + * if the x offset + width exceed the stride. + * + * TODO: linear and Y-tiled seem fine, Yf untested, + */ + if (fb->modifier == I915_FORMAT_MOD_X_TILED) { + int cpp = fb->format->cpp[0]; + + while ((*x + w) * cpp > plane_state->color_plane[0].stride) { + if (*offset == 0) { + drm_dbg_kms(&dev_priv->drm, + "Unable to find suitable display surface offset due to X-tiling\n"); + return -EINVAL; + } + + *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, + *offset, + *offset - alignment); + } + } + + return 0; +} + static int skl_check_main_surface(struct intel_plane_state *plane_state) { struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); @@ -3899,9 +3949,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int w = drm_rect_width(&plane_state->uapi.src) >> 16; int h = drm_rect_height(&plane_state->uapi.src) >> 16; int max_width, min_width, max_height; - u32 alignment, offset; - int aux_plane = intel_main_to_aux_plane(fb, 0); - u32 aux_offset = plane_state->color_plane[aux_plane].offset; + const int aux_plane = intel_main_to_aux_plane(fb, 0); + const u32 alignment = intel_surf_alignment(fb, 0); + u32 offset; + int ret; if (INTEL_GEN(dev_priv) >= 11) { max_width = icl_max_plane_width(fb, 0, rotation); @@ -3926,41 +3977,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) return -EINVAL; } - intel_add_fb_offsets(&x, &y, plane_state, 0); - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); - alignment = intel_surf_alignment(fb, 0); - if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) - return -EINVAL; - - /* - * AUX surface offset is specified as the distance from the - * main surface offset, and it must be non-negative. Make - * sure that is what we will get. - */ - if (aux_plane && offset > aux_offset) - offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, - offset, aux_offset & ~(alignment - 1)); - - /* - * When using an X-tiled surface, the plane blows up - * if the x offset + width exceed the stride. - * - * TODO: linear and Y-tiled seem fine, Yf untested, - */ - if (fb->modifier == I915_FORMAT_MOD_X_TILED) { - int cpp = fb->format->cpp[0]; - - while ((x + w) * cpp > plane_state->color_plane[0].stride) { - if (offset == 0) { - drm_dbg_kms(&dev_priv->drm, - "Unable to find suitable display surface offset due to X-tiling\n"); - return -EINVAL; - } - - offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, - offset, offset - alignment); - } - } + ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); + if (ret) + return ret; /* * CCS AUX surface doesn't have its own x/y offsets, we must make sure diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index d10b7c8cde3f..4be68b5be149 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -609,6 +609,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); u32 skl_plane_stride(const struct intel_plane_state *plane_state, int plane); int skl_check_plane_surface(struct intel_plane_state *plane_state); +int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, + int *x, int *y, u32 *offset); int i9xx_check_plane_surface(struct intel_plane_state *plane_state); int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); unsigned int i9xx_plane_max_stride(struct intel_plane *plane, From patchwork Tue Oct 13 23:01:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDAA014B5 for ; Tue, 13 Oct 2020 22:58:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC76920B1F for ; Tue, 13 Oct 2020 22:58:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC76920B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 834BE6E980; Tue, 13 Oct 2020 22:58:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C3FE6E13A for ; Tue, 13 Oct 2020 22:58:03 +0000 (UTC) IronPort-SDR: rHZX94sHniLqjhpG3qMlINQR6SNf2MB9qtz7WWX4dhf7P/JJWGJqjctVDcPp+0cXuZmQZrv2cQ MQTIitr+lOqw== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315614" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315614" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: 1CeH4i0djI0/NSrNtq7tGARb413W6OXxWBIzwlukA8sJRR0IDgm64k6SogaMKKtSN0lTJT9KEG C4IswZ6MSrhQ== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976718" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:20 -0700 Message-Id: <20201013230121.331595-5-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013230121.331595-1-jose.souza@intel.com> References: <20201013230121.331595-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Do the calculation of x and y offsets using skl_calc_main_surface_offset(). RFC/WIP: This causes the value of the calculated x to be different than plane_state->color_plane[color_plane].x, not sure if that is expected. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 91ba97bf609b..c30d7069cbaa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1174,7 +1174,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1191,9 +1192,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); + if (ret) + drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); From patchwork Tue Oct 13 23:01:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11836151 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7A1C14B5 for ; Tue, 13 Oct 2020 22:58:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB2CC20B1F for ; Tue, 13 Oct 2020 22:58:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB2CC20B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BE426E97D; Tue, 13 Oct 2020 22:58:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B0BBD6E150 for ; Tue, 13 Oct 2020 22:58:03 +0000 (UTC) IronPort-SDR: 2FWnS78QKFxecopl5cv38q19G38SdAp8IikIxcHUI5AUa3clgUkUnKOIUp4BuyapCrrjU3HryD zKgCPSjSnwrQ== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="145315615" X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="145315615" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 IronPort-SDR: yyKN9TulMgBOu5bKnGl8PrlXEGQr1fiJh0T1WYtLOHMwZtu9q04a8f4ecCiLriDd77WdI0MMqt 8p9fBpq6I/yw== X-IronPort-AV: E=Sophos;i="5.77,372,1596524400"; d="scan'208";a="313976720" Received: from josouza-mobl2.jf.intel.com (HELO josouza-MOBL2.intel.com) ([10.24.14.55]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 15:58:02 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Oct 2020 16:01:21 -0700 Message-Id: <20201013230121.331595-6-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013230121.331595-1-jose.souza@intel.com> References: <20201013230121.331595-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] DEBUG: drm/i915/display: Add debug information to selective fetch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Just for feature development, not needed in production. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c30d7069cbaa..1b2ae3bd02ee 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1194,11 +1194,19 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, /* TODO: consider auxiliary surfaces */ x = plane_state->uapi.src.x1 >> 16; - y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + y = plane_state->uapi.src.y1 >> 16; + drm_info(&dev_priv->drm, "plane%c src.x=%i src.y=%i clip.y1=%i clip.y2=%i\n", + plane_name(plane->id), x, y, clip->y1, clip->y2); + drm_info(&dev_priv->drm, "\tcolor_plane[color_plane].x=%i color_plane[color_plane].y=%i\n", + plane_state->color_plane[color_plane].x, + plane_state->color_plane[color_plane].y); + + y += clip->y1; ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); if (ret) drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", ret); + drm_info(&dev_priv->drm, "\tcalculated offset x=%i y=%i\n", x, y); val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); @@ -1335,6 +1343,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst; } + drm_info(state->base.dev, "intel_psr2_sel_fetch_update()\n"); + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { struct drm_rect *sel_fetch_area, temp; @@ -1411,6 +1421,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (j < 0) sel_fetch_area->y2 += j; + drm_info(state->base.dev, "\tplane%c y1=%i y2=%i dst.y1=%i dst.y2=%i\n", + plane_name(plane->id), sel_fetch_area->y1, + sel_fetch_area->y2, new_plane_state->uapi.dst.y1, + new_plane_state->uapi.dst.y2); + temp = *sel_fetch_area; temp.y1 += new_plane_state->uapi.dst.y1 >> 16; temp.y2 += new_plane_state->uapi.dst.y1 >> 16;