From patchwork Wed Oct 14 12:54:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 11837621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E37EE921 for ; Wed, 14 Oct 2020 12:55:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B69EF20BED for ; Wed, 14 Oct 2020 12:55:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="XMafx1fC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730896AbgJNMzZ (ORCPT ); Wed, 14 Oct 2020 08:55:25 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:13728 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727061AbgJNMzY (ORCPT ); Wed, 14 Oct 2020 08:55:24 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09ECqGFX019487; Wed, 14 Oct 2020 14:55:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=wsGIXxxHRanfrzSuhl2i4VZtSbpz2LNavXq5QOc27fo=; b=XMafx1fCh/LCI+G/GPKaGeSoW7q4ya49n0wz9AtINmtM65dXH1D0RsORKd+JTU/cII64 pGtpkYi804pNG8fhPyJp9fF+XgDt/wSqTBSJLjsVqYMqByulcODjdnXiq7FT6eIvzJqv p3CwPYzaLtk9HSARMy22OGfettC+Wf4lBDMreHEsUUTeIAMWEPNGdd7N8XPboJzYLF8r g9DA6rlQee5dY1R8PRZBurV6tdObOdjZ/QmUaatmtdQ0qRjwJU6/zAZ1Jwd+I42hvy22 ks9PvUCTnexJitqgjFYFZXcGwoo0KZFSo2fhcCID8bvdeFRL68WAG88O8YScY+UG7AcM 6w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 34353wef26-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Oct 2020 14:55:11 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C858510002A; Wed, 14 Oct 2020 14:55:10 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B90172DA52A; Wed, 14 Oct 2020 14:55:10 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 14 Oct 2020 14:55:10 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson , Ahmad Fatoum Subject: [PATCH v2 1/4] dt-bindings: arm: stm32: Add compatible for syscon tamp node Date: Wed, 14 Oct 2020 14:54:38 +0200 Message-ID: <20201014125441.2457-2-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201014125441.2457-1-arnaud.pouliquen@st.com> References: <20201014125441.2457-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-10-14_07:2020-10-14,2020-10-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32 SoC to support TAMP registers access. Signed-off-by: Arnaud Pouliquen Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f1cd0103c74..6634b3e0853e 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -19,6 +19,7 @@ properties: - st,stm32mp151-pwr-mcu - st,stm32-syscfg - st,stm32-power-config + - st,stm32-tamp - const: syscon reg: From patchwork Wed Oct 14 12:54:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 11837619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54E5A15E6 for ; Wed, 14 Oct 2020 12:55:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A36622242 for ; Wed, 14 Oct 2020 12:55:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="FADOcfjh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729886AbgJNMzZ (ORCPT ); Wed, 14 Oct 2020 08:55:25 -0400 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:56100 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729267AbgJNMzY (ORCPT ); Wed, 14 Oct 2020 08:55:24 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09ECr9no003174; Wed, 14 Oct 2020 14:55:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=jPr7oz6V/C/0BCEXLC3ve38DWAGIvboOAC9KbnxfjRg=; b=FADOcfjh94aoXJOAUwU11FS9n2wTKyglNEX1KyRCI6gxkZOAUInXdcIxhR+xUoYOnH/k dCKuZwwTkBbRsbPGlzWb0bgMkMsrBn5PcX4VWtbLYHilekkHdOkewdSGBw7gDyYobXdD ctgOgS0SqyOrkUazbpjbM7ThiZzvF43Ys3wp1x9XKNo7axj8iY90N7taDJWh9NeqBvP/ GmSS2VNxrB/GwVGDqkSehm/ZxoAApFqcNoIuRInAqAc4ZC9tfUS7UrPQM19f2wrvRmj6 C1IrfwwxxirRfV/K2Y9mqPCPXjYwoRgISZJLatfv5cbe+zBTfzI+LUU0q1q/whWN2tPp 6Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 34356edsr4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Oct 2020 14:55:13 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E092810002A; Wed, 14 Oct 2020 14:55:11 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D1AC82DA52A; Wed, 14 Oct 2020 14:55:11 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 14 Oct 2020 14:55:11 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson , Ahmad Fatoum Subject: [PATCH v2 2/4] dt-bindings: remoteproc: stm32_rproc: update for firmware synchronization Date: Wed, 14 Oct 2020 14:54:39 +0200 Message-ID: <20201014125441.2457-3-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201014125441.2457-1-arnaud.pouliquen@st.com> References: <20201014125441.2457-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-10-14_07:2020-10-14,2020-10-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add new properties description used to attach to a pre-loaded firmware according to the commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation") which updates the driver part. Signed-off-by: Arnaud Pouliquen Reviewed-by: Rob Herring --- .../bindings/remoteproc/st,stm32-rproc.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 4ffa25268fcc..3207942d51bf 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -96,6 +96,19 @@ properties: 3rd cell: register bitmask for the deep sleep bit maxItems: 1 + st,syscfg-m4-state: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: | + Reference to the tamp register which exposes the Cortex-M4 state. + maxItems: 1 + + st,syscfg-rsc-tbl: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: | + Reference to the tamp register which references the Cortex-M4 + resource table address. + maxItems: 1 + st,auto-boot: $ref: /schemas/types.yaml#/definitions/flag description: @@ -122,6 +135,8 @@ examples: resets = <&rcc MCU_R>; st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; }; ... From patchwork Wed Oct 14 12:54:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 11837617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0178921 for ; Wed, 14 Oct 2020 12:55:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C19472173E for ; Wed, 14 Oct 2020 12:55:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="O0zGMkYj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729267AbgJNMza (ORCPT ); Wed, 14 Oct 2020 08:55:30 -0400 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:56419 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729912AbgJNMz0 (ORCPT ); Wed, 14 Oct 2020 08:55:26 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09ECrFHb008363; Wed, 14 Oct 2020 14:55:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=owCUp3ap2EbMKfAx/xEipaA99wmq/HRTHA1XL0MNvMw=; b=O0zGMkYjrp+snAThNA0jh9W+T3GPMxy6pvDN7c95YYNoBRzLoDpvz/CuF4r+luK3KWCR ikz3P22WMC7yDMKvkMYz7syj+C5i6DQ0bHyaOTTKyy1Bhj9JK6angLLj5O34YWzs9+NA EP9uIq4pSwk79dbjhFmz964BENdWIgAfsJX5oYfKTu32hoLnpTTwGXzSHTZlCO1iPaSn tHBEWzmADnLb+bvNLmM/vj/uLV8T61Qyp2Ra5MnuNs+yfU5Mwdf0gXWxR6FMsLXsKYOR B64VTURmSa8p7veUXDdvR9lUz3BVqFnLk+6Jbhv+omImwsmSTcm+4nQciEEIa9VGG2ij 7Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3435875uxk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Oct 2020 14:55:14 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 09872100034; Wed, 14 Oct 2020 14:55:13 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EEED12DA52A; Wed, 14 Oct 2020 14:55:12 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 14 Oct 2020 14:55:12 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson , Ahmad Fatoum Subject: [PATCH v2 3/4] dt-bindings: remoteproc: stm32_rproc: update syscon descriptions Date: Wed, 14 Oct 2020 14:54:40 +0200 Message-ID: <20201014125441.2457-4-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201014125441.2457-1-arnaud.pouliquen@st.com> References: <20201014125441.2457-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-10-14_07:2020-10-14,2020-10-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Align other syscon descriptions with st,syscfg-m4-state and st,syscfg-rsc-tbl descriptions by suppressing the cells description. Signed-off-by: Arnaud Pouliquen Acked-by: Rob Herring --- .../devicetree/bindings/remoteproc/st,stm32-rproc.yaml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index 3207942d51bf..a1171dfba024 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -38,9 +38,6 @@ properties: st,syscfg-tz: description: Reference to the system configuration which holds the RCC trust zone mode - - Phandle of syscon block. - - The offset of the RCC trust zone mode register. - - The field mask of the RCC trust zone mode. $ref: "/schemas/types.yaml#/definitions/phandle-array" maxItems: 1 @@ -91,9 +88,6 @@ properties: $ref: "/schemas/types.yaml#/definitions/phandle-array" description: | Reference to the system configuration which holds the remote - 1st cell: phandle to syscon block - 2nd cell: register offset containing the deep sleep setting - 3rd cell: register bitmask for the deep sleep bit maxItems: 1 st,syscfg-m4-state: From patchwork Wed Oct 14 12:54:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 11837615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 019D914B4 for ; Wed, 14 Oct 2020 12:55:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBC08208B3 for ; Wed, 14 Oct 2020 12:55:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="KzTLNfTx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730065AbgJNMzY (ORCPT ); Wed, 14 Oct 2020 08:55:24 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:41388 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729886AbgJNMzY (ORCPT ); Wed, 14 Oct 2020 08:55:24 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09ECqtv0015297; Wed, 14 Oct 2020 14:55:14 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=9bTCitwnBAltRZQ7gOYLHIo8QHxlqk1VrxB1btIyl3k=; b=KzTLNfTxLA+SdECp61CYy4zvOHuw/EYembLjHrSng9UqSuZRY/IbUv/f5q5k9nhJGcgo lMe3N7vYUHM1hC3QjFxmQUFbMxgyYf7dhwJBiEUJpRH/GxmtM7+CH+vcKDnhNsZ/zpHI 407uxuP/xWF1a+1n8u+K7E18TnGwv041b6obfQowhUWG6rAFfDFG4F3gIqGGOaJFK9Ge Rj4lLT81qC8MndoDsw0VrJzf3exPDLM6ZpDaV9M50VPqP/PPINCOxZUWpzgtY9XO8Gwo GjfiFb0p4JJSAuJI4xVixQ2LwwwT0TUZoEZ3B46yQ7veLlXYsRhYTjODZtO8Xw3cP31U Sg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3455c8hqrm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Oct 2020 14:55:14 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6536810002A; Wed, 14 Oct 2020 14:55:14 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 55D6F2DA52D; Wed, 14 Oct 2020 14:55:14 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 14 Oct 2020 14:55:13 +0200 From: Arnaud Pouliquen To: Rob Herring , Alexandre Torgue CC: , , , , , Arnaud Pouliquen , Mathieu Poirier , Ohad Ben-Cohen , Bjorn Andersson , Ahmad Fatoum Subject: [PATCH v2 4/4] ARM: dts: stm32: update stm32mp151 for remote proc synchronization support Date: Wed, 14 Oct 2020 14:54:41 +0200 Message-ID: <20201014125441.2457-5-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201014125441.2457-1-arnaud.pouliquen@st.com> References: <20201014125441.2457-1-arnaud.pouliquen@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-10-14_07:2020-10-14,2020-10-14 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Two backup registers are used to store the Cortex-M4 state and the resource table address. Declare the tamp node and add associated properties in m4_rproc node to allow Linux to attach to a firmware loaded by the first boot stages. Associated driver implementation is available in commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation"). Signed-off-by: Arnaud Pouliquen Tested-by: Mathieu Poirier --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bfe29023fbd5..842ecffae73a 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1541,6 +1541,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1717,6 +1722,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; };