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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id l11sm8472829wro.89.2020.10.17.07.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:02:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/44] util/cutils: Introduce freq_to_str() to display Hertz units Date: Sat, 17 Oct 2020 16:02:00 +0200 Message-Id: <20201017140243.1078718-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luc Michel , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Alistair Francis , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce freq_to_str() to convert frequency values in human friendly units using the SI units for Hertz. Suggested-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-Id: <20201012095804.3335117-2-f4bug@amsat.org> --- include/qemu/cutils.h | 12 ++++++++++++ util/cutils.c | 14 ++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h index 3a86ec0321e..4bbf4834ea5 100644 --- a/include/qemu/cutils.h +++ b/include/qemu/cutils.h @@ -158,6 +158,18 @@ int qemu_strtosz_metric(const char *nptr, const char **end, uint64_t *result); char *size_to_str(uint64_t val); +/** + * freq_to_str: + * @freq_hz: frequency to stringify + * + * Return human readable string for frequency @freq_hz. + * Use SI units like KHz, MHz, and so forth. + * + * The caller is responsible for releasing the value returned + * with g_free() after use. + */ +char *freq_to_str(uint64_t freq_hz); + /* used to print char* safely */ #define STR_OR_NULL(str) ((str) ? (str) : "null") diff --git a/util/cutils.c b/util/cutils.c index 8da34e04b0b..be4e43a9eff 100644 --- a/util/cutils.c +++ b/util/cutils.c @@ -885,6 +885,20 @@ char *size_to_str(uint64_t val) return g_strdup_printf("%0.3g %sB", (double)val / div, suffixes[i]); } +char *freq_to_str(uint64_t freq_hz) +{ + static const char *const suffixes[] = { "", "K", "M", "G", "T", "P", "E" }; + double freq = freq_hz; + size_t idx = 0; + + while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { + freq /= 1000.0; + idx++; + } + + return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); +} + int qemu_pstrcmp0(const char **str1, const char **str2) { return g_strcmp0(*str1, *str2); From patchwork Sat Oct 17 14:02:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDD3C14B5 for ; Sat, 17 Oct 2020 14:04:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 807742072C for ; Sat, 17 Oct 2020 14:04:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MwhIzd9v" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 807742072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmpL-0003FZ-JB for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:04:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmnV-0001UH-Bi for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:01 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:55019) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmnT-0003gN-6D for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:00 -0400 Received: by mail-wm1-x341.google.com with SMTP id p15so6120999wmi.4 for ; Sat, 17 Oct 2020 07:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ckhgHIzetD2FmHEm0FTTUKRnqskZdYevul/a5BWHNys=; b=MwhIzd9vmKrNrMQcJ4xyTdGkBMDODFCRnuLvsNjbU1/TLj/fr3P0cRjdLTbxkg2QZ0 zETo7T9j/B1RF2DjsFcKSrwoBiYKBpndj9Hn6/J7H9EAwAIPQTO7Ktbb2vaV+G+V00mw ZmmYucRGaXnM6gNFVskqJe/1esoAxkBSjB2nYA0xMsNB2G6CgYVrK5UnZhN1ujab7m+p bB4acVFxaKLLW+27yBHQnnd7cnJq4vl5WJi/3dQ2pMB9aGT6mOlpctjlecWYH7+PFJuv SXsnDXTYSG4QA5CYK7S+7DjWs7Qo5YI9j56liOq1B8uWB1qMK9g9Hoa/foiOFK7C0Bdc WnQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ckhgHIzetD2FmHEm0FTTUKRnqskZdYevul/a5BWHNys=; b=TJlfgGisyYZe9r48Ez5aMZ5KlweKwI2oaxGMI+rXVx0Bm3dnJWOe3MJAm5uJID4y+T XtZGp2GcUwE+R2l8JIDfZCAUqgIKfhJ9dkkFtHoC645KMd2Xu8q1y8RNplaZ2TSViTFU PLfSfDINd+3Tq+WjHjAWA9RNwF2nSqM0v1vCat3UWChmCY0hpaMqRjDbgYwPEx6kDCfC M0gCBVDkwdV9LpDeQXvLoe2VV3ln0JsX2uw1c6eEfRnkTOv5CFtx84q13P/yXMrfkKin g8cwZM5c0/7iGwz4lNrauvl8F6JBx5cXWG/qijk6iAqwVzCt3cDtmhs6eA/MWMEDrwgK QN4Q== X-Gm-Message-State: AOAM531YQ3FQ2c9l/uSHEh5oHrmKuBb5K9L6taXgYk6X957gXk45ncJ7 OjGUz0bQqOFjLFK6Wi9bZ92hw104kr4= X-Google-Smtp-Source: ABdhPJw8G3qQpcBEOQOl2n1jsv9b14X+nabi32lR8Ou+QXQn4MMlOoWQ6dDih6K8nK2W55im4NDSkw== X-Received: by 2002:a7b:c4cb:: with SMTP id g11mr8707586wmk.88.1602943375100; Sat, 17 Oct 2020 07:02:55 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id b189sm7279971wmb.37.2020.10.17.07.02.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:02:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 02/44] hw/qdev-clock: Display error hint when clock is missing from device Date: Sat, 17 Oct 2020 16:02:01 +0200 Message-Id: <20201017140243.1078718-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , "Edgar E . Iglesias" , Aleksandar Rikalo , Luc Michel , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Instead of directly aborting, display a hint to help the developer figure out the problem (likely trying to connect a clock to a device pre-dating the Clock API, thus not expecting clocks). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Reviewed-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Message-Id: <20201012095804.3335117-4-f4bug@amsat.org> --- hw/core/qdev-clock.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index 47ecb5b4fae..6a9a340d0fb 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -12,6 +12,7 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "hw/qdev-clock.h" #include "hw/qdev-core.h" #include "qapi/error.h" @@ -153,6 +154,11 @@ Clock *qdev_get_clock_in(DeviceState *dev, const char *name) assert(name); ncl = qdev_get_clocklist(dev, name); + if (!ncl) { + error_report("Can not find clock-in '%s' for device type '%s'", + name, object_get_typename(OBJECT(dev))); + abort(); + } assert(!ncl->output); return ncl->clock; @@ -165,6 +171,11 @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name) assert(name); ncl = qdev_get_clocklist(dev, name); + if (!ncl) { + error_report("Can not find clock-out '%s' for device type '%s'", + name, object_get_typename(OBJECT(dev))); + abort(); + } assert(ncl->output); return ncl->clock; From patchwork Sat Oct 17 14:02:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 79F9216BC for ; Sat, 17 Oct 2020 14:09:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D5DB2072C for ; Sat, 17 Oct 2020 14:09:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UokLcAdf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2D5DB2072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmtz-0001df-Ah for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:09:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmnY-0001VK-Fk for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:08 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmnW-0003gd-Qz for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:04 -0400 Received: by mail-wr1-x42c.google.com with SMTP id t9so6549393wrq.11 for ; Sat, 17 Oct 2020 07:03:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N+6P5UyNzQt64543jNV3+JqEP1ruUMZwDb9XjKLtnVQ=; b=UokLcAdfIvbxLFzHsZ+I+CiGEmjwM5PeSp77ZmCFFk3RV6ATrDiOffn65e2v7lhduq 7jMmhJEcYCjBJJG2CoPiX6dcTlXZ2kuo2teiO/ZxttnL60Wa04bFnw3HiqcLGaqK7vzQ LdYyr3hVim3AQvLtvbU19ewYtKwT9ynX1D1W2chfWAgvUqjvfXJ/MmFJr7xeqWBm2EwK BDDl9wYhbeouIv4p5X/3maRTAPAqp5ZqpXKIRMiE5ueaiRAYVAS/oltTiFFb+2k5w/GG m/3LUit1+mgriud4JH5Blu+KAVP4YuQCeCiwq+b3HoTSLrx0ygcpXQH6QgFAe29oAOly lrpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=N+6P5UyNzQt64543jNV3+JqEP1ruUMZwDb9XjKLtnVQ=; b=AF5XU5qALfbSKp5eveyHZRFISjRmcKV1tunLLnmmb+TsRFiAwp5e339Trygg8JjjEE bEY3qxbSXYMKvqpTvc63OFM/63xOLUzJw4/aj87j/ndCL7RoWYxqp5dFUNr703vQkhf5 CJc0ltgdaAgHiIR9T1+N1NkCbPZNkKkdujVOfZKhGDvpyTEaEe1QJbvhYve0yGcS7ci4 LjeUvKJCc3Jl+/+aye+c8+yeMUJt4Vy7Tpq5mvClWPE/Diewg0IfwefPOY96dp9WACnB rNVUofTnGeoQVWdcD/A1NBHrwkz0eV2k7EdZZiMdWkpQE4q1uKp3BQTS2VAAZX6KVNyO SusA== X-Gm-Message-State: AOAM533ME25qAioebKaHIYkTNYWj3VYPuFfCTOfo42rsp4nu5t1zckte cytmovse5biRPXMNhU8P1fSJKFucNB0= X-Google-Smtp-Source: ABdhPJyqrT+skP3Rc8vENV40BvEMM08JKTFVY/XKZPXcFmyh4Ppc3MLpElduEL+7q18vql3cCLBBDw== X-Received: by 2002:adf:e50b:: with SMTP id j11mr10486045wrm.263.1602943379830; Sat, 17 Oct 2020 07:02:59 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id x18sm9349551wrg.4.2020.10.17.07.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:02:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 03/44] hw/core/clock: Add the clock_new helper function Date: Sat, 17 Oct 2020 16:02:02 +0200 Message-Id: <20201017140243.1078718-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luc Michel , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Luc Michel This function creates a clock and parents it to another object with a given name. It calls clock_setup_canonical_path before returning the new clock. This function is useful to create clocks in devices when one doesn't want to expose it at the qdev level (as an input or an output). Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201010135759.437903-4-luc@lmichel.fr> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/clock.h | 13 +++++++++++++ hw/core/clock.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/hw/clock.h b/include/hw/clock.h index d357594df99..cbc5e6ced1e 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -90,6 +90,19 @@ extern const VMStateDescription vmstate_clock; */ void clock_setup_canonical_path(Clock *clk); +/** + * clock_new: + * @parent: the clock parent + * @name: the clock object name + * + * Helper function to create a new clock and parent it to @parent. There is no + * need to call clock_setup_canonical_path on the returned clock as it is done + * by this function. + * + * @return the newly created clock + */ +Clock *clock_new(Object *parent, const char *name); + /** * clock_set_callback: * @clk: the clock to register the callback into diff --git a/hw/core/clock.c b/hw/core/clock.c index 7066282f7b9..f866717a835 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -23,6 +23,21 @@ void clock_setup_canonical_path(Clock *clk) clk->canonical_path = object_get_canonical_path(OBJECT(clk)); } +Clock *clock_new(Object *parent, const char *name) +{ + Object *obj; + Clock *clk; + + obj = object_new(TYPE_CLOCK); + object_property_add_child(parent, name, obj); + object_unref(obj); + + clk = CLOCK(obj); + clock_setup_canonical_path(clk); + + return clk; +} + void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) { clk->callback = cb; From patchwork Sat Oct 17 14:02:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 045B81580 for ; Sat, 17 Oct 2020 14:07:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C01C72072C for ; Sat, 17 Oct 2020 14:07:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lhX/T6Br" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C01C72072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:39830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmrL-0006oR-Nc for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:06:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmne-0001WJ-SA for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:10 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:38942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmna-0003hD-Qs for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:10 -0400 Received: by mail-wr1-x431.google.com with SMTP id y12so6582122wrp.6 for ; Sat, 17 Oct 2020 07:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w+RNDLWj4IFLfK+eBwoAQeU4+ogED2fJwsKp3kpT+Og=; b=lhX/T6Bru4d0moFLuUF2q4LSoamJYEL5oNBJuvK0IxgRDUtHSVPxN6AJ0Bv4l22Qks xzJEqr2pha9/XVqVVrVWi8Hs+67hZcHWQUw5mjmWWvTYyvJYI8Ntl9CQNsggRghkr3P1 ubWi1C8ear09/xBwpw1L/uG2Snkt7LKZbT7g+T3X/3C0lrQTynM7yeGGrzj+BUggViO+ 4sEV7HyrGH74z67Au32UsqRXRlXXY7x6Lv8E/66MLcocGLWozxczlZ6x7xAoZOj3vUz6 62h3ybpTChNmvIIEVnhDyEV5ELR9G4f7xirn0wQNgRSYRlWsxA3KwWODqENhfKUx79Ih ilJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=w+RNDLWj4IFLfK+eBwoAQeU4+ogED2fJwsKp3kpT+Og=; b=BWlk4ViLd+rBuaoFe96QMZtll73g6YNBHCF/wxrG8zw74/hq05B+Fz5Hv3yjd67gZj nCZdXhlLSWk24tpihoz4hvwAN5+NZWFO31zh1ipl/5GzojER76NkfUDRAaJum4KXJ/A5 fUmru4PIsEdFVtHU3I/+thf68sNof8l+g6y4fVi2SVRUu7bhmiohYs1CEQxHw0zUCifa 6gbfnhOjCyMHiB0ym58q1lBnXl6OaY5MW53obhu9KsKX1qXRMjhlcLDRK0ZWXG+zPyXc XwPblI++Xhug+dABKN4vexiCSVjXp+m+H18iMt/TZ1LsWOAwDofahO4b/wtzQqpBYH79 O/yA== X-Gm-Message-State: AOAM530P/icpvpZ3Ohg4/weZo/0rJ2Y0nEseSWRulfpxFOAXVdf6H/AI 8E15XA3NqXAQxW/lqnlHk6S856j/VFM= X-Google-Smtp-Source: ABdhPJxG5+l9hlcXnZrOemPyWR8o2wyYmK06a0XaqlKt/EeufscTUvpOWH0ZY346xWY67cemSmFizg== X-Received: by 2002:adf:e444:: with SMTP id t4mr10876914wrm.58.1602943384583; Sat, 17 Oct 2020 07:03:04 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id f6sm8403768wru.50.2020.10.17.07.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 04/44] target/mips: Fix some comment spelling errors Date: Sat, 17 Oct 2020 16:02:03 +0200 Message-Id: <20201017140243.1078718-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , zhaolichang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Edmondson , =?utf-8?q?Herv=C3=A9_Poussine?= =?utf-8?q?au?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: zhaolichang There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 2 +- target/mips/translate.c | 10 +++++----- target/mips/translate_init.c.inc | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 7f159a9230c..b811f547f38 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) /* * A MIPS configured with a vectorizing external interrupt controller * will feed a vector into the Cause pending lines. The core treats - * the status lines as a vector level, not as indiviual masks. + * the status lines as a vector level, not as individual masks. */ r = pending > status; } else { diff --git a/target/mips/translate.c b/target/mips/translate.c index 398edf72898..b4d009078e0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, t0 = tcg_temp_new(); addr = tcg_temp_new(); - /* compare the address against that of the preceeding LL */ + /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); tcg_temp_free(addr); @@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) } /* return resulting half-words to its original position */ tcg_gen_shri_i32(t0, t0, 16); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); tcg_temp_free(t1); @@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) } /* return resulting half-words to its original position */ tcg_gen_shri_i32(t0, t0, 16); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); tcg_temp_free(t1); @@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) } /* return resulting byte to its original position */ tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } @@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) } /* return resulting byte to its original position */ tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 637caccd890..c735b2bf667 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) /* MVPConf1 implemented, TLB sharable, no gating storage support, programmable cache partitioning implemented, number of allocatable - and sharable TLB entries, MVP has allocatable TCs, 2 VPEs + and shareable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | From patchwork Sat Oct 17 14:02:04 2020 Content-Type: text/plain; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id 205sm7816168wme.38.2020.10.17.07.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 05/44] target/mips: Demacro helpers for . Date: Sat, 17 Oct 2020 16:02:04 +0200 Message-Id: <20201017140243.1078718-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/fpu_helper.c | 59 ++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 20 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 56beda49d82..f851723f22d 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -983,27 +983,46 @@ uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0) } /* unary operations, not modifying fp status */ -#define FLOAT_UNOP(name) \ -uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ -{ \ - return float64_ ## name(fdt0); \ -} \ -uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ -{ \ - return float32_ ## name(fst0); \ -} \ -uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ -{ \ - uint32_t wt0; \ - uint32_t wth0; \ - \ - wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ - wth0 = float32_ ## name(fdt0 >> 32); \ - return ((uint64_t)wth0 << 32) | wt0; \ + +uint64_t helper_float_abs_d(uint64_t fdt0) +{ + return float64_abs(fdt0); +} + +uint32_t helper_float_abs_s(uint32_t fst0) +{ + return float32_abs(fst0); +} + +uint64_t helper_float_abs_ps(uint64_t fdt0) +{ + uint32_t wt0; + uint32_t wth0; + + wt0 = float32_abs(fdt0 & 0XFFFFFFFF); + wth0 = float32_abs(fdt0 >> 32); + return ((uint64_t)wth0 << 32) | wt0; +} + +uint64_t helper_float_chs_d(uint64_t fdt0) +{ + return float64_chs(fdt0); +} + +uint32_t helper_float_chs_s(uint32_t fst0) +{ + return float32_chs(fst0); +} + +uint64_t helper_float_chs_ps(uint64_t fdt0) +{ + uint32_t wt0; + uint32_t wth0; + + wt0 = float32_chs(fdt0 & 0XFFFFFFFF); + wth0 = float32_chs(fdt0 >> 32); + return ((uint64_t)wth0 << 32) | wt0; } -FLOAT_UNOP(abs) -FLOAT_UNOP(chs) -#undef FLOAT_UNOP /* MIPS specific unary operations */ uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) From patchwork Sat Oct 17 14:02:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56D5114B4 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id h16sm9232144wre.87.2020.10.17.07.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/44] target/mips: Demacro helpers for MF. Date: Sat, 17 Oct 2020 16:02:05 +0200 Message-Id: <20201017140243.1078718-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/fpu_helper.c | 63 +++++++++++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index f851723f22d..b3c715494a9 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1666,25 +1666,54 @@ uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0, } -#define FLOAT_FMADDSUB(name, bits, muladd_arg) \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft, \ - uint ## bits ## _t fd) \ -{ \ - uint ## bits ## _t fdret; \ - \ - fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \ - &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return fdret; \ +uint32_t helper_float_maddf_s(CPUMIPSState *env, uint32_t fs, + uint32_t ft, uint32_t fd) +{ + uint32_t fdret; + + fdret = float32_muladd(fs, ft, fd, 0, + &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint64_t helper_float_maddf_d(CPUMIPSState *env, uint64_t fs, + uint64_t ft, uint64_t fd) +{ + uint64_t fdret; + + fdret = float64_muladd(fs, ft, fd, 0, + &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint32_t helper_float_msubf_s(CPUMIPSState *env, uint32_t fs, + uint32_t ft, uint32_t fd) +{ + uint32_t fdret; + + fdret = float32_muladd(fs, ft, fd, float_muladd_negate_product, + &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint64_t helper_float_msubf_d(CPUMIPSState *env, uint64_t fs, + uint64_t ft, uint64_t fd) +{ + uint64_t fdret; + + fdret = float64_muladd(fs, ft, fd, float_muladd_negate_product, + &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; } -FLOAT_FMADDSUB(maddf_s, 32, 0) -FLOAT_FMADDSUB(maddf_d, 64, 0) -FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product) -FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product) -#undef FLOAT_FMADDSUB /* compare operations */ #define FOP_COND_D(op, cond) \ From patchwork Sat Oct 17 14:02:06 2020 Content-Type: text/plain; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id s1sm7324631wmh.22.2020.10.17.07.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 07/44] target/mips: Demacro helpers for . Date: Sat, 17 Oct 2020 16:02:06 +0200 Message-Id: <20201017140243.1078718-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/fpu_helper.c | 98 ++++++++++++++++++++++++++++++++-------- 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index b3c715494a9..6cc956c023d 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1475,29 +1475,87 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) return ((uint64_t)fsth2 << 32) | fstl2; } -#define FLOAT_MINMAX(name, bits, minmaxfunc) \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft) \ -{ \ - uint ## bits ## _t fdret; \ - \ - fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \ - &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return fdret; \ + +uint32_t helper_float_max_s(CPUMIPSState *env, uint32_t fs, uint32_t ft) +{ + uint32_t fdret; + + fdret = float32_maxnum(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; } -FLOAT_MINMAX(max_s, 32, maxnum) -FLOAT_MINMAX(max_d, 64, maxnum) -FLOAT_MINMAX(maxa_s, 32, maxnummag) -FLOAT_MINMAX(maxa_d, 64, maxnummag) +uint64_t helper_float_max_d(CPUMIPSState *env, uint64_t fs, uint64_t ft) +{ + uint64_t fdret; + + fdret = float64_maxnum(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint32_t helper_float_maxa_s(CPUMIPSState *env, uint32_t fs, uint32_t ft) +{ + uint32_t fdret; + + fdret = float32_maxnummag(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint64_t helper_float_maxa_d(CPUMIPSState *env, uint64_t fs, uint64_t ft) +{ + uint64_t fdret; + + fdret = float64_maxnummag(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint32_t helper_float_min_s(CPUMIPSState *env, uint32_t fs, uint32_t ft) +{ + uint32_t fdret; + + fdret = float32_minnum(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint64_t helper_float_min_d(CPUMIPSState *env, uint64_t fs, uint64_t ft) +{ + uint64_t fdret; + + fdret = float64_minnum(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint32_t helper_float_mina_s(CPUMIPSState *env, uint32_t fs, uint32_t ft) +{ + uint32_t fdret; + + fdret = float32_minnummag(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} + +uint64_t helper_float_mina_d(CPUMIPSState *env, uint64_t fs, uint64_t ft) +{ + uint64_t fdret; + + fdret = float64_minnummag(fs, ft, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fdret; +} -FLOAT_MINMAX(min_s, 32, minnum) -FLOAT_MINMAX(min_d, 64, minnum) -FLOAT_MINMAX(mina_s, 32, minnummag) -FLOAT_MINMAX(mina_d, 64, minnummag) -#undef FLOAT_MINMAX /* ternary operations */ From patchwork Sat Oct 17 14:02:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DFE714B4 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id v4sm7231835wmg.35.2020.10.17.07.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Date: Sat, 17 Oct 2020 16:02:07 +0200 Message-Id: <20201017140243.1078718-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jiaxun Yang LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslq: load 16 bytes to GPR gssq: store 16 bytes from GPR gslqc1: load 16 bytes to FPR gssqc1: store 16 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com> [PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0] Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index b4d009078e0..e83954d782f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -460,6 +460,17 @@ enum { R6_OPC_SCD = 0x27 | OPC_SPECIAL3, }; +/* Loongson EXT load/store quad word opcodes */ +#define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020)) +enum { + OPC_GSLQ = 0x0020 | OPC_LWC2, + OPC_GSLQC1 = 0x8020 | OPC_LWC2, + OPC_GSSHFL = OPC_LWC2, + OPC_GSSQ = 0x0020 | OPC_SWC2, + OPC_GSSQC1 = 0x8020 | OPC_SWC2, + OPC_GSSHFS = OPC_SWC2, +}; + /* BSHFL opcodes */ #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -5910,6 +5921,79 @@ no_rd: tcg_temp_free_i64(t1); } +static void gen_loongson_lswc2(DisasContext *ctx, int rt, + int rs, int rd) +{ + TCGv t0; +#if defined(TARGET_MIPS64) + TCGv t1; + int lsq_rt1 = ctx->opcode & 0x1f; + int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; +#endif + + t0 = tcg_temp_new(); + + switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { +#if defined(TARGET_MIPS64) + case OPC_GSLQ: + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t1, rt); + gen_store_gpr(t0, lsq_rt1); + tcg_temp_free(t1); + break; + case OPC_GSLQC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_fpr64(ctx, t1, rt); + gen_store_fpr64(ctx, t0, lsq_rt1); + tcg_temp_free(t1); + break; + case OPC_GSSQ: + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + gen_load_gpr(t1, lsq_rt1); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; + case OPC_GSSQC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + gen_load_fpr64(ctx, t1, lsq_rt1); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; +#endif + default: + MIPS_INVAL("loongson_gslsq"); + generate_exception_end(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); +} + /* Traps */ static void gen_trap(DisasContext *ctx, uint32_t opc, int rs, int rt, int16_t imm) @@ -30774,6 +30858,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)); + } else if (ctx->insn_flags & ASE_LEXT) { + gen_loongson_lswc2(ctx, rt, rs, rd); } else { /* OPC_LWC2, OPC_SWC2 */ /* COP2: Not implemented. */ From patchwork Sat Oct 17 14:02:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B8F1014B5 for ; Sat, 17 Oct 2020 14:07:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 216732072C for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id 24sm7284039wmg.8.2020.10.17.07.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) Date: Sat, 17 Oct 2020 16:02:08 +0200 Message-Id: <20201017140243.1078718-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jiaxun Yang LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslwlc1: similar to lwl but RT is FPR instead of GPR gslwrc1: similar to lwr but RT is FPR instead of GPR gsldlc1: similar to ldl but RT is FPR instead of GPR gsldrc1: similar to ldr but RT is FPR instead of GPR gsswlc1: similar to swl but RT is FPR instead of GPR gsswrc1: similar to swr but RT is FPR instead of GPR gssdlc1: similar to sdl but RT is FPR instead of GPR gssdrc1: similar to sdr but RT is FPR instead of GPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com> [PMD: Reuse t1 on MIPS32, reintroduce t2/fp0] Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 182 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e83954d782f..b335645e03b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -471,6 +471,19 @@ enum { OPC_GSSHFS = OPC_SWC2, }; +/* Loongson EXT shifted load/store opcodes */ +#define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f)) +enum { + OPC_GSLWLC1 = 0x4 | OPC_GSSHFL, + OPC_GSLWRC1 = 0x5 | OPC_GSSHFL, + OPC_GSLDLC1 = 0x6 | OPC_GSSHFL, + OPC_GSLDRC1 = 0x7 | OPC_GSSHFL, + OPC_GSSWLC1 = 0x4 | OPC_GSSHFS, + OPC_GSSWRC1 = 0x5 | OPC_GSSHFS, + OPC_GSSDLC1 = 0x6 | OPC_GSSHFS, + OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, +}; + /* BSHFL opcodes */ #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -5924,12 +5937,13 @@ no_rd: static void gen_loongson_lswc2(DisasContext *ctx, int rt, int rs, int rd) { - TCGv t0; + TCGv t0, t1, t2; + TCGv_i32 fp0; #if defined(TARGET_MIPS64) - TCGv t1; int lsq_rt1 = ctx->opcode & 0x1f; int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; #endif + int shf_offset = sextract32(ctx->opcode, 6, 8); t0 = tcg_temp_new(); @@ -5986,6 +6000,170 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, tcg_temp_free(t1); break; #endif + case OPC_GSSHFL: + switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { + case OPC_GSLWLC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 = tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 3); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_shl_tl(t0, t0, t1); + t2 = tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + tcg_gen_andc_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); +#if defined(TARGET_MIPS64) + tcg_gen_extrl_i64_i32(fp0, t0); +#else + tcg_gen_ext32s_tl(fp0, t0); +#endif + gen_store_fpr32(ctx, fp0, rt); + tcg_temp_free_i32(fp0); + break; + case OPC_GSLWRC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 = tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 3); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 31); + t2 = tcg_const_tl(0xfffffffeull); + tcg_gen_shl_tl(t2, t2, t1); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); +#if defined(TARGET_MIPS64) + tcg_gen_extrl_i64_i32(fp0, t0); +#else + tcg_gen_ext32s_tl(fp0, t0); +#endif + gen_store_fpr32(ctx, fp0, rt); + tcg_temp_free_i32(fp0); + break; +#if defined(TARGET_MIPS64) + case OPC_GSLDLC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 = tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 7); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); + tcg_gen_shl_tl(t0, t0, t1); + t2 = tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_andc_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + gen_store_fpr64(ctx, t0, rt); + break; + case OPC_GSLDRC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 = tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 7); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 63); + t2 = tcg_const_tl(0xfffffffffffffffeull); + tcg_gen_shl_tl(t2, t2, t1); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + gen_store_fpr64(ctx, t0, rt); + break; +#endif + default: + MIPS_INVAL("loongson_gsshfl"); + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case OPC_GSSHFS: + switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { + case OPC_GSSWLC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + break; + case OPC_GSSWRC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + break; +#if defined(TARGET_MIPS64) + case OPC_GSSDLC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + gen_load_fpr64(ctx, t1, rt); + gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + break; + case OPC_GSSDRC1: + check_cp1_enabled(ctx); + t1 = tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + gen_load_fpr64(ctx, t1, rt); + gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + break; +#endif + default: + MIPS_INVAL("loongson_gsshfs"); + generate_exception_end(ctx, EXCP_RI); + break; + } + break; default: MIPS_INVAL("loongson_gslsq"); generate_exception_end(ctx, EXCP_RI); From patchwork Sat Oct 17 14:02:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B5261580 for ; Sat, 17 Oct 2020 14:05:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A92F02072C for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id l26sm7386822wmi.39.2020.10.17.07.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions Date: Sat, 17 Oct 2020 16:02:09 +0200 Message-Id: <20201017140243.1078718-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jiaxun Yang LDC2/SDC2 opcodes have been rewritten as "load & store with offset" group of instructions by loongson-ext ASE. This patch add implementation of these instructions: gslbx: load 1 bytes to GPR gslhx: load 2 bytes to GPR gslwx: load 4 bytes to GPR gsldx: load 8 bytes to GPR gslwxc1: load 4 bytes to FPR gsldxc1: load 8 bytes to FPR gssbx: store 1 bytes from GPR gsshx: store 2 bytes from GPR gsswx: store 4 bytes from GPR gssdx: store 8 bytes from GPR gsswxc1: store 4 bytes from FPR gssdxc1: store 8 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com> --- target/mips/translate.c | 179 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index b335645e03b..f449758606d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -484,6 +484,24 @@ enum { OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, }; +/* Loongson EXT LDC2/SDC2 opcodes */ +#define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7)) + +enum { + OPC_GSLBX = 0x0 | OPC_LDC2, + OPC_GSLHX = 0x1 | OPC_LDC2, + OPC_GSLWX = 0x2 | OPC_LDC2, + OPC_GSLDX = 0x3 | OPC_LDC2, + OPC_GSLWXC1 = 0x6 | OPC_LDC2, + OPC_GSLDXC1 = 0x7 | OPC_LDC2, + OPC_GSSBX = 0x0 | OPC_SDC2, + OPC_GSSHX = 0x1 | OPC_SDC2, + OPC_GSSWX = 0x2 | OPC_SDC2, + OPC_GSSDX = 0x3 | OPC_SDC2, + OPC_GSSWXC1 = 0x6 | OPC_SDC2, + OPC_GSSDXC1 = 0x7 | OPC_SDC2, +}; + /* BSHFL opcodes */ #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -6172,6 +6190,165 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, tcg_temp_free(t0); } +/* Loongson EXT LDC2/SDC2 */ +static void gen_loongson_lsdc2(DisasContext *ctx, int rt, + int rs, int rd) +{ + int offset = sextract32(ctx->opcode, 3, 8); + uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); + TCGv t0, t1; + TCGv_i32 fp0; + + /* Pre-conditions */ + switch (opc) { + case OPC_GSLBX: + case OPC_GSLHX: + case OPC_GSLWX: + case OPC_GSLDX: + /* prefetch, implement as NOP */ + if (rt == 0) { + return; + } + break; + case OPC_GSSBX: + case OPC_GSSHX: + case OPC_GSSWX: + case OPC_GSSDX: + break; + case OPC_GSLWXC1: +#if defined(TARGET_MIPS64) + case OPC_GSLDXC1: +#endif + check_cp1_enabled(ctx); + /* prefetch, implement as NOP */ + if (rt == 0) { + return; + } + break; + case OPC_GSSWXC1: +#if defined(TARGET_MIPS64) + case OPC_GSSDXC1: +#endif + check_cp1_enabled(ctx); + break; + default: + MIPS_INVAL("loongson_lsdc2"); + generate_exception_end(ctx, EXCP_RI); + return; + break; + } + + t0 = tcg_temp_new(); + + gen_base_offset_addr(ctx, t0, rs, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); + + switch (opc) { + case OPC_GSLBX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); + gen_store_gpr(t0, rt); + break; + case OPC_GSLHX: + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, rt); + break; + case OPC_GSLWX: + gen_base_offset_addr(ctx, t0, rs, offset); + if (rd) { + gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); + } + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, rt); + break; +#if defined(TARGET_MIPS64) + case OPC_GSLDX: + gen_base_offset_addr(ctx, t0, rs, offset); + if (rd) { + gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); + } + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t0, rt); + break; +#endif + case OPC_GSLWXC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, offset); + if (rd) { + gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); + } + fp0 = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + gen_store_fpr32(ctx, fp0, rt); + tcg_temp_free_i32(fp0); + break; +#if defined(TARGET_MIPS64) + case OPC_GSLDXC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, offset); + if (rd) { + gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); + } + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_fpr64(ctx, t0, rt); + break; +#endif + case OPC_GSSBX: + t1 = tcg_temp_new(); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_temp_free(t1); + break; + case OPC_GSSHX: + t1 = tcg_temp_new(); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; + case OPC_GSSWX: + t1 = tcg_temp_new(); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; +#if defined(TARGET_MIPS64) + case OPC_GSSDX: + t1 = tcg_temp_new(); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; +#endif + case OPC_GSSWXC1: + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); + tcg_temp_free_i32(fp0); + break; +#if defined(TARGET_MIPS64) + case OPC_GSSDXC1: + t1 = tcg_temp_new(); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; +#endif + default: + break; + } + + tcg_temp_free(t0); +} + /* Traps */ static void gen_trap(DisasContext *ctx, uint32_t opc, int rs, int rt, int16_t imm) @@ -31055,6 +31232,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) /* OPC_JIC, OPC_JIALC */ gen_compute_compact_branch(ctx, op, 0, rt, imm); } + } else if (ctx->insn_flags & ASE_LEXT) { + gen_loongson_lsdc2(ctx, rt, rs, rd); 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id x64sm7473502wmg.33.2020.10.17.07.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/44] target/mips/op_helper: Convert multiple if() to switch case Date: Sat, 17 Oct 2020 16:02:10 +0200 Message-Id: <20201017140243.1078718-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]). Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Message-Id: <20200813181527.22551-2-f4bug@amsat.org> --- target/mips/op_helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9552b280e07..c15f5c07761 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1574,15 +1574,20 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY + uint32_t cache_operation = extract32(op, 2, 3); target_ulong index = addr & 0x1fffffff; - if (op == 9) { - /* Index Store Tag */ + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); - } else if (op == 5) { - /* Index Load Tag */ + break; + case 0b001: /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); + break; + default: + break; } #endif } From patchwork Sat Oct 17 14:02:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E78C14B5 for ; Sat, 17 Oct 2020 14:12:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F9322072C for ; Sat, 17 Oct 2020 14:12:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JfYiAQd/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F9322072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:55950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmwU-0005Ct-Ne for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:12:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmoD-0001lz-DU for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:45 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:55081) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmoB-0003jZ-Rj for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:45 -0400 Received: by mail-wm1-x334.google.com with SMTP id p15so6122089wmi.4 for ; Sat, 17 Oct 2020 07:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LfhnJlD5ICt8SM68uBqo2cJX//28deS2z59iVNfu0PI=; b=JfYiAQd/bhekY/nPqLmhS0HWkfBC73prgWUMUtFgcG4iQaQtgGhh9z06CeSeIKwJrv 4JeTvDoqmZs66JC5j46jngl0fj7oaCR+OwxONsXdAKCTY+itW4wk9i1Ehz/5ayI3vIiR 7eUDp4LUnwnzpSZIV8QHMdsmdoIMMyfLcsSK0O1X2tpK3AO1rVWIjkBrETRBcECJv0l8 yigZyxjky+3UXCX5+TXJdd2zRx/jZm15csBXKvSvpZD6J4Mvvsxlg7yDs6d9+GcSwFiw ayWWTxhxJ5HsLX6R64kmMWJAMoyfemq9LxzdAWI7yrhQUG7Rtp2WHw1hQaYUcyi2hG9Q irRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LfhnJlD5ICt8SM68uBqo2cJX//28deS2z59iVNfu0PI=; b=Bqjo/+V1Luypi0bw6qH1FntGQyQ5iwaB263PVapzgpHZFp3oTwMRS1SQ/8oj1/mmCH JeCHyp4wB8YyPiXb+iPirIzTdtBbt7d3UlOpLJSaaHqkcQcMFgUt9ooyoX0wd5IRmE73 YWR9wU7Y4RpsUmR57UPrI0bBXovEvrY2/MjhhS5Lg7JJDKb8W1S5LYbQq922iu+5TKSg HVlDdA0PKTC8dTowGVialNs7BkXJcCcnjirLFig4ufJ/Vxrw/J4CJu2K2w+x7ImiU4mv s1zx5lFrIRKjGF85aiCJlLdkjU3oSPaS+MEyG2abIHCjI9DMPuQE/PXo3XwP8Xt1gBx4 t8IA== X-Gm-Message-State: AOAM533sVqzgIwFN5hOS4L1v2sAhxDucvqPlsY+rMvA0hRyzDvHFfFSL qorfsvSJ76XwHwjI4EO9MzjHXE8CbA8= X-Google-Smtp-Source: ABdhPJxuGE3erFN1R3CnyNhjkcDeOQbvlhsJ6lxe8pRD9gkn5Yeqh/ay8KId3J23Shb40JAI+v/zlw== X-Received: by 2002:a1c:bb06:: with SMTP id l6mr8944254wmf.40.1602943421884; Sat, 17 Oct 2020 07:03:41 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id e11sm3013725wrj.75.2020.10.17.07.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op Date: Sat, 17 Oct 2020 16:02:11 +0200 Message-Id: <20201017140243.1078718-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" QEMU does not model caches, so there is not much to do with the Invalidate/Writeback opcodes. Make it explicit adding a comment. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Message-Id: <20200813181527.22551-3-f4bug@amsat.org> --- target/mips/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c15f5c07761..2496d1dd718 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1586,6 +1586,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; default: break; } From patchwork Sat Oct 17 14:02:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C3FD814B4 for ; Sat, 17 Oct 2020 14:12:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 875B2206B6 for ; Sat, 17 Oct 2020 14:12:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KVCEkciR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 875B2206B6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:56274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmwa-0005LG-K3 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:12:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmoH-0001vK-P3 for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:49 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmoG-0003kt-8Y for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:49 -0400 Received: by mail-wr1-x436.google.com with SMTP id n6so6529999wrm.13 for ; Sat, 17 Oct 2020 07:03:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QVmCBzAijqIxVbHfMUmSPN/CpI6hZqRTxfcmVPbu0NA=; b=KVCEkciRTE7Jpa3bDmrfXZ/fBHouFmR5oJYG38COqNnNBEapA9epwsy0rUjWswoVYL e9YMWblt3k8VPQpZz6uSdVhzuxAcxuMjfhgBKvvSSGwOH2Wb5G01+T6nxWxTipPopDlu cNP+73uG1Hlwsho26PBRvlVXk8BCtgK4B2RAWFx0P3H7KqzHGZNtWwnfOeDdk5d0IfoG AHafDmTQazEMecfOwTa8gQM9XllRjYTfvBMaPxM7Ri3D2+WyJ6uos/cO9DSh0nF5wBzp tPAr3xEYFH5BaRWlOQqxOMJG/uBfecbF+ZHpb3HtIZ2BsCuBLQ+eCHoIbVT9H/qh4Nix 9rJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QVmCBzAijqIxVbHfMUmSPN/CpI6hZqRTxfcmVPbu0NA=; b=TpjDlSb3haemBKoxyfzZ4iuY+8979BvFOeJBCFtlb651C0s8rv3rXaDasvnNxjBkdH RY/kEUQu66aNpG0eJaYe8wwPB969+cT8nwZNn36DpZKxJ/Z/ljPEL1FXNJ9Fz54Jwpxq Ot3B3T9RKbIkeTdWlkHBHCXCADTK29NE9Dkfe9iV6GP+rcq52EyW27q0migNMvoPO9b3 sJtXciuHY7WGhMN2R8vVauDBa8LAxol8/qF+CiH9VCzbgaWdJfyc0s7U2M5wu3jM516p kqunT8DMP321jR46rXl5NbMszTvAPwlcdChaTzxKrpmitUsGlQfAzRif12FUnPlfx+m1 rIYA== X-Gm-Message-State: AOAM531mF1yFQG6fCtywFRumOrsnFsK7o+VTD4PqM2Wjos8wJeofXR8p 801yIDmraPIsKYhkrSQbT2lJ6HZ8V0Q= X-Google-Smtp-Source: ABdhPJwkqIqa9dMANp6emE7laWWkLuj4iweTq0EA3lDHIX8v+ibZe5ZSK5KwjUqTxFZhzfUKIxZDwQ== X-Received: by 2002:adf:e3cb:: with SMTP id k11mr10346246wrm.341.1602943426613; Sat, 17 Oct 2020 07:03:46 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id g5sm7492870wmi.4.2020.10.17.07.03.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode Date: Sat, 17 Oct 2020 16:02:12 +0200 Message-Id: <20201017140243.1078718-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In case the guest uses a cache opcode we are not expecting, log it to give us a chance to notice it, in case we should actually do something. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Message-Id: <20200813181527.22551-4-f4bug@amsat.org> --- target/mips/op_helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 2496d1dd718..0050d0616b6 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1574,6 +1574,13 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY + static const char *const type_name[] = { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type = extract32(op, 0, 2); uint32_t cache_operation = extract32(op, 2, 3); target_ulong index = addr & 0x1fffffff; @@ -1592,6 +1599,8 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) /* no-op */ break; default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); break; } #endif From patchwork Sat Oct 17 14:02:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C66314B4 for ; Sat, 17 Oct 2020 14:14:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C750420704 for ; Sat, 17 Oct 2020 14:14:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="suumtwTA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C750420704 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmyP-0000In-Rt for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:14:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmoM-00026W-Mn for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:54 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:50431) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmoK-0003lC-Qo for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:03:54 -0400 Received: by mail-wm1-x332.google.com with SMTP id 13so6155376wmf.0 for ; Sat, 17 Oct 2020 07:03:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NCF5wa/3qOXXh6lH3vb50TSlF2Pm3DCj19abyPtcLXk=; b=suumtwTAQbeubki8d5Fe1JXlQKCnhl75w6nufIOL78DUyxW0/kkfnoeJEHkSaK/4V0 SsNU1HvPXcnqhkSiPuKJvmGcEGj6FCMS5fhFM1Mq1jpsuV7ri11oDh4lsSklPNmzauwB q53xt8u8siGkKIKH8K0uhJIbRAUfyZEO9sxptf41l2UuSpNyrPq5RMitg7bhYxT4S85H 9cyGsr1YFigKBPMfLxSaoU1CYLKHVwkCXpo1uOxbcLKrMh1E5MVT+jnj5vceC0VE0j6a FRT5zXuzhFlG0tVNbU24S3FKr4puadQvwgPnT1G0IqisorFfra+6uy3SgGbb8J1saV8I Ji/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NCF5wa/3qOXXh6lH3vb50TSlF2Pm3DCj19abyPtcLXk=; b=ejZKv61U3etyWZVUCP4TGFZ60ZgLYFGEi/b3JC1niK14iT9MA1mPiv84IFN9VxS7Em SZpD/u5N604XCDkgkZgm71KhkCBi7+EjjeKi1++W1KZ/Vtv0SWVj4kUdI9rM7RDA77hJ UUgGE2WXEmeIt0xhP+9+RnV5eZFufB//Uzme2lB9OoB1Q3wDfrv+kYjJdzzodrpxRded W8xH4jGEx5h7/2eD1cniTXJd6E43ktQajIHMdedXlvYz9qDy+oGvhlfwSBXflz6Jz7Wi jYLD3GhYjqcksoBvw37QULLlXitRZKU76/Cv9qZkhlofOCt//j8oT3pgwEwB99KV++rz dl7w== X-Gm-Message-State: AOAM533rc4haPU+5AZl4RKUMP5+NH+PFOAcRBoBd+ab2sCzTdZezC1IJ PjM34wg9Xj1kSHDtmn1enrenJI7YtiE= X-Google-Smtp-Source: ABdhPJzcmYUUe4a7IEoN+3u18Uyyy2HBRzuoh1SaEuYDLu8X86t3dC9rXyIjzmVEPiUJSm95oclDSw== X-Received: by 2002:a1c:7c12:: with SMTP id x18mr8894969wmc.107.1602943431162; Sat, 17 Oct 2020 07:03:51 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id g125sm2882531wme.33.2020.10.17.07.03.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers Date: Sat, 17 Oct 2020 16:02:13 +0200 Message-Id: <20201017140243.1078718-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Luc Michel , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register used as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Reviewed-by: Luc Michel Message-Id: <20201012095804.3335117-6-f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++ target/mips/cp0_timer.c | 25 ------------------------- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index b811f547f38..dd8a7809b64 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); +uint32_t cpu_mips_get_random(CPUMIPSState *env); void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s); void cpu_mips_realize_env(CPUMIPSState *env); /* cp0_timer.c */ -uint32_t cpu_mips_get_random(CPUMIPSState *env); uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index de64add038b..12143ac55b9 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) *tcst |= asid; } +/* XXX: do not use a global */ +uint32_t cpu_mips_get_random(CPUMIPSState *env) +{ + static uint32_t seed = 1; + static uint32_t prev_idx; + uint32_t idx; + uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; + + if (nb_rand_tlb == 1) { + return env->tlb->nb_tlb - 1; + } + + /* Don't return same value twice, so get another value */ + do { + /* + * Use a simple algorithm of Linear Congruential Generator + * from ISO/IEC 9899 standard. + */ + seed = 1103515245 * seed + 12345; + idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; + } while (idx == prev_idx); + prev_idx = idx; + return idx; +} + /* CP0 helpers */ target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index bd7efb152dd..9c38e9da1c8 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -29,31 +29,6 @@ #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ -/* XXX: do not use a global */ -uint32_t cpu_mips_get_random(CPUMIPSState *env) -{ - static uint32_t seed = 1; - static uint32_t prev_idx = 0; - uint32_t idx; - uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; - - if (nb_rand_tlb == 1) { - return env->tlb->nb_tlb - 1; - } - - /* Don't return same value twice, so get another value */ - do { - /* - * Use a simple algorithm of Linear Congruential Generator - * from ISO/IEC 9899 standard. - */ - seed = 1103515245 * seed + 12345; - idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; - } while (idx == prev_idx); - prev_idx = idx; - return idx; -} - /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) { From patchwork Sat Oct 17 14:02:14 2020 Content-Type: text/plain; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id p9sm7542621wma.12.2020.10.17.07.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name Date: Sat, 17 Oct 2020 16:02:14 +0200 Message-Id: <20201017140243.1078718-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Name variables holding nanoseconds with the '_ns' suffix. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Message-Id: <20201012095804.3335117-7-f4bug@amsat.org> --- target/mips/cp0_timer.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 9c38e9da1c8..5194c967ae3 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -32,13 +32,14 @@ /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) { - uint64_t now, next; + uint64_t now_ns, next_ns; uint32_t wait; - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - wait = env->CP0_Compare - env->CP0_Count - (uint32_t)(now / TIMER_PERIOD); - next = now + (uint64_t)wait * TIMER_PERIOD; - timer_mod(env->timer, next); + now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + wait = env->CP0_Compare - env->CP0_Count - + (uint32_t)(now_ns / TIMER_PERIOD); + next_ns = now_ns + (uint64_t)wait * TIMER_PERIOD; + timer_mod(env->timer, next_ns); } /* Expire the timer. */ @@ -56,16 +57,16 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env) if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; } else { - uint64_t now; + uint64_t now_ns; - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); if (timer_pending(env->timer) - && timer_expired(env->timer, now)) { + && timer_expired(env->timer, now_ns)) { /* The timer has already expired. */ cpu_mips_timer_expire(env); } - return env->CP0_Count + (uint32_t)(now / TIMER_PERIOD); + return env->CP0_Count + (uint32_t)(now_ns / TIMER_PERIOD); } } From patchwork Sat Oct 17 14:02:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842773 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B54214B4 for ; Sat, 17 Oct 2020 14:18:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5DD3F20714 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id v6sm2513056wrp.69.2020.10.17.07.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin Date: Sat, 17 Oct 2020 16:02:15 +0200 Message-Id: <20201017140243.1078718-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" TIMER_PERIOD value of '10 ns' can be explained looking at commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz and CP0 default count rate is half the frequency of the CPU. Document that. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-8-f4bug@amsat.org> --- target/mips/cp0_timer.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5194c967ae3..6fec5fe0ff7 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -27,7 +27,17 @@ #include "sysemu/kvm.h" #include "internal.h" -#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ +/* + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz + * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2). + * + * TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz + * + * TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns + */ +#define CPU_FREQ_HZ_DEFAULT 200000000 +#define CP0_COUNT_RATE_DEFAULT 2 +#define TIMER_PERIOD 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) From patchwork Sat Oct 17 14:02:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842771 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5C2915E6 for ; Sat, 17 Oct 2020 14:18:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C13520714 for ; Sat, 17 Oct 2020 14:18:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pp7diaAg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6C13520714 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:52236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn2a-00074Z-IO for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:18:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmob-0002J5-OV for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:12 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:44923) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmoY-0003mL-Vm for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:08 -0400 Received: by mail-wr1-x429.google.com with SMTP id t9so6551558wrq.11 for ; Sat, 17 Oct 2020 07:04:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sUvsBgE8lqeGgpqBP2TiIkm6s4bhzj/3ycAdv64yLQA=; b=Pp7diaAgsS4FJ7mRd+CTmuBBGj9+4eZFWSgA7UjfBNWwNRCjejmzgKhcTs4FopZmFI q57zf1mmSZB1FSB5rgr0/H6XPskLG6qyKl+CXIrtY5AcAjJCF9MC6bZUsgOoBMFJjrlE iSZVbizlXj+CO5aYYq1RJzpPwqUeCnFXTaATcCyZbL/syGmtMhiZcifm5yE4ZLQFxOuN CqrqSwHxolrTTsvvwLjUMwYfLcGvXPIO1hYoRMQTQLvyeF53a9zAhQkdRhZSZlGV/R8I lSlW5pdVdr8Cy3a6K7xTplCE78lVyJ7cChNNj+d6TTUX/S6i/2YLIkp5qUlqdNbVzpbZ SFkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sUvsBgE8lqeGgpqBP2TiIkm6s4bhzj/3ycAdv64yLQA=; b=MsK1uwc3Q+uu6f4CPeBvsnqerttj94vJaG+S/uW4ipKTIiU+VkbDs6/UvHb+SMkCfp 1zGHRgNMoCduRQW+Ki64VnnJqRHdIXThUY6COmxXeTYR+TDO5CVol8WRhlH9eeNi9LtV SdryBEN3Z88W+DxWjQ8fK1aIooimdmoSbrlmuqHEdYGwkhLYcPtR8zQSd8KHrz8cXCPs J4P3waa6uLG7z5dGktB/x0B7+iwnwec6uygeHzCtvDEwOijsRgfZ1T7ijZBjkklQvyW0 anX7MlWbH+vTj1R/7uRwRORajA71oOsfHyfrIhq1bXacekBDVgbBCRfo/pE++2mJfD+W PBBA== X-Gm-Message-State: AOAM531YYx1eqtglF0kZkAKMxmHF2EWqKMcVEdZkWW8HoKp5MuoNQ3q5 rEUcaavfbQlLyQdCPdv2j39+aeMC0wA= X-Google-Smtp-Source: ABdhPJxsueWVIAKlVmpmTj2PWDv7ldxqtapggtb6nMpfS2wwKjTxCzVRsLtXL0K1ofNTwSlCh/Z0Vw== X-Received: by 2002:adf:84a5:: with SMTP id 34mr10949869wrg.152.1602943445414; Sat, 17 Oct 2020 07:04:05 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id z11sm8559575wrh.70.2020.10.17.07.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState Date: Sat, 17 Oct 2020 16:02:16 +0200 Message-Id: <20201017140243.1078718-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently the CP0 timer period is fixed at 10 ns, corresponding to a fixed CPU frequency of 200 MHz (using half the speed of the CPU). In few commits we will be able to use a different CPU frequency. In preparation, move the cp0_count_ns variable to CPUMIPSState so we can modify it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <20201012095804.3335117-9-f4bug@amsat.org> --- target/mips/cpu.h | 1 + target/mips/cp0_timer.c | 23 ++++++----------------- target/mips/cpu.c | 21 +++++++++++++++++++++ 3 files changed, 28 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7cf7f5239f7..085a88e9550 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1145,6 +1145,7 @@ struct CPUMIPSState { struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ + uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; /** diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 6fec5fe0ff7..5ec0d6249e9 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -27,18 +27,6 @@ #include "sysemu/kvm.h" #include "internal.h" -/* - * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz - * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2). - * - * TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz - * - * TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns - */ -#define CPU_FREQ_HZ_DEFAULT 200000000 -#define CP0_COUNT_RATE_DEFAULT 2 -#define TIMER_PERIOD 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ - /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) { @@ -47,8 +35,8 @@ static void cpu_mips_timer_update(CPUMIPSState *env) now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); wait = env->CP0_Compare - env->CP0_Count - - (uint32_t)(now_ns / TIMER_PERIOD); - next_ns = now_ns + (uint64_t)wait * TIMER_PERIOD; + (uint32_t)(now_ns / env->cp0_count_ns); + next_ns = now_ns + (uint64_t)wait * env->cp0_count_ns; timer_mod(env->timer, next_ns); } @@ -76,7 +64,7 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env) cpu_mips_timer_expire(env); } - return env->CP0_Count + (uint32_t)(now_ns / TIMER_PERIOD); + return env->CP0_Count + (uint32_t)(now_ns / env->cp0_count_ns); } } @@ -92,7 +80,8 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) } else { /* Store new count register */ env->CP0_Count = count - - (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD); + (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + env->cp0_count_ns); /* Update timer timer */ cpu_mips_timer_update(env); } @@ -119,7 +108,7 @@ void cpu_mips_stop_count(CPUMIPSState *env) { /* Store the current value */ env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / - TIMER_PERIOD); + env->cp0_count_ns); } static void mips_timer_cb(void *opaque) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e86cd065483..84b727fefa8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,6 +134,25 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +/* + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz + * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2). + * + * TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz + * + * TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns + */ +#define CPU_FREQ_HZ_DEFAULT 200000000 +#define CP0_COUNT_RATE_DEFAULT 2 +#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ + +static void mips_cp0_period_set(MIPSCPU *cpu) +{ + CPUMIPSState *env = &cpu->env; + + env->cp0_count_ns = TIMER_PERIOD_DEFAULT; +} + static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -141,6 +160,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; + mips_cp0_period_set(cpu); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); From patchwork Sat Oct 17 14:02:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842731 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A59C1580 for ; Sat, 17 Oct 2020 14:09:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 39CF92072C for ; Sat, 17 Oct 2020 14:09:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rOGUa/GV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 39CF92072C Authentication-Results: mail.kernel.org; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id b63sm7974074wme.9.2020.10.17.07.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency Date: Sat, 17 Oct 2020 16:02:17 +0200 Message-Id: <20201017140243.1078718-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The CP0 timer period is a function of the CPU frequency. Start using the default values, which will be replaced by properties in the next commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <20201012095804.3335117-10-f4bug@amsat.org> --- target/mips/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 84b727fefa8..46188139b7b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -144,13 +144,13 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 -#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - env->cp0_count_ns = TIMER_PERIOD_DEFAULT; + env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_DEFAULT, + CPU_FREQ_HZ_DEFAULT); } static void mips_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Sat Oct 17 14:02:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842743 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C931514B5 for ; Sat, 17 Oct 2020 14:11:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 646C42072C for ; Sat, 17 Oct 2020 14:11:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MpwL15+Q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 646C42072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:52452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmvU-0003lD-B0 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:11:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmol-0002Mz-AI for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:20 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:43718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmoi-0003mm-75 for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:18 -0400 Received: by mail-wr1-x436.google.com with SMTP id g12so6554771wrp.10 for ; Sat, 17 Oct 2020 07:04:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gcSFIGw0lHwM+wP/lVQPID0kXeFa2b1r5NkvHKAKJbE=; b=MpwL15+QPtIZ6xCu9ADESAqOwHrqfRTIZdDmRTaFxyMJUMPCzJnwXCMdYuYQUH4sRD AQYDr0mxi0MePgS2QoZYDvVa8jepqDiH6nYmxJo6DkWQep9nHkjBKkuYk417keIAL+z7 mGz/oWrNdG0wzGvx38Dds5ERj5vv0noEls5of+E6bepKb1T6kiSnTvQhA/7HHnyw+Gtu 9YufzxmlUA6fOrM64zj5JIASKnfE3hb/7F1/+BYQdLlUXG1Tx8C1r2seCxfa7xJNlMyx kr8jTeN+s0NB9Zwy3mHOv9F/gMGXurpkGoBxrR6hlTAgJ9tRZUdEBcjPOafFJf1pomhs l8nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gcSFIGw0lHwM+wP/lVQPID0kXeFa2b1r5NkvHKAKJbE=; b=m4NXs3qlVhI1A8tCyjnMQubrE7NLBpf5SZF3zZPKLgpY4ApAiIVLqJf++pWBebKhqt uFEjEoIBWPzj2wjUVKDXnAvJMJZoX9KLtdAKjBdlngfF9FMsUSXK+gS1W+/SFIF2LY/3 InY5LCad7AT3PS1wuCGF48ieyu+Dj+r6bO2+yDGzfLkaFTST9mghwNn9xpfuQtmiei94 0KEer1rGPDgbpZySdr3klIgPwTlqy21jWThCZ36nEMnbKvF8AhCnZhmVVbyR/pblhcwj PFayY5cTD91HNUl7aVUARG9t/lUkBJaGjDsDiBR1lRdjnfb9+8O5N4uLCT2mfaveLNs1 A1kA== X-Gm-Message-State: AOAM5307XUqyUdYGvs1dVHk4OvZNQaUF1I/hXZp8SNsF6lklJ0e1sDJL KdLKZ+dUrPxgqfDjEXl54+f2EtgpvEY= X-Google-Smtp-Source: ABdhPJzRtyBDoPYqNfT0aWPyzm/wJqvJoIlqEmjN9V64pFenmfVscg+msq3e/MvC4ANacWN21ug0Rw== X-Received: by 2002:a05:6000:1112:: with SMTP id z18mr10086418wrw.3.1602943454712; Sat, 17 Oct 2020 07:04:14 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id t12sm8996734wrm.25.2020.10.17.07.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property Date: Sat, 17 Oct 2020 16:02:18 +0200 Message-Id: <20201017140243.1078718-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-11-f4bug@amsat.org> --- target/mips/cpu.h | 9 +++++++++ target/mips/cpu.c | 19 +++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 085a88e9550..baeceb892ef 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1151,6 +1151,7 @@ struct CPUMIPSState { /** * MIPSCPU: * @env: #CPUMIPSState + * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. */ @@ -1161,6 +1162,14 @@ struct MIPSCPU { CPUNegativeOffsetState neg; CPUMIPSState env; + /* + * The Count register acts as a timer, incrementing at a constant rate, + * whether or not an instruction is executed, retired, or any forward + * progress is made through the pipeline. The rate at which the counter + * increments is implementation dependent, and is a function of the + * pipeline clock of the processor, not the issue width of the processor. + */ + unsigned cp0_count_rate; }; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 46188139b7b..461edfe22b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "exec/exec-all.h" - +#include "hw/qdev-properties.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -135,12 +135,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) } /* - * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz - * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = 2). - * - * TIMER_FREQ_HZ = CPU_FREQ_HZ / CP0_COUNT_RATE = 200 MHz / 2 = 100 MHz - * - * TIMER_PERIOD_NS = 1 / TIMER_FREQ_HZ = 10 ns + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 @@ -149,7 +144,7 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_DEFAULT, + env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_rate, CPU_FREQ_HZ_DEFAULT); } @@ -202,6 +197,13 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) return oc; } +static Property mips_cpu_properties[] = { + /* CP0 timer running at half the clock of the CPU */ + DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate, + CP0_COUNT_RATE_DEFAULT), + DEFINE_PROP_END_OF_LIST() +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -211,6 +213,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; From patchwork Sat Oct 17 14:02:19 2020 Content-Type: text/plain; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id a5sm8534104wrt.80.2020.10.17.07.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies Date: Sat, 17 Oct 2020 16:02:19 +0200 Message-Id: <20201017140243.1078718-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Use the Clock API and let the CPU object have an input clock. If no clock is connected, keep using the default frequency of 200 MHz used since the introduction of the 'r4k' machine in commit 6af0bf9c7c3. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-12-f4bug@amsat.org> --- target/mips/cpu.h | 4 ++++ target/mips/cpu.c | 11 +++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index baeceb892ef..062a4ba6225 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -4,6 +4,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" +#include "hw/clock.h" #include "mips-defs.h" #define TCG_GUEST_DEFAULT_MO (0) @@ -1151,6 +1152,8 @@ struct CPUMIPSState { /** * MIPSCPU: * @env: #CPUMIPSState + * @clock: this CPU input clock (may be connected + * to an output clock from another device). * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. @@ -1160,6 +1163,7 @@ struct MIPSCPU { CPUState parent_obj; /*< public >*/ + Clock *clock; CPUNegativeOffsetState neg; CPUMIPSState env; /* diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 461edfe22b7..2a6f4840e20 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -27,6 +27,7 @@ #include "sysemu/kvm.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -144,8 +145,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_rate, - CPU_FREQ_HZ_DEFAULT); + env->cp0_count_ns = cpu->cp0_count_rate + * clock_get_ns(MIPS_CPU(cpu)->clock); + assert(env->cp0_count_ns); } static void mips_cpu_realizefn(DeviceState *dev, Error **errp) @@ -155,6 +157,10 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; + if (!clock_get(cpu->clock)) { + /* Initialize the frequency in case the clock remains unconnected. */ + clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); + } mips_cp0_period_set(cpu); cpu_exec_realizefn(cs, &local_err); @@ -178,6 +184,7 @@ static void mips_cpu_initfn(Object *obj) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); cpu_set_cpustate_pointers(cpu); + cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu); env->cpu_model = mcc->cpu_def; } From patchwork Sat Oct 17 14:02:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD6F915E6 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id 71sm9193904wrm.20.2020.10.17.07.04.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper Date: Sat, 17 Oct 2020 16:02:20 +0200 Message-Id: <20201017140243.1078718-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce an helper to create a MIPS CPU and connect it to a reference clock. This helper is not MIPS specific, but so far only MIPS CPUs need it. Suggested-by: Huacai Chen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-13-f4bug@amsat.org> --- target/mips/cpu.h | 12 ++++++++++++ target/mips/cpu.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 062a4ba6225..d41579d44ae 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1307,4 +1307,16 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, MIPS_HFLAG_HWRENA_ULR); } +/** + * mips_cpu_create_with_clock: + * @typename: a MIPS CPU type. + * @cpu_refclk: this cpu input clock (an output clock of another device) + * + * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, + * then realizes the CPU. + * + * Returns: A #CPUState or %NULL if an error occurred. + */ +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); + #endif /* MIPS_CPU_H */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 2a6f4840e20..33a9ed5c24b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -288,3 +288,15 @@ static void mips_cpu_register_types(void) } type_init(mips_cpu_register_types) + +/* Could be used by generic CPU object */ +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) +{ + DeviceState *cpu; + + cpu = DEVICE(object_new(cpu_type)); + qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); + qdev_realize(cpu, NULL, &error_abort); + + return MIPS_CPU(cpu); +} From patchwork Sat Oct 17 14:02:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842779 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B250114B4 for ; Sat, 17 Oct 2020 14:20:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BB5B20714 for ; Sat, 17 Oct 2020 14:20:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QpSQevVZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7BB5B20714 Authentication-Results: mail.kernel.org; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id s11sm8853952wrm.56.2020.10.17.07.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz Date: Sat, 17 Oct 2020 16:02:21 +0200 Message-Id: <20201017140243.1078718-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Since its introduction in commit 6af0bf9c7c3, the 'r4k' machine runs at 200 MHz. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-14-f4bug@amsat.org> --- hw/mips/r4k.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c index 3487013a4a1..39bc626e7c5 100644 --- a/hw/mips/r4k.c +++ b/hw/mips/r4k.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" +#include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/intc/i8259.h" @@ -182,6 +183,7 @@ void mips_r4k_init(MachineState *machine) MemoryRegion *isa_io = g_new(MemoryRegion, 1); MemoryRegion *isa_mem = g_new(MemoryRegion, 1); int bios_size; + Clock *cpuclk; MIPSCPU *cpu; CPUMIPSState *env; ResetData *reset_info; @@ -192,8 +194,11 @@ void mips_r4k_init(MachineState *machine) DriveInfo *dinfo; int be; + cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); + clock_set_hz(cpuclk, 200000000); /* 200 MHz */ + /* init CPUs */ - cpu = MIPS_CPU(cpu_create(machine->cpu_type)); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); From patchwork Sat Oct 17 14:02:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842783 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D97E514B4 for ; Sat, 17 Oct 2020 14:22:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B9792064B for ; Sat, 17 Oct 2020 14:22:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iEPscC/K" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9B9792064B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:34792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn6W-0003HR-O3 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:22:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmp2-0002kB-Sv for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:37 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmp1-0003o1-6N for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:36 -0400 Received: by mail-wm1-x32c.google.com with SMTP id p15so6123471wmi.4 for ; Sat, 17 Oct 2020 07:04:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2du0I+yb+HwbuymUy7ZKJilfZng7wrSnlIMlk5mAbJI=; b=iEPscC/Krn7YrA07zMjweZVyt0/W+ECwh9ZMJRBs2yXBAANa9yUZ6Hf2H+Ab3fWR0W oK+jne/InRQHMFjtMLRHAIXX5V82fJRj14ekuqSzzYg2uj1oLMOgJNHThBYjNpWwjc1N E1zbC9k1vy9DWuyyy9k5a/LPDb19nAXUV1zGJNxMETd1L9+6PYLiNv+xGlq/S6t8pMqr vmPhgzD6EzqPy29EtS04Fbb9++Ey4cBI+flF2vrUSKcj/whDZAyUfokz4lc3QRymgRnT 2eLryTNVFUD7N88MUXd9KZ/bdogPy1DGKTK3aV9WuQzn0OT3rQubBv3MG3yWQL63vvMH zOxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2du0I+yb+HwbuymUy7ZKJilfZng7wrSnlIMlk5mAbJI=; b=WLj64MmQ52/byVjgOF5+c+0D1pnkhdbAPbedpJ8+qloRC+hf3YsFoGvCR5uO8PqrBd NJVS3vlevqeVhWktu3Qyma8VXomqIFiiHSkBVN0y8v7dlojhA6o6KnL4yci6aMWR6nm9 lIporh795s/l9jf5MC0ApwXdbFj7UbbYSiSHnwYDL9xYtp04GapAHUL5C3TMnSbpqRXY F3OTPkjVBn7lwAqQVlI2UO8ZGP1XHNptra1QpphZOJiEejLhoyAAqwn6c8OqKRsvb7bj c6bb2C9t66dW4+7z4M66X4jK46aa4xrWIIGlFSZd6DgvtGMRzpzMaB/BnEtvzp6yPE0f O0hw== X-Gm-Message-State: AOAM533V6DdFajOicTmPI7LlCE3BO7mSiWmoCM2lCjiv6SOS54BzOV8r zFYgxmwPsilN1gRmpVN1OY42kK+3fp0= X-Google-Smtp-Source: ABdhPJwJ6w2hjGX0HLJUBBmgfA1ehblMkszC93hdqLx70HXtb52c+i1jH/5ZIw+SVPzXwxhLZqleEA== X-Received: by 2002:a1c:7d54:: with SMTP id y81mr8342558wmc.114.1602943473422; Sat, 17 Oct 2020 07:04:33 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id i33sm9106111wri.79.2020.10.17.07.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz Date: Sat, 17 Oct 2020 16:02:22 +0200 Message-Id: <20201017140243.1078718-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The CPU frequency is normally provided by the firmware in the "cpuclock" environment variable. The 2E board can handles up to 660MHz, but be conservative and take the same value used by the Linux kernel: 533 MHz. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <20201012095804.3335117-15-f4bug@amsat.org> --- hw/mips/fuloong2e.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index b000ed1d7f7..b8234f61083 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -23,6 +23,7 @@ #include "qemu/units.h" #include "qapi/error.h" #include "cpu.h" +#include "hw/clock.h" #include "hw/intc/i8259.h" #include "hw/dma/i8257.h" #include "hw/isa/superio.h" @@ -298,12 +299,16 @@ static void mips_fuloong2e_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; I2CBus *smbus; + Clock *cpuclk; MIPSCPU *cpu; CPUMIPSState *env; DeviceState *dev; + cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); + clock_set_hz(cpuclk, 533080000); /* ~533 MHz */ + /* init CPUs */ - cpu = MIPS_CPU(cpu_create(machine->cpu_type)); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); From patchwork Sat Oct 17 14:02:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842785 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA02515E6 for ; Sat, 17 Oct 2020 14:24:15 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 654FF20657 for ; Sat, 17 Oct 2020 14:24:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="olCb6qdu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 654FF20657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:38830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn82-0004yY-3x for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:24:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmp7-0002oC-01 for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:41 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:37883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmp5-0003oM-Df for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:40 -0400 Received: by mail-wr1-x432.google.com with SMTP id h7so6604146wre.4 for ; Sat, 17 Oct 2020 07:04:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RVpDTlE+erpFb5VKlsMSt7Bi8xmM/yPxH3xBl9KpxtU=; b=olCb6qduyY2UmWFDxguyfTzByj/6QvaiOGVCBu865dPC+977VUl7fUVGoiawDwdrmW K1Bfp1QjlK4oSazp7MbC6Y+C9M+uDAhl3D7x73RM6V/ZJuewdkTnx6d80OOsIuqXyB3j wJ62YtXUPuR7MiDci2gYUuP59TFRf3kmtvKiqJ3Pp9S/fcnHkw7Z8xZ9TSfSOtnogj82 EMEQWSzVAvLD1FdiMMwuzWKK5wRD+xgb5hmumLkvcN2E+kZH3LmwGJ4otE9loNp9qwkD 3qkVy5BtPzmda1PFVVz7BKcV9k0284cEJ4N9edrj9oKLfVQxDYjrsPKmII9ruUkqAcZz f47Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RVpDTlE+erpFb5VKlsMSt7Bi8xmM/yPxH3xBl9KpxtU=; b=r1q3YzPwPWrpgIQ1QKnyjxKIGIsc1yUwygE5Fad/1EC7umzcf4aGtzeBIPMy5RYBRJ Me2NPb9r6D6res/BIe7NemMsjvLBfhx0qqDShL8zG17Qyydid9pNsiHAnwCt9fR4ML/g ZutwpjLNHNm0zPBn59UqP2b8euElsfktKPiZiJafZNpDVG0QBIhzQojHkMBB0KART8ru lYDawc826ZxFz74eHwGVtiygiPfaI2MwiQGaYWUuOWRNSNOsuVnT44DVoGwZsu/IKfDY LFX3KM6WsTx8vwn7J4pX6s4sYlxc7vBn5eNr0AtL67+bf/qJS3jm//wTYWmNqyFZmSUN 4cUw== X-Gm-Message-State: AOAM530zF1Bucz+xjiD2JdEyGpQqZz6fm+B2/GAzu91cPmb1f4z+T1A1 sjsx0OYGcdReejaGuyrka56H4houQc0= X-Google-Smtp-Source: ABdhPJzd2DPD4PRYqXoc5mdju30MlEtlO79KZdouSZdk5Fqvu0EWZNaaFsacCDeiWyqDDClemqW2fg== X-Received: by 2002:adf:f3c7:: with SMTP id g7mr10869289wrp.394.1602943477938; Sat, 17 Oct 2020 07:04:37 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id t10sm7295832wmf.46.2020.10.17.07.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 24/44] hw/mips/mipssim: Correct CPU frequency Date: Sat, 17 Oct 2020 16:02:23 +0200 Message-Id: <20201017140243.1078718-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The MIPSsim machine CPU frequency is too fast running at 200 MHz, while it should be 12 MHz for the 24K and 6 MHz for the 5K core. Ref: Linux commit c78cbf49c4ed ("Support for MIPSsim, the cycle accurate MIPS simulator.") Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-16-f4bug@amsat.org> --- hw/mips/mipssim.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 5d4ad74828d..f0042f7f436 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -29,6 +29,7 @@ #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" +#include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/char/serial.h" @@ -150,13 +151,21 @@ mips_mipssim_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *isa = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); + Clock *cpuclk; MIPSCPU *cpu; CPUMIPSState *env; ResetData *reset_info; int bios_size; + cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); +#ifdef TARGET_MIPS64 + clock_set_hz(cpuclk, 6000000); /* 6 MHz */ +#else + clock_set_hz(cpuclk, 12000000); /* 12 MHz */ +#endif + /* Init CPUs. */ - cpu = MIPS_CPU(cpu_create(machine->cpu_type)); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); env = &cpu->env; reset_info = g_malloc0(sizeof(ResetData)); From patchwork Sat Oct 17 14:02:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5397814B5 for ; Sat, 17 Oct 2020 14:13:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0733F20704 for ; Sat, 17 Oct 2020 14:13:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mqHNvVO2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0733F20704 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmxX-0007AW-5M for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:13:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpC-000339-Cl for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:46 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:35836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpA-0003ou-Ot for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:04:46 -0400 Received: by mail-wm1-x334.google.com with SMTP id q5so8400700wmq.0 for ; Sat, 17 Oct 2020 07:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XmLmCuW1uC91Ho4Ow45XNevc9vvm/zFFsaaxmUUiG5M=; b=mqHNvVO2fTMeS3nBKdm4vhleFvgihW6QRu3mUkC5imATa2QZ2zKtKNyFHkR6Ccot2+ +md8ipYIZm57WNnUPBgSfgg9qi0E0jD6oE295Y8MBqzt7v9H9IOzbWJvyhk7Oud/oc1X eMoib9l90CxJtzMpG/VAALC0aK5FkBi8eRG956I5ayjrpZk2UuIQrWfPeVJ40bR+70yV BGpXsPc3eTxE5jLjTAeUqUamkjgNgR7Y35CdAoCm8Zzyg5JPXo1+rmfe4tcOY7AZPbmO CcjGQmcGwLqSMRQHzqsJ6lCivTjtnw2LmJBf+qzUaNHoHCR79B+k7YbLyoVL1DUSck4s HVBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XmLmCuW1uC91Ho4Ow45XNevc9vvm/zFFsaaxmUUiG5M=; b=jELkQfnFs411boZ7eRT4FL5KwzXSHggHSFpnqR0b4xTDtKHq8oPwaOMl2Bu53XITvS 4CD5F+pC6LxOSlxkCFTiqulOTQCvLSGPUuVC3FQHBzfD7Ed8aqZjRPqLUV/PCeOGaITf VjuSexR/ZDbhWSf0sZwYscunufLtB/rufON+DmH+rIi0T7gVNPbCsT1N28RCyGZFEiB7 CjuKqs1MxL+x0IRU9/d9XjNaCfHoLcKMbrXwTuj1LTlE2qDMYQkJ1DMUJ1YgWQE5rA4C ckyctiBNmBYw2O05rYI1lkZdqyqDHdxaveSHur/wO4k7z8iBH8sj4xIXJvxCIMh2z7Tb r3wg== X-Gm-Message-State: AOAM532awnEJyL8z2bghBY/9Z5k/b5iFU9vKQ7O+NKMrYbzmyK72GXxB wfWBBt8Brv2QuU/g1QInwkRjqnepqAk= X-Google-Smtp-Source: ABdhPJwj01yC179U9DYlynyObToIbQeXqwPVrPV5r+USZE7Ridb8rpPYLCwGaZB60dbFY1V2tyOFSw== X-Received: by 2002:a05:600c:2144:: with SMTP id v4mr8603091wml.172.1602943482716; Sat, 17 Oct 2020 07:04:42 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id j7sm9226923wrn.81.2020.10.17.07.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 25/44] hw/mips/jazz: Correct CPU frequencies Date: Sat, 17 Oct 2020 16:02:24 +0200 Message-Id: <20201017140243.1078718-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61 CPU at ~134 MHz. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-17-f4bug@amsat.org> --- hw/mips/jazz.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 47723093b63..8f1ad55ba34 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" +#include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/intc/i8259.h" @@ -142,6 +143,7 @@ static void mips_jazz_init(MachineState *machine, MemoryRegion *address_space = get_system_memory(); char *filename; int bios_size, n; + Clock *cpuclk; MIPSCPU *cpu; CPUClass *cc; CPUMIPSState *env; @@ -163,14 +165,25 @@ static void mips_jazz_init(MachineState *machine, MemoryRegion *bios2 = g_new(MemoryRegion, 1); SysBusESPState *sysbus_esp; ESPState *esp; + static const struct { + unsigned freq_hz; + unsigned pll_mult; + } ext_clk[] = { + [JAZZ_MAGNUM] = {50000000, 2}, + [JAZZ_PICA61] = {33333333, 4}, + }; if (machine->ram_size > 256 * MiB) { error_report("RAM size more than 256Mb is not supported"); exit(EXIT_FAILURE); } + cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); + clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz + * ext_clk[jazz_model].pll_mult); + /* init CPUs */ - cpu = MIPS_CPU(cpu_create(machine->cpu_type)); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); From patchwork Sat Oct 17 14:02:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842791 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A230414B4 for ; Sat, 17 Oct 2020 14:25:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55A6D20657 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id x3sm7544780wmi.45.2020.10.17.07.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores Date: Sat, 17 Oct 2020 16:02:25 +0200 Message-Id: <20201017140243.1078718-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Expose a qdev input clock named 'clk-in', and connect it to each core to forward-propagate the clock. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-18-f4bug@amsat.org> --- include/hw/mips/cps.h | 2 ++ hw/mips/cps.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 9e35a881366..859a8d4a674 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -21,6 +21,7 @@ #define MIPS_CPS_H #include "hw/sysbus.h" +#include "hw/clock.h" #include "hw/misc/mips_cmgcr.h" #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" @@ -43,6 +44,7 @@ struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + Clock *clock; }; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 23c0f87e41a..af7b58c4bdd 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -22,6 +22,7 @@ #include "qemu/module.h" #include "hw/mips/cps.h" #include "hw/mips/mips.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "hw/mips/cpudevs.h" #include "sysemu/kvm.h" @@ -38,6 +39,7 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MIPSCPSState *s = MIPS_CPS(obj); + s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL); /* * Cover entire address space as there do not seem to be any * constraints for the base address of CPC and GIC. @@ -80,6 +82,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) errp)) { return; } + /* All cores use the same clock tree */ + qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return; From patchwork Sat Oct 17 14:02:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842787 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 339D814B4 for ; Sat, 17 Oct 2020 14:24:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23AEF20657 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id m11sm7619662wmf.10.2020.10.17.07.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz Date: Sat, 17 Oct 2020 16:02:26 +0200 Message-Id: <20201017140243.1078718-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The I6400 can run at 1 GHz or more. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-19-f4bug@amsat.org> --- hw/mips/boston.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b3f69e949c..cf2296f4488 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -30,6 +30,7 @@ #include "hw/mips/cps.h" #include "hw/mips/cpudevs.h" #include "hw/pci-host/xilinx-pcie.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -54,6 +55,7 @@ struct BostonState { MachineState *mach; MIPSCPSState cps; SerialMM *uart; + Clock *cpuclk; CharBackend lcd_display; char lcd_content[8]; @@ -251,10 +253,19 @@ static const MemoryRegionOps boston_platreg_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static void mips_boston_instance_init(Object *obj) +{ + BostonState *s = BOSTON(obj); + + s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); + clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ +} + static const TypeInfo boston_device = { .name = TYPE_MIPS_BOSTON, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BostonState), + .instance_init = mips_boston_instance_init, }; static void boston_register_types(void) @@ -462,6 +473,8 @@ static void boston_mach_init(MachineState *machine) &error_fatal); object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, &error_fatal); + qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", + qdev_get_clock_out(dev, "cpu-refclk")); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); From patchwork Sat Oct 17 14:02:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842797 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57F7D14B4 for ; Sat, 17 Oct 2020 14:27:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 08F2E20657 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id x21sm8374368wmi.3.2020.10.17.07.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz Date: Sat, 17 Oct 2020 16:02:27 +0200 Message-Id: <20201017140243.1078718-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-20-f4bug@amsat.org> --- hw/mips/malta.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4019c9dc1a8..1e2b750719e 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -26,6 +26,7 @@ #include "qemu/units.h" #include "qemu-common.h" #include "cpu.h" +#include "hw/clock.h" #include "hw/southbridge/piix.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" @@ -57,6 +58,7 @@ #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" +#include "hw/qdev-clock.h" #define ENVP_ADDR 0x80002000l #define ENVP_NB_ENTRIES 16 @@ -94,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) struct MaltaState { SysBusDevice parent_obj; + Clock *cpuclk; MIPSCPSState cps; qemu_irq i8259[ISA_NUM_IRQS]; }; @@ -1159,7 +1162,7 @@ static void main_cpu_reset(void *opaque) } } -static void create_cpu_without_cps(MachineState *ms, +static void create_cpu_without_cps(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { CPUMIPSState *env; @@ -1167,7 +1170,7 @@ static void create_cpu_without_cps(MachineState *ms, int i; for (i = 0; i < ms->smp.cpus; i++) { - cpu = MIPS_CPU(cpu_create(ms->cpu_type)); + cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -1189,6 +1192,7 @@ static void create_cps(MachineState *ms, MaltaState *s, &error_fatal); object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); + qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); @@ -1203,7 +1207,7 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s, if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { - create_cpu_without_cps(ms, cbus_irq, i8259_irq); + create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); } } @@ -1421,10 +1425,19 @@ void mips_malta_init(MachineState *machine) pci_vga_init(pci_bus); } +static void mips_malta_instance_init(Object *obj) +{ + MaltaState *s = MIPS_MALTA(obj); + + s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); + clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ +} + static const TypeInfo mips_malta_device = { .name = TYPE_MIPS_MALTA, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(MaltaState), + .instance_init = mips_malta_instance_init, }; static void mips_malta_machine_init(MachineClass *mc) From patchwork Sat Oct 17 14:02:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842807 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A44815E6 for ; Sat, 17 Oct 2020 14:29:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1DC620657 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id z6sm8889134wrm.33.2020.10.17.07.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 29/44] hw/mips/cps: Do not allow use without input clock Date: Sat, 17 Oct 2020 16:02:28 +0200 Message-Id: <20201017140243.1078718-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Now than all QOM users provides the input clock, do not allow using a CPS without input clock connected. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-21-f4bug@amsat.org> --- hw/mips/cps.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index af7b58c4bdd..c624821315a 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -74,6 +74,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) bool itu_present = false; bool saar_present = false; + if (!clock_get(s->clock)) { + error_setg(errp, "CPS input clock is not connected to an output clock"); + return; + } + for (i = 0; i < s->num_vp; i++) { cpu = MIPS_CPU(object_new(s->cpu_type)); From patchwork Sat Oct 17 14:02:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842813 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5270B15E6 for ; Sat, 17 Oct 2020 14:32:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 197A720657 for ; Sat, 17 Oct 2020 14:32:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SGTBbSiX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 197A720657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnFe-000735-74 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:32:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37244) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpb-0003lR-6Y for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:11 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:55759) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpZ-0003sq-3F for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:10 -0400 Received: by mail-wm1-x343.google.com with SMTP id a72so6127153wme.5 for ; Sat, 17 Oct 2020 07:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iLy9KPPIH/IaR0EvDlMGJ9V0mA4+5oswM3SWnu1jL9U=; b=SGTBbSiXbW9YLOK7kkSjYZ6om3fWfJYG/10jwtHMmJOtCUuOesQiFjCefKFKWNCyId kE/2D/EV2AaZppTg3YITIUdnBfJdqV/ZDuB7B9lfYwsvWVXxO+1/FDw4kWrJEMKVYB3G WtE5TudopTS7w1pyObY7jzoKiJ/ePPGApm/q3yF5+JQgI1cbaLM+y/MamyyBhivkvE8t fD5lrlUY/qmXcoLb5dpqcSKB+6E4WZlTTLVjgAFzL4wnHJoSI+tZhIzuW926A6k9xq8s f327sQ3y40/j80SdTn1XTe28FnbOzQYwAuAqfGFMOxbT4ixDnhJ1R+cG4rstGL+ahn2Z +D4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iLy9KPPIH/IaR0EvDlMGJ9V0mA4+5oswM3SWnu1jL9U=; b=WO2yxmgvR/hecMIh121ugjAdyeGdHnU2qNBBgUaXM/XAkNj6+GzTS2sRl5oQDx2W06 YNj8cSrC+8+wJKb+kOS6ev/IoE6o9Yqcjh4cx+7Xo1QO645uKn3wYbF3enb4aBPD0s8j z2P2byzzjJ+sw0ZsBQXg6a8Ql5vvfFK3vlvuxvL4V3bqyHZnWEmLIK+l1vpgKUYcJrx8 JnQVACzHYuvh4SI36DzHIp6feaSX4FLqlwSP0Dcp2jMeizAKR0GpWHoQefqzQF+Ia7IW GARHJo6ZfLBCl0DnflBGWul/JmZAlyT7mruZZMw/AlbbK3Mw8eyT2r9aNMvqLcX6diHC WW3w== X-Gm-Message-State: AOAM531xxEIh5BWsem74B+CA2w+ElRDmxDec7jwwDPdVoUl8IChn64GO o4qMsEEsuK/5zoC/csVH3g6ugvVFOVg= X-Google-Smtp-Source: ABdhPJxZdWzeM2W3p56t8YM+Id/2hJtkmh3nJiJP4T26fcY+JVdpepPFWV8jt97BlY3BWaoDCQcWQw== X-Received: by 2002:a1c:6302:: with SMTP id x2mr9141898wmb.121.1602943505962; Sat, 17 Oct 2020 07:05:05 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id n5sm8920455wrm.2.2020.10.17.07.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock Date: Sat, 17 Oct 2020 16:02:29 +0200 Message-Id: <20201017140243.1078718-31-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" All our QOM users provides an input clock. In order to avoid avoid future machines added without clock, display a warning. User-mode emulation use the CP0 timer with the RDHWR instruction (see commit cdfcad788394) so keep using the fixed 200 MHz clock without diplaying any warning. Only display it in system-mode emulation. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201012095804.3335117-22-f4bug@amsat.org> --- target/mips/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 33a9ed5c24b..76d50b00b42 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -19,12 +19,14 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "cpu.h" #include "internal.h" #include "kvm_mips.h" #include "qemu/module.h" #include "sysemu/kvm.h" +#include "sysemu/qtest.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" @@ -158,6 +160,14 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) Error *local_err = NULL; if (!clock_get(cpu->clock)) { +#ifndef CONFIG_USER_ONLY + if (!qtest_enabled()) { + g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); + + warn_report("CPU input clock is not connected to any output clock, " + "using default frequency of %s.", cpu_freq_str); + } +#endif /* Initialize the frequency in case the clock remains unconnected. */ clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); } From patchwork Sat Oct 17 14:02:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E8BC14B5 for ; Sat, 17 Oct 2020 14:34:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D33F420708 for ; Sat, 17 Oct 2020 14:34:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ox3HtYJ7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D33F420708 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:40798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnHz-0001Da-Ux for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:34:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpd-0003oz-WA for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:14 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpc-0003tJ-Gc for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:13 -0400 Received: by mail-wr1-x430.google.com with SMTP id x7so6612438wrl.3 for ; Sat, 17 Oct 2020 07:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wDo4Ac8Bvr/h/F3tHmitZ/IsFCAT0CVJ5bwb+MZqKJo=; b=Ox3HtYJ77Ug7pnxuU5PZM59OE9hh3Os3xaqCyy/nJp+kjOJMh/FFrvAI1EqDx8v4RJ +XQVjOST/ZFTKpY5mhivLhnzeqqIew6LpQ1AvEedsKpbsWNuRElOsExiBG88wJZDQGqB xke3KR1EIuiP/ZEaKoPbzCsoebpCnOoTTp0WrNcbSTIo9c9VxnTuV0slpHTFxbQ2K4YX 04dqHRwg8ucFzgJazm0V/RjByyPkXk1bPZNqWsPdatkXDWA5JyjKpKBtAawbQWVIUq9Q 1pulf/z3jl8XCHyYLbYMnRV9uT656dN3/xmN6b3V2MF0KrcOGSfELp/qJR36uASfOkY0 6IhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wDo4Ac8Bvr/h/F3tHmitZ/IsFCAT0CVJ5bwb+MZqKJo=; b=Wp+WSZvpxnWLSfdGia81Gz109M9fxonvj8cm0Js0yQHUPQgxSOKNnYySAeTeFtBI84 f/Iq+K3rNCu0OYaW6VISimGF6ROJIYELI3wDBya4t2ynUhDoVjxCB8frpW+dn/3pGCGp NXViagBS6pYJS4WGyU8EIV/UQ1i9AaO4p5aLtcxE3MgjsM4H/gM32mZgpVDdNnMuoG6l jxJAqFiJ/bsZbz7L+jGmLRNNMIJi76aqmorsQL7mjMzyKQyc4iFfSh7Qt/BfhawpKRXz GJCedaztWhvP8Gt2xs5eUcCou6EFaY5Evv0nFPXLU6CmhQKRtmbU5ZmutJIVO91zLvBq Loqw== X-Gm-Message-State: AOAM5332QbrQUGoi/8lt5GpYASUPj02H5r1ougsiypxpsSo8zJexqqoa c5gw8Gr14LMQxetljggxrbGRmxakn+Q= X-Google-Smtp-Source: ABdhPJws1PIRtLZP1SPD/bJsJ3x0MEWSUD5aSYA4lJ0GnS05y4Gvxe0Oih/urz67IjnMoFgbQ6Sx0g== X-Received: by 2002:adf:a50e:: with SMTP id i14mr10379247wrb.121.1602943510674; Sat, 17 Oct 2020 07:05:10 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id p13sm7844630wmb.5.2020.10.17.07.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 31/44] hw/mips/malta: Fix FPGA I/O region size Date: Sat, 17 Oct 2020 16:02:30 +0200 Message-Id: <20201017140243.1078718-32-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The FPGA present on the CoreCard has an I/O region 1MiB wide. Refs: - Atlas User’s Manual (Document Number: MD00005) - Malta User’s Manual (Document Number: MD00048) Fixes: ea85df72b60 ("mips_malta: convert to memory API") Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20200905213049.761949-1-f4bug@amsat.org> --- hw/mips/malta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 1e2b750719e..a4a4c386268 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -578,7 +578,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", &s->iomem, 0, 0x900); memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", - &s->iomem, 0xa00, 0x10000 - 0xa00); + &s->iomem, 0xa00, 0x100000 - 0xa00); memory_region_add_subregion(address_space, base, &s->iomem_lo); memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); From patchwork Sat Oct 17 14:02:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842793 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E30A514B4 for ; Sat, 17 Oct 2020 14:25:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95D4420657 for ; Sat, 17 Oct 2020 14:25:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pt8GE+Kb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 95D4420657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:44340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn9Z-0007Ja-Ko for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:25:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpi-0003uE-KG for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:19 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34398) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmph-0003ut-1f for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:18 -0400 Received: by mail-wr1-x444.google.com with SMTP id i1so6609300wro.1 for ; Sat, 17 Oct 2020 07:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Ewc141UoMMZXp239BJOBQyclagaXr5vDLAwNvdaTwE=; b=Pt8GE+Kbr0H46mFNuSl9XlxOxkatk5AliYhHgOlEhrZxzYWPRG2CKoYh5zcJ4OqCu1 CRJWpZeL2NHOVONLBicrH87Oxp82a96RXzauCM9wHi59d9WCNQ+vi8BmNibFg+YF50Pv t/ni+OoQQ25DtIl34g1PHDYuucJctuXQN6/6ko20ZN/Gb9w0t2FfPLtAfsrgGlyXLW4N 2r+aPb7H65N3hHElfkBHecHhE0xfw+0njbmRcsIAZbiqA4zHzYCLVeEDWHPnIY8aWUdv U9pt8qJQc8XiAD6t225kUqDSIH4WAAkNiJMkQB57Wj9QLsPr6Qn8YQkkM4P+nRZMHrO/ zC3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8Ewc141UoMMZXp239BJOBQyclagaXr5vDLAwNvdaTwE=; b=pSb8fSMkMelr+jx+NOMK7FJ+kTcZlnbqEuSNKzlk0L3NJOZCHVGM6fB4GI+1dCs5P9 pKDvhlFBR4F7xEwkOLfCxpYZ9LbqMZmPC4VMGQ0M6cq3rblChEPi8FldYqqROQ45hlWt n8lzPhEXhWYXuiU6Uv0C0ulMd0RIyit2cHlj2sYNaf6UzEATwYuRihwqUwpA9Xmm3gJQ +x6nBYyaPJ67urk/IPLYJOGiJ3nRkKWp9Ghv46OlAdz/Q+J3AOsmgMORlqDOdB3O92Va TzWaTbivJHMJshutG5WEIA+YtOng3dP57rmnnGjUe0L1XtBATL/IvnfnzniSpUei6BRu FGcA== X-Gm-Message-State: AOAM533DyXrV+cRkCEJlljPEZs0Zp5l2lgujsJm9pKMa4S8y/fSBjsWJ /KVU8/Ocw+/D8rbWmyxqSyvMBvRMsfc= X-Google-Smtp-Source: ABdhPJyCR3LaJnL3t89ztgrWpjhTPSzEmSGQFl+sk2JmpxBE8Yf6K5RXwxvyi0kx8U94dqtYmbeDJg== X-Received: by 2002:a05:6000:81:: with SMTP id m1mr10518028wrx.67.1602943515522; Sat, 17 Oct 2020 07:05:15 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id j9sm9162391wrp.59.2020.10.17.07.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 32/44] hw/mips/malta: Move gt64120 related code together Date: Sat, 17 Oct 2020 16:02:31 +0200 Message-Id: <20201017140243.1078718-33-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The 'empty_slot' region created is related to the gt64120. Move its creation close to the gt64120 instance creation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201012160503.3472140-2-f4bug@amsat.org> --- hw/mips/malta.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a4a4c386268..944045d7701 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1239,13 +1239,6 @@ void mips_malta_init(MachineState *machine) DeviceState *dev = qdev_new(TYPE_MIPS_MALTA); MaltaState *s = MIPS_MALTA(dev); - /* - * The whole address space decoded by the GT-64120A doesn't generate - * exception when accessing invalid memory. Create an empty slot to - * emulate this feature. - */ - empty_slot_init("GT64120", 0, 0x20000000); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* create CPU */ @@ -1399,6 +1392,12 @@ void mips_malta_init(MachineState *machine) /* Northbridge */ pci_bus = gt64120_register(s->i8259); + /* + * The whole address space decoded by the GT-64120A doesn't generate + * exception when accessing invalid memory. Create an empty slot to + * emulate this feature. + */ + empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ dev = piix4_create(pci_bus, &isa_bus, &smbus); From patchwork Sat Oct 17 14:02:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842799 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04D1D17CA for ; Sat, 17 Oct 2020 14:27:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B56E520657 for ; Sat, 17 Oct 2020 14:27:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jYBQ4BEK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B56E520657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnBV-0001W4-Kf for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:27:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpo-00046Y-FG for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:24 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:41367) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpm-0003z1-S8 for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:24 -0400 Received: by mail-wr1-x430.google.com with SMTP id s9so6561702wro.8 for ; Sat, 17 Oct 2020 07:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KkzjSFScIeOvIHF/kF8jPGG8E3yTqTBPtxI+D53JLeI=; b=jYBQ4BEKTh8kCYMjdPjLZtmWcnRefWvp967sxK+tfjl5IesMkqw+W7FOJFsq+rlUL8 f/oJHwXi/9bmDDKaYJovE3iCFhFNbWVAjg8zR44xlG5Pb54d8BN1C7bqY6Ye2idfX1bt LBEGW0gAQenLHdHub7sr1n7c4UdQ4OPALLRKAHz5KEKhqvNSoP/+JazgPUh4/snXeSz3 v6Lc3VVNMlTc5nDi6AQCzYPjY0GdWaZ0Rs7yIC4X2qLdncwhtpm0F/7Q0bWs0j6L5qQm 2w3BdTcKa6zz0RGUpGnWTzyGniiqoPWmamjE1JK7RWgqyY11lgaWcQXsu0vdkJm9k/Y/ srKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KkzjSFScIeOvIHF/kF8jPGG8E3yTqTBPtxI+D53JLeI=; b=hBpyOgJ+z0vMYRJ8u44BKjtr2WQNCgKV+0nWSQp1CXvwW2evqFz5+MLmEMT8toPoEx e6Qa/OAzkUkzLGUlV8egZ42trII8z7EEAh3djAm7I5AivqfzbnoDEzfI/U57tW/D/f2p XyupI8C0YGo/nHisAyKTIzCtkPlJw0MxUosayS9bWe5MGU2FZb6pxy+YpVR2DAsN6HlI up3O/OWXB6SvcvxZmGdir9Q0EG2CpgMd53cOXmbFKf6l71HeJ8424gCFCNh0P3HcSBNM vYMjm7xhIbCeI91uCx28jhsvnrMnYevdV4z1djhnukleGtOKW9JpHyy4dXRUk/Zax4CW 3SfQ== X-Gm-Message-State: AOAM533bRNeDOFAJooPxpAzMiFUCW4Ei7rlFw+GHwz5B5yzBkTM3ObeG 4gsGYUURabUxJs/CGv4kfk2G1CFfRm8= X-Google-Smtp-Source: ABdhPJxKQFboNrStLicnmTgxcUWCi3KKpX6hw+lzpcdgj432g7otPb4sAUn78h0+StCYZz0lWiOtAg== X-Received: by 2002:adf:e5cf:: with SMTP id a15mr9917414wrn.186.1602943520242; Sat, 17 Oct 2020 07:05:20 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id g83sm7477018wmf.15.2020.10.17.07.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 33/44] hw/mips/malta: Use clearer qdev style Date: Sat, 17 Oct 2020 16:02:32 +0200 Message-Id: <20201017140243.1078718-34-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In order to be consistent with the other code base uses, rewrite slightly how the MIPS_MALTA object is created. No logical change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201012160503.3472140-3-f4bug@amsat.org> --- hw/mips/malta.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 944045d7701..ff3225bb8e3 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1235,11 +1235,11 @@ void mips_malta_init(MachineState *machine) DriveInfo *dinfo; int fl_idx = 0; int be; + MaltaState *s; + DeviceState *dev; - DeviceState *dev = qdev_new(TYPE_MIPS_MALTA); - MaltaState *s = MIPS_MALTA(dev); - - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); /* create CPU */ mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); From patchwork Sat Oct 17 14:02:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E90614B4 for ; Sat, 17 Oct 2020 14:15:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2FA420704 for ; Sat, 17 Oct 2020 14:15:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iUcTr3z6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2FA420704 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:40682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTmzs-0002Ik-Ix for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:15:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmps-0004Gt-7Z for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:28 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:43719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpq-0003zb-DO for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:27 -0400 Received: by mail-wr1-x432.google.com with SMTP id g12so6557076wrp.10 for ; Sat, 17 Oct 2020 07:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4E8kG4ILRSk7MsJbvzjJRPB5rdnj2Bu4UJI6JB3HuIQ=; b=iUcTr3z67+6NWNFjA7GDPK4xAEXZT/ImzFGxJEiBeQOurmkUgkmsPOWlluFg2sbsPG VqUWHPP4OREMQW2mq0vwsBeN9TE0zcRMpNaN7K8A5aPKUxiyUJBZc5e1aMnQQyjPK0p5 GeR2S7KF+7KuBNxNNteu8BiX8nx7VHAtNq8e2MRpWoL9bhrV9Mn3IvyXVy/63g9lXpPW KEFdkiofDn3rETSsX1BGkFTQy2Fu4z8bJ3yML1eDTIrJErAmDR0OJADK2pyAFsdi2B1h Ett0+KMx2mJ3FPobFrXvSZ3sFziHSz0p+ez1+gxUc6A/41KBXsCs1MWyGGdeJjeLgAou q99Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4E8kG4ILRSk7MsJbvzjJRPB5rdnj2Bu4UJI6JB3HuIQ=; b=T+eS3iyc54ObDVHJhr98OYa3egRYDKHMLxkZF4GT8Ukts9v2Nd2zSCbkM3goSNKvN7 FIu+uWzOGUzHcJZAR2ShYgs+EzjkJCBqxke+J2E9S5zZ6QoAYGKma8FcqSRIr5mqy0AQ DrNK+u+PDiud6LKDLwM7g4sbMz8I4fmKAhBUPu/RbshZRFHjdzuHOSU6aT5t8zFZuaMu u5QF/4YYaviWm9kvh0fYUamnPJyAlw++KkRaGaz18zJ82/LsinABYAapCJFMbSPl3myy H64ceMyYD+04i0vWNz8szytgXNtiIgMEZvYGRbKezXg04qXm47PH65Ymbnd/p70iRzJB C7HQ== X-Gm-Message-State: AOAM533tirwtHqIeJvgMNaSW0lSAb+Na9E9/CqQ/HU6XUKM4f2z/PrX6 Rz8HGDerPRiJuji4JdDodpV5ltg6DGA= X-Google-Smtp-Source: ABdhPJy062B0Et3e5Fm/WJ0XhHay2TILDCL+FijssvofiueYvzkbfq5IOZb5gfP7smUTo1VQpn3VNQ== X-Received: by 2002:adf:f3cb:: with SMTP id g11mr10886090wrp.210.1602943524903; Sat, 17 Oct 2020 07:05:24 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id o129sm7229274wmb.25.2020.10.17.07.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 34/44] hw/mips: Simplify loading 64-bit ELF kernels Date: Sat, 17 Oct 2020 16:02:33 +0200 Message-Id: <20201017140243.1078718-35-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Since 82790064116 ("Cast ELF datatypes properly to host 64bit types") we don't need to sign-extend the entry_point address. Remove this unnecessary code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20200927163943.614604-2-f4bug@amsat.org> --- hw/mips/mipssim.c | 6 +----- hw/mips/r4k.c | 6 +----- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index f0042f7f436..afef4f2e77a 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -77,11 +77,7 @@ static int64_t load_kernel(void) (uint64_t *)&entry, NULL, (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS, 1, 0); - if (kernel_size >= 0) { - if ((entry & ~0x7fffffffULL) == 0x80000000) { - entry = (int32_t)entry; - } - } else { + if (kernel_size < 0) { error_report("could not load kernel '%s': %s", loaderparams.kernel_filename, load_elf_strerror(kernel_size)); diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c index 39bc626e7c5..7ee37c49689 100644 --- a/hw/mips/r4k.c +++ b/hw/mips/r4k.c @@ -102,11 +102,7 @@ static int64_t load_kernel(void) (uint64_t *)&entry, NULL, (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS, 1, 0); - if (kernel_size >= 0) { - if ((entry & ~0x7fffffffULL) == 0x80000000) { - entry = (int32_t)entry; - } - } else { + if (kernel_size < 0) { error_report("could not load kernel '%s': %s", loaderparams.kernel_filename, load_elf_strerror(kernel_size)); From patchwork Sat Oct 17 14:02:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842809 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6E1E14B4 for ; Sat, 17 Oct 2020 14:29:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A627720657 for ; Sat, 17 Oct 2020 14:29:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dj1g7CUa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A627720657 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnDX-00049S-RD for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:29:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmpx-0004TE-0q for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:33 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54106) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmpv-00040a-6e for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:32 -0400 Received: by mail-wm1-x342.google.com with SMTP id f21so6140835wml.3 for ; Sat, 17 Oct 2020 07:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bt4oVFiiKF8ndprKkDoZPz+ozlge1hSxtT3OwSh/bHU=; b=dj1g7CUaMqX1C9a9Dv6DxW9I6/lfX6YWm4e1j8eV0sM4WoSB7umnyUa8ZFJkGx+UI0 ZR6XFCJGOBAOQXHpkc7zg5F0Rlzu6gLXnQgGihXHW8YOF3Ey3xtme6dmfjm3xaGN4A3F xNODDjq/5FjX71Z2/Zl9MY2UF2Ae8EuN9Pg74bhiMp+NtErQ8y8Yl5KoEmcKR6f/Egxt jZ53ej5Ib9EPTEmB5ZWjtncMEIgKhh+F6gu9i3dTrK7COyJayZNSvlWgyplVfTOT4uqB 6W6qzSdK9tou4X0l/MpdTlnS6CWI5G+4c18uWc38294G1Z/dU/lomMXUkRlDnBnBbioL RLKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Bt4oVFiiKF8ndprKkDoZPz+ozlge1hSxtT3OwSh/bHU=; b=G8O/GZyHq5UQuZ3NIHzdFUS0ciEAIL6DkRVK/IcuHfiFDwEgbbf4wWI0VWHsvS4Tme kGpOKhahZI2R9zPHQlk8KbCrp9bGAbN66/xvQFrqQAmNyX939enQt4rFPuFZyiVHqnaf J+khwXgbSWcq2dEbR1VubGAc8W6ulfugAUiDUTT2V69KAR4K39kXnVimMi3sgBPkObQB KoRdFffYsOnSW0/m/Qjsk2arYDdmFEUnSo5eukREOG/nYLbGnsv62BdhlHIFI5QCqZom 7E22/50MmdmToTF1fjcEIF/louqNlZT/ByURjAcRAjk25ONtUwiVhVWUPUJXsKEXKwax BXhQ== X-Gm-Message-State: AOAM532JnqoQEnaK6AoE9s2SPN0hxs+nNY8VpqIAMaY4x4E8UE1TWhvs R2Ai4UWk42bkIm9oCQ/DUZ4s1DR66lg= X-Google-Smtp-Source: ABdhPJw+zfUVnonjZrl9qJe5J05dKOVnePJdxGV9kyOZYKmqTxzOeg9qFj7gFA3cPHB7VEQMN1wasQ== X-Received: by 2002:a1c:4006:: with SMTP id n6mr8459943wma.46.1602943529605; Sat, 17 Oct 2020 07:05:29 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id c18sm8821587wrt.10.2020.10.17.07.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 35/44] hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE) Date: Sat, 17 Oct 2020 16:02:34 +0200 Message-Id: <20201017140243.1078718-36-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Instead of using a INITRD_PAGE_MASK definition, use the simpler INITRD_PAGE_SIZE one which allows us to simplify the code by using directly the self-explicit ROUND_UP() macro. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20200927163943.614604-3-f4bug@amsat.org> --- include/hw/mips/mips.h | 4 +++- hw/mips/fuloong2e.c | 3 +-- hw/mips/malta.c | 6 +++--- hw/mips/mipssim.c | 3 +-- hw/mips/r4k.c | 3 +-- 5 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 0af4c3d5d74..6c9c8805f3f 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -2,8 +2,10 @@ #define HW_MIPS_H /* Definitions for mips board emulation. */ +#include "qemu/units.h" + /* Kernels can be configured with 64KB pages */ -#define INITRD_PAGE_MASK (~((1 << 16) - 1)) +#define INITRD_PAGE_SIZE (64 * KiB) #include "exec/memory.h" diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index b8234f61083..de66215f95f 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -133,8 +133,7 @@ static int64_t load_kernel(CPUMIPSState *env) if (loaderparams.initrd_filename) { initrd_size = get_image_size(loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & - INITRD_PAGE_MASK; + initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE); if (initrd_offset + initrd_size > ram_size) { error_report("memory too small for initial ram disk '%s'", loaderparams.initrd_filename); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ff3225bb8e3..beb0f43941a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1077,9 +1077,9 @@ static int64_t load_kernel(void) * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB * pages. */ - initrd_offset = (loaderparams.ram_low_size - initrd_size - - (128 * KiB) - - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; + initrd_offset = ROUND_UP(loaderparams.ram_low_size + - (initrd_size + 128 * KiB), + INITRD_PAGE_SIZE); if (kernel_high >= initrd_offset) { error_report("memory too small for initial ram disk '%s'", loaderparams.initrd_filename); diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index afef4f2e77a..97dcc232476 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -90,8 +90,7 @@ static int64_t load_kernel(void) if (loaderparams.initrd_filename) { initrd_size = get_image_size(loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & - INITRD_PAGE_MASK; + initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE); if (initrd_offset + initrd_size > loaderparams.ram_size) { error_report("memory too small for initial ram disk '%s'", loaderparams.initrd_filename); diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c index 7ee37c49689..38308543421 100644 --- a/hw/mips/r4k.c +++ b/hw/mips/r4k.c @@ -115,8 +115,7 @@ static int64_t load_kernel(void) if (loaderparams.initrd_filename) { initrd_size = get_image_size(loaderparams.initrd_filename); if (initrd_size > 0) { - initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & - INITRD_PAGE_MASK; + initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE); if (initrd_offset + initrd_size > ram_size) { error_report("memory too small for initial ram disk '%s'", loaderparams.initrd_filename); From patchwork Sat Oct 17 14:02:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842821 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB04D15E6 for ; Sat, 17 Oct 2020 14:37:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6843820708 for ; Sat, 17 Oct 2020 14:37:11 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id v189sm7976153wmg.14.2020.10.17.07.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 36/44] hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON Date: Sat, 17 Oct 2020 16:02:35 +0200 Message-Id: <20201017140243.1078718-37-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Eduardo Habkost , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost This will make the type name constant consistent with the name of the type checking macro. Signed-off-by: Eduardo Habkost Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cf2296f4488..74c18edbb34 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -44,10 +44,10 @@ #include #include "qom/object.h" -#define TYPE_MIPS_BOSTON "mips-boston" +#define TYPE_BOSTON "mips-boston" typedef struct BostonState BostonState; DECLARE_INSTANCE_CHECKER(BostonState, BOSTON, - TYPE_MIPS_BOSTON) + TYPE_BOSTON) struct BostonState { SysBusDevice parent_obj; @@ -262,7 +262,7 @@ static void mips_boston_instance_init(Object *obj) } static const TypeInfo boston_device = { - .name = TYPE_MIPS_BOSTON, + .name = TYPE_BOSTON, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BostonState), .instance_init = mips_boston_instance_init, @@ -455,7 +455,7 @@ static void boston_mach_init(MachineState *machine) exit(1); } - dev = qdev_new(TYPE_MIPS_BOSTON); + dev = qdev_new(TYPE_BOSTON); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); s = BOSTON(dev); From patchwork Sat Oct 17 14:02:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842815 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0F0117CA for ; Sat, 17 Oct 2020 14:32:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5370E2073A for ; Sat, 17 Oct 2020 14:32:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JKUc/F0M" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5370E2073A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnFe-00073Q-Gr for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:32:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmq6-0004pA-Hy for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:42 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:56097) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmq4-00045W-Qk for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:42 -0400 Received: by mail-wm1-x329.google.com with SMTP id a72so6128172wme.5 for ; Sat, 17 Oct 2020 07:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AHKgFTwyonlJMqUSo/VQEjDBt8yNtjw9Fbnqm+Zig2A=; b=JKUc/F0ME2xaE+SsbpW6aq8Xb+cFkNBz4zNuxePa3VgSfgTvGOtbB0gYRaqFxY0JxT dFPWcXYNCNAo1kc/iH+W58i2WF86sYEZxrYCnus9T2SW9ii/YdAAzzp9eipL3Hpv++lY uW2M0hx2IekSLiWSOhoapNFdJ6pcvdBBaqr3HO65sQKULRjwNoP4ahcoQGVaOL+Eq3sm ZP0UztDTu/4WT7QEYCJM7iBmosYxBRFo/o8BCdfLjDVD8WlfpxHJYuN4uE1VXxQzB+ru tAtNESc+MxzsTcHSPFzLhCZQb4asPUF5z+cS4U5x5fwUGcuQZ/Xw4p8lHdOWqX7GNMqx kZsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AHKgFTwyonlJMqUSo/VQEjDBt8yNtjw9Fbnqm+Zig2A=; b=glJNZJS7VoFV8Gv3Io6XNS1FzMDDTAZ0maDCgr6+tK7DNCfeJcS3oda5RVM1udVFGn MCLrw7GAicE8GhoZf47UiY21As96i9qx1we3pXL9oZdAED1jLK4HmiTEnAEK9kCRPQtR mgI/mtY5Hwg1u+qyeOGHzjGY91t7QK5dbHbMaGtPYohhWr2Suw7F3cL8oGQ9j3PQjBmq DHyUcrucVPb03RbUoyF8t8fKtTfVij4213a6asJlrqM+9X0IKBwmIMbJVutKOVoK63Fn QF5N5ZLofiqKIAz0ny7HibLfpK809x0rMu75qOwsR8VOS1ux8YvdBYqDpLZB+rL98kJP 4lpg== X-Gm-Message-State: AOAM532oSnh7KyC9gRNRM29VT4ZnTV5M1CF+X2VF2WJIIX8sD7j/k8nY i1hPBKBvagcv2JUnTWZNmRVLldw6Y3M= X-Google-Smtp-Source: ABdhPJziIqazOQvmXQvGUIrrm0X3L/uh1C92KlG2t5MI5XxWjIevMoNtG4CJvuHoiZ9Cf7pBWDT73Q== X-Received: by 2002:a1c:bc03:: with SMTP id m3mr8929428wmf.171.1602943539165; Sat, 17 Oct 2020 07:05:39 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id r1sm9098034wro.18.2020.10.17.07.05.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 37/44] hw/mips: Remove exit(1) in case of missing ROM Date: Sat, 17 Oct 2020 16:02:36 +0200 Message-Id: <20201017140243.1078718-38-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Pavel Dovgalyuk , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Pavel Dovgalyuk This patch updates MIPS-based machines to allow starting them without ROM. In this case CPU starts to execute instructions from the empty memory, but QEMU allows introspecting the machine configuration. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 8 +++----- hw/mips/jazz.c | 8 +++----- hw/mips/malta.c | 11 ++++------- hw/mips/mipssim.c | 10 +++------- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index de66215f95f..a9e0c2f8d30 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -337,10 +337,8 @@ static void mips_fuloong2e_init(MachineState *machine) kernel_entry = load_kernel(env); write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); } else { - if (bios_name == NULL) { - bios_name = FULOONG_BIOSNAME; - } - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, + bios_name ?: FULOONG_BIOSNAME); if (filename) { bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE); @@ -350,7 +348,7 @@ static void mips_fuloong2e_init(MachineState *machine) } if ((bios_size < 0 || bios_size > BIOS_SIZE) && - !kernel_filename && !qtest_enabled()) { + bios_name && !qtest_enabled()) { error_report("Could not load MIPS bios '%s'", bios_name); exit(1); } diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 8f1ad55ba34..71448f72ac9 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -218,10 +218,7 @@ static void mips_jazz_init(MachineState *machine, memory_region_add_subregion(address_space, 0xfff00000LL, bios2); /* load the BIOS image. */ - if (bios_name == NULL) { - bios_name = BIOS_FILENAME; - } - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name ?: BIOS_FILENAME); if (filename) { bios_size = load_image_targphys(filename, 0xfff00000LL, MAGNUM_BIOS_SIZE); @@ -229,7 +226,8 @@ static void mips_jazz_init(MachineState *machine, } else { bios_size = -1; } - if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) { + if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) + && bios_name && !qtest_enabled()) { error_report("Could not load MIPS bios '%s'", bios_name); exit(1); } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index beb0f43941a..9d1a3b50b7a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1332,10 +1332,8 @@ void mips_malta_init(MachineState *machine) /* Load firmware from flash. */ if (!dinfo) { /* Load a BIOS image. */ - if (bios_name == NULL) { - bios_name = BIOS_FILENAME; - } - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, + bios_name ?: BIOS_FILENAME); if (filename) { bios_size = load_image_targphys(filename, FLASH_ADDRESS, BIOS_SIZE); @@ -1344,9 +1342,8 @@ void mips_malta_init(MachineState *machine) bios_size = -1; } if ((bios_size < 0 || bios_size > BIOS_SIZE) && - !kernel_filename && !qtest_enabled()) { - error_report("Could not load MIPS bios '%s', and no " - "-kernel argument was specified", bios_name); + bios_name && !qtest_enabled()) { + error_report("Could not load MIPS bios '%s'", bios_name); exit(1); } } diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 97dcc232476..aaa62a0f4b7 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -177,10 +177,7 @@ mips_mipssim_init(MachineState *machine) /* Map the BIOS / boot exception handler. */ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); /* Load a BIOS / boot exception handler image. */ - if (bios_name == NULL) { - bios_name = BIOS_FILENAME; - } - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name ?: BIOS_FILENAME); if (filename) { bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE); g_free(filename); @@ -188,10 +185,9 @@ mips_mipssim_init(MachineState *machine) bios_size = -1; } if ((bios_size < 0 || bios_size > BIOS_SIZE) && - !kernel_filename && !qtest_enabled()) { + bios_name && !qtest_enabled()) { /* Bail out if we have neither a kernel image nor boot vector code. */ - error_report("Could not load MIPS bios '%s', and no " - "-kernel argument was specified", bios_name); + error_report("Could not load MIPS bios '%s'", bios_name); exit(1); } else { /* We have a boot vector start address. */ From patchwork Sat Oct 17 14:02:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842819 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A2AB14B5 for ; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id v189sm7976682wmg.14.2020.10.17.07.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 38/44] tests/acceptance: Add MIPS record/replay tests Date: Sat, 17 Oct 2020 16:02:37 +0200 Message-Id: <20201017140243.1078718-39-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -9 X-Spam_score: -1.0 X-Spam_bar: - X-Spam_report: (-1.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, PDS_BTC_ID=0.499, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Pavel Dovgalyuk , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Pavel Dovgalyuk This patch adds MIPS-targeted acceptance tests for record/replay functions. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <160276110297.2705.10918105269658307206.stgit@pasha-ThinkPad-X280> [PMD: Moved 'override timeout' comment from instance to class, moved nanomips tests to ReplayKernelSlow class, tagged ReplayKernelSlow class with AVOCADO_TIMEOUT_EXPECTED] Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/replay_kernel.py | 167 +++++++++++++++++++++++++++++- 1 file changed, 166 insertions(+), 1 deletion(-) diff --git a/tests/acceptance/replay_kernel.py b/tests/acceptance/replay_kernel.py index 952f429cace..00c228382bd 100644 --- a/tests/acceptance/replay_kernel.py +++ b/tests/acceptance/replay_kernel.py @@ -9,6 +9,8 @@ # later. See the COPYING file in the top-level directory. import os +import lzma +import shutil import logging import time @@ -19,7 +21,7 @@ from avocado.utils import process from boot_linux_console import LinuxKernelTest -class ReplayKernel(LinuxKernelTest): +class ReplayKernelBase(LinuxKernelTest): """ Boots a Linux kernel in record mode and checks that the console is operational and the kernel command line is properly passed @@ -74,6 +76,7 @@ def run_rr(self, kernel_path, kernel_command_line, console_pattern, logger = logging.getLogger('replay') logger.info('replay overhead {:.2%}'.format(t2 / t1 - 1)) +class ReplayKernelNormal(ReplayKernelBase): @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') def test_x86_64_pc(self): """ @@ -91,6 +94,51 @@ def test_x86_64_pc(self): self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5) + def test_mips_malta(self): + """ + :avocado: tags=arch:mips + :avocado: tags=machine:malta + :avocado: tags=endian:big + """ + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20130217T032700Z/pool/main/l/linux-2.6/' + 'linux-image-2.6.32-5-4kc-malta_2.6.32-48_mips.deb') + deb_hash = 'a8cfc28ad8f45f54811fc6cf74fc43ffcfe0ba04' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinux-2.6.32-5-4kc-malta') + kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0' + console_pattern = 'Kernel command line: %s' % kernel_command_line + + self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5) + + def test_mips64el_malta(self): + """ + This test requires the ar tool to extract "data.tar.gz" from + the Debian package. + + The kernel can be rebuilt using this Debian kernel source [1] and + following the instructions on [2]. + + [1] http://snapshot.debian.org/package/linux-2.6/2.6.32-48/ + #linux-source-2.6.32_2.6.32-48 + [2] https://kernel-team.pages.debian.net/kernel-handbook/ + ch-common-tasks.html#s-common-official + + :avocado: tags=arch:mips64el + :avocado: tags=machine:malta + """ + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20130217T032700Z/pool/main/l/linux-2.6/' + 'linux-image-2.6.32-5-5kc-malta_2.6.32-48_mipsel.deb') + deb_hash = '1aaec92083bf22fda31e0d27fa8d9a388e5fc3d5' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinux-2.6.32-5-5kc-malta') + kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0' + console_pattern = 'Kernel command line: %s' % kernel_command_line + self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5) + def test_aarch64_virt(self): """ :avocado: tags=arch:aarch64 @@ -302,3 +350,120 @@ def test_xtensa_lx60(self): file_path = self.fetch_asset(tar_url, asset_hash=tar_hash) self.do_test_advcal_2018(file_path, 'santas-sleigh-ride.elf', args=('-cpu', 'dc233c')) + +@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout') +class ReplayKernelSlow(ReplayKernelBase): + # Override the timeout, because this kernel includes an inner + # loop which is executed with TB recompilings during replay, + # making it very slow. + timeout = 180 + + def test_mips_malta_cpio(self): + """ + :avocado: tags=arch:mips + :avocado: tags=machine:malta + :avocado: tags=endian:big + :avocado: tags=slowness:high + """ + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20160601T041800Z/pool/main/l/linux/' + 'linux-image-4.5.0-2-4kc-malta_4.5.5-1_mips.deb') + deb_hash = 'a3c84f3e88b54e06107d65a410d1d1e8e0f340f8' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinux-4.5.0-2-4kc-malta') + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' + '8584a59ed9e5eb5ee7ca91f6d74bbb06619205b8/rootfs/' + 'mips/rootfs.cpio.gz') + initrd_hash = 'bf806e17009360a866bf537f6de66590de349a99' + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) + initrd_path = self.workdir + "rootfs.cpio" + archive.gzip_uncompress(initrd_path_gz, initrd_path) + + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0 console=tty ' + 'rdinit=/sbin/init noreboot') + console_pattern = 'Boot successful.' + self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5, + args=('-initrd', initrd_path)) + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') + def test_mips64el_malta_5KEc_cpio(self): + """ + :avocado: tags=arch:mips64el + :avocado: tags=machine:malta + :avocado: tags=endian:little + :avocado: tags=slowness:high + """ + kernel_url = ('https://github.com/philmd/qemu-testing-blob/' + 'raw/9ad2df38/mips/malta/mips64el/' + 'vmlinux-3.19.3.mtoman.20150408') + kernel_hash = '00d1d268fb9f7d8beda1de6bebcc46e884d71754' + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) + initrd_url = ('https://github.com/groeck/linux-build-test/' + 'raw/8584a59e/rootfs/' + 'mipsel64/rootfs.mipsel64r1.cpio.gz') + initrd_hash = '1dbb8a396e916847325284dbe2151167' + initrd_path_gz = self.fetch_asset(initrd_url, algorithm='md5', + asset_hash=initrd_hash) + initrd_path = self.workdir + "rootfs.cpio" + archive.gzip_uncompress(initrd_path_gz, initrd_path) + + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'console=ttyS0 console=tty ' + 'rdinit=/sbin/init noreboot') + console_pattern = 'Boot successful.' + self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5, + args=('-initrd', initrd_path, '-cpu', '5KEc')) + + def do_test_mips_malta32el_nanomips(self, kernel_path_xz): + kernel_path = self.workdir + "kernel" + with lzma.open(kernel_path_xz, 'rb') as f_in: + with open(kernel_path, 'wb') as f_out: + shutil.copyfileobj(f_in, f_out) + + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + + 'mem=256m@@0x0 ' + 'console=ttyS0') + console_pattern = 'Kernel command line: %s' % kernel_command_line + self.run_rr(kernel_path, kernel_command_line, console_pattern, shift=5, + args=('-cpu', 'I7200')) + + def test_mips_malta32el_nanomips_4k(self): + """ + :avocado: tags=arch:mipsel + :avocado: tags=machine:malta + :avocado: tags=endian:little + """ + kernel_url = ('https://mipsdistros.mips.com/LinuxDistro/nanomips/' + 'kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/' + 'generic_nano32r6el_page4k.xz') + kernel_hash = '477456aafd2a0f1ddc9482727f20fe9575565dd6' + kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash) + self.do_test_mips_malta32el_nanomips(kernel_path_xz) + + def test_mips_malta32el_nanomips_16k_up(self): + """ + :avocado: tags=arch:mipsel + :avocado: tags=machine:malta + :avocado: tags=endian:little + """ + kernel_url = ('https://mipsdistros.mips.com/LinuxDistro/nanomips/' + 'kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/' + 'generic_nano32r6el_page16k_up.xz') + kernel_hash = 'e882868f944c71c816e832e2303b7874d044a7bc' + kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash) + self.do_test_mips_malta32el_nanomips(kernel_path_xz) + + def test_mips_malta32el_nanomips_64k_dbg(self): + """ + :avocado: tags=arch:mipsel + :avocado: tags=machine:malta + :avocado: tags=endian:little + """ + kernel_url = ('https://mipsdistros.mips.com/LinuxDistro/nanomips/' + 'kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/' + 'generic_nano32r6el_page64k_dbg.xz') + kernel_hash = '18d1c68f2e23429e266ca39ba5349ccd0aeb7180' + kernel_path_xz = self.fetch_asset(kernel_url, asset_hash=kernel_hash) + self.do_test_mips_malta32el_nanomips(kernel_path_xz) From patchwork Sat Oct 17 14:02:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842769 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4823B15E6 for ; Sat, 17 Oct 2020 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id u195sm7587193wmu.18.2020.10.17.07.05.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 39/44] docs/system: Update MIPS CPU documentation Date: Sat, 17 Oct 2020 16:02:38 +0200 Message-Id: <20201017140243.1078718-40-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Huacai Chen Add Loongson-3A CPU models description. Signed-off-by: Huacai Chen Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com> [PMD: Split patch in 2: CPU / machine] Signed-off-by: Philippe Mathieu-Daudé --- docs/system/cpu-models-mips.rst.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc index 499b5b6fedb..02cc4bb884c 100644 --- a/docs/system/cpu-models-mips.rst.inc +++ b/docs/system/cpu-models-mips.rst.inc @@ -48,11 +48,17 @@ across all desired hosts. ``I6400`` MIPS64 Processor (Release 6, 2014) +``Loongson-2E`` + MIPS64 Processor (Loongson 2, 2006) + ``Loongson-2F`` MIPS64 Processor (Loongson 2, 2008) -``Loongson-2E`` - MIPS64 Processor (Loongson 2, 2006) +``Loongson-3A1000`` + MIPS64 Processor (Loongson 3, 2010) + +``Loongson-3A4000`` + MIPS64 Processor (Loongson 3, 2018) ``mips64dspr2`` MIPS64 Processor (Release 2, 2006) From patchwork Sat Oct 17 14:02:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842775 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A772915E6 for ; Sat, 17 Oct 2020 14:19:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A07E20714 for ; Sat, 17 Oct 2020 14:19:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P7XiCO+O" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6A07E20714 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:55580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn3M-0008Sj-Ip for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:19:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmqJ-000537-Ub for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:56 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:38770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmqI-00047W-Ap for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:05:55 -0400 Received: by mail-wm1-x329.google.com with SMTP id b127so8382777wmb.3 for ; Sat, 17 Oct 2020 07:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iuO8xvBpXep6eLb/F7St0rc68Indv4ZsZQ0L+M/FNuI=; b=P7XiCO+Oetyfs+aDoX6OecYt24LulPbyceXndHiTY11Mdg6H2DnGpYcELidRXH4+Y+ 7N+TbKu0NFoCkVYVNWbvNlrGd2RfpG9rI4vHv1j53lx1Ts7KsNzY3d14ABLVbk2/+YxC cNPLAs0PP4X7cbRecK2aWDVg0WzGUyBtclJTQ44jneI2IA+E645sMxye0pkTOn/4Io6M NbjFDFU0tbQRVf8WO1XaScl8NWExdkLZPyhBTSkxPmaRlYoqKxo+wTf0aysCktAobQSo G3PfYbsPg/L/lHrILoQgv9yPUzkMR3wmkd7HZ73VUaPWPSW0wH2TMkRBWJ7RXNpWT7Vj cYxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iuO8xvBpXep6eLb/F7St0rc68Indv4ZsZQ0L+M/FNuI=; b=OiQxYJ+VdarLUiZRCATAmv3sUElOCI7EMK1jfFkyCZu75LMmnJpZG2GPgDNzo0WcaK bD5kVugl1WR1wkj1NT7nCFPs9NHkekljO/6jWBpvLcZaTerGjckP5DfH+w4xJ74jrskm qgxy/X2on/LcWWYS60gLLQnnixYF/YJvt1G7t3JFrYbqe++yVhFSYJ9n4SoVOQJ4/XNh 3x42ZHW26R4iW34S+hpstCaK2mFln1f2Tt2uY8O+pdeE3O/1RRB+YdF/2pyMjHvzUyVq 29INkc3szfqIz+qBmSCxHgGrUfPV6wI3+GWFZfEFZkYJjIxfbyPpi8NyjXt2AypuOUsC exlg== X-Gm-Message-State: AOAM532UCJsGo/5oPSLyJi1/IE2NHicqr8/wiaX3U4CxdyEsZ/5lYCaV Ilw/tfDMkiy65tJJiW7DESgkn+33QaE= X-Google-Smtp-Source: ABdhPJxykTBXGwmq/YYhM5dLoMcVfRHRm4PsTDJT3jMl89PfESvOBCH29BIUSv144QGxxtKYuUSQ4Q== X-Received: by 2002:a05:600c:2905:: with SMTP id i5mr8712893wmd.9.1602943552836; Sat, 17 Oct 2020 07:05:52 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id g125sm2890034wme.33.2020.10.17.07.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 40/44] MAINTAINERS: Remove myself Date: Sat, 17 Oct 2020 16:02:39 +0200 Message-Id: <20201017140243.1078718-41-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic , =?utf-8?q?Herv=C3=A9?= =?utf-8?q?_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic I have been working on project other than QEMU for some time, and would like to devote myself to that project. It is impossible for me to find enough time to perform maintainer's duties with needed meticulousness and patience. I wish prosperous future to QEMU and all colleagues in QEMU community. Signed-off-by: Aleksandar Markovic Message-Id: <1602103041-32017-6-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 99ab02bbab3..b91bd754d16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -220,11 +220,10 @@ F: hw/microblaze/ F: disas/microblaze.c MIPS TCG CPUs -M: Aleksandar Markovic R: Aurelien Jarno R: Jiaxun Yang R: Aleksandar Rikalo -S: Maintained +S: Orphaned F: target/mips/ F: default-configs/*mips* F: disas/*mips* @@ -386,7 +385,6 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen -M: Aleksandar Markovic S: Odd Fixes F: target/mips/kvm.c @@ -1123,10 +1121,9 @@ F: hw/display/jazz_led.c F: hw/dma/rc4030.c Malta -M: Aleksandar Markovic M: Philippe Mathieu-Daudé R: Aurelien Jarno -S: Maintained +S: Odd Fixes F: hw/isa/piix4.c F: hw/acpi/piix4.c F: hw/mips/malta.c @@ -1136,14 +1133,12 @@ F: tests/acceptance/linux_ssh_mips_malta.py F: tests/acceptance/machine_mips_malta.py Mipssim -M: Aleksandar Markovic R: Aleksandar Rikalo -S: Odd Fixes +S: Orphaned F: hw/mips/mipssim.c F: hw/net/mipsnet.c R4000 -M: Aleksandar Markovic R: Aurelien Jarno R: Aleksandar Rikalo S: Obsolete @@ -1152,7 +1147,6 @@ F: hw/mips/r4k.c Fuloong 2E M: Huacai Chen M: Philippe Mathieu-Daudé -M: Aleksandar Markovic R: Jiaxun Yang S: Odd Fixes F: hw/mips/fuloong2e.c @@ -2823,12 +2817,11 @@ F: tcg/i386/ F: disas/i386.c MIPS TCG target -M: Aleksandar Markovic R: Aurelien Jarno R: Huacai Chen R: Jiaxun Yang R: Aleksandar Rikalo -S: Maintained +S: Orphaned F: tcg/mips/ PPC TCG target @@ -3169,7 +3162,7 @@ S: Odd Fixes F: scripts/git-submodule.sh UI translations -M: Aleksandar Markovic +S: Orphaned F: po/*.po Sphinx documentation configuration and build machinery From patchwork Sat Oct 17 14:02:40 2020 Content-Type: text/plain; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id m1sm7386347wmm.34.2020.10.17.07.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:05:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 41/44] MAINTAINERS: Put myself forward for MIPS target Date: Sat, 17 Oct 2020 16:02:40 +0200 Message-Id: <20201017140243.1078718-42-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Thomas Huth , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" To avoid the MIPS target being orphan, volunteer to keep an eye on it and put together pull requests. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Reviewed-by: Thomas Huth Message-Id: <20201013101659.3557154-2-f4bug@amsat.org> --- MAINTAINERS | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b91bd754d16..50fb9fda34d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -220,10 +220,11 @@ F: hw/microblaze/ F: disas/microblaze.c MIPS TCG CPUs +M: Philippe Mathieu-Daudé R: Aurelien Jarno R: Jiaxun Yang R: Aleksandar Rikalo -S: Orphaned +S: Odd Fixes F: target/mips/ F: default-configs/*mips* F: disas/*mips* @@ -2817,11 +2818,12 @@ F: tcg/i386/ F: disas/i386.c MIPS TCG target +M: Philippe Mathieu-Daudé R: Aurelien Jarno R: Huacai Chen R: Jiaxun Yang R: Aleksandar Rikalo -S: Orphaned +S: Odd Fixes F: tcg/mips/ PPC TCG target From patchwork Sat Oct 17 14:02:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62FCF15E6 for ; Sat, 17 Oct 2020 14:16:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1FAC920704 for ; Sat, 17 Oct 2020 14:16:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="f5advx1z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1FAC920704 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:44164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTn0f-0003jm-8m for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmqU-0005G2-Tu for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:06 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmqT-00048L-6P for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:06 -0400 Received: by mail-wr1-x429.google.com with SMTP id h5so6580791wrv.7 for ; Sat, 17 Oct 2020 07:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K4I6rKlRV5CwkXwi1bhz1e4ZJqjshXMHPloXxAGf1Gs=; b=f5advx1zgDfzeVwXM7qs/p/Ay06yMXHouCwif8kW3SK93qbRcRCb4drq5pO6ECTlYV 0a3PqW+zA0AWf/qWBU8kJPbPj3961C/F7gUPx/rov56AIOvkwXcYxjVij1fjMnPhuKDg c2pxCzg8TSV2dtcH80rIm9RI/jHJPr7LHX8lzStlwM4dArT5JQIQoGkMJR1HVJ1IU3de RMYaC4c5bJ4ILHKSeUxMuxBOtmnsey1PGaLCHoVog1bH1U5LMLc+/Kntzg1K5ooq809Q 1D/VdGA6uQ/BeXVB4xnh1RwMq7iiWcaEiuNIVBHM1nWdAlow/pwRbvsmGS0OqZNSOuUw rv/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=K4I6rKlRV5CwkXwi1bhz1e4ZJqjshXMHPloXxAGf1Gs=; b=M+XHPWcu+B/1yWI4qifsgRRUeo3QqHFtWg3yPjre6k/6th0KFVYMDiLIHH41BT0TF7 CtMd71ZqQAyihsKx2eC6CZD6umbyD9yh1GUD3Ooa8uful0WnBorDXCN7KF7ex8YDBPGN OGdwOza2/qHJOfraFlQEg3+6YpOkwN4wDo39W5iG2MPkwS9OqWwaZRPGXDa5+08hxF60 vVFaN+4PeIvgnBXW4DEhntaehIDqdGfKLHMCay4faBqHXNODtUJwAgcQl2/fx2stVhaP PDPVEQHQiwrw6UP130mohHErUERJQZ0rO+fQTfquWNG0+baTRCgTz+D4Fj5Tz9ssPiO1 4Bqg== X-Gm-Message-State: AOAM533aattwzIE+gRv6zuJxLHlsS/s71qcuXTjXaGmtIBmYsUkyvyCI Jw4uQKZa3tYd6G2gj7n3W8ZgGW6p/Vo= X-Google-Smtp-Source: ABdhPJzCxUSgdlziZfXv4uD1ng0gnQ2iPCuCmjbBBcyBT/XlH5ugoZcR1gpvUyx8zmP7Yez1X1Wypg== X-Received: by 2002:a5d:6cad:: with SMTP id a13mr11099223wra.347.1602943561904; Sat, 17 Oct 2020 07:06:01 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id b189sm7292068wmb.37.2020.10.17.07.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:06:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 42/44] MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail Date: Sat, 17 Oct 2020 16:02:41 +0200 Message-Id: <20201017140243.1078718-43-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Thomas Huth , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Paul's Wavecomp email has been bouncing for months. He told us he "no longer has access to modern MIPS CPUs or Boston hardware, and wouldn't currently have time to spend on them if he did." [1] but "perhaps that might change in the future." [2]. Be fair and downgrade the status of the Boston board to "Odd Fixes" (has a maintainer but they don't have time to do much other). Similarly to commit 2b107c2c1c (".mailmap: Update Paul Burton email address"), update his email address here too. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718739.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg728605.html Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20201013101659.3557154-4-f4bug@amsat.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 50fb9fda34d..8770cd6d05a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1162,9 +1162,9 @@ S: Maintained F: hw/intc/loongson_liointc.c Boston -M: Paul Burton +M: Paul Burton R: Aleksandar Rikalo -S: Maintained +S: Odd Fixes F: hw/core/loader-fit.c F: hw/mips/boston.c F: hw/pci-host/xilinx-pcie.c From patchwork Sat Oct 17 14:02:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1794D14B5 for ; Sat, 17 Oct 2020 14:38:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA1FD20708 for ; Sat, 17 Oct 2020 14:38:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="d5diqqeF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA1FD20708 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnLh-0005mN-T5 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:38:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmqX-0005MG-Kh for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:09 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:52835) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmqW-00048p-0B for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:09 -0400 Received: by mail-wm1-x334.google.com with SMTP id e23so6142301wme.2 for ; Sat, 17 Oct 2020 07:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gN5fG1W2a6ABvVlFISLEsEnU3++HZ+v2I6FNfu0op4U=; b=d5diqqeFh0UWzD1oEGPFGSH0Vp0hsp93siVOISRezbTjupm2MDl/aOiNULYOztM0x8 NLUx1EJkE1CIobTOmhdv1Zd6reVXZ0gqbgaKGnI2okhSyyHqsJFGHXClD5dOVfs6iaoP e/VJWs/dRaRGP7XYDqbmwLbg3Mqk/pn3CbwD5XWvMzECTkl+Ri9DGcBPgNkvgt9UOQko AFn0+kmKtqVl9DGaEOhi+Pb3kWlRZZfA/XmNEDIFFN/FZDwf2tGEHHU+RXAdpl03DylS bTwFR6Eh3gyWuxhIC47VvvARTwRd2WvEl7T877v7yUzP9l23wV7/Hh6TcwxWaF+mh7UD +8RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gN5fG1W2a6ABvVlFISLEsEnU3++HZ+v2I6FNfu0op4U=; b=Un7grveiFsQicSWQXTBtDoq9kw7HxdzsdjbWJSD2du9retRd0pMu9+grH5v2vhFUnb S1GKKGBPnRfaPb/QybSKbMbG+ryN281an563x8PFBwHVF6GfTd/RE1cNeLVr3tcz1M8w 80JD5GQnonOcJ3IhtZSUhsMM1qDbbGobg+Cv6woKo7votYz5G31/VoJIoVg5VLvZy3sm jlla85f7fVMgbpJkK1/J9infBfUjhob8mlHcN6VWLbh04w4t1NBWhEyMHNbsoqAEZJjl sL9qsAkUXUydSvjICwzb2A5hw6tDjUhpisYSdlX1bv3dlBYspUMadgOrokDPrOa7N9mv GCtA== X-Gm-Message-State: AOAM530qA68IdYLvVmIVN2yd/af+04NJo3S3uPFGhScFlGgc4s7P1C3K NZyS96nUWgPaB+Cdc0P2m+r53bBBlbI= X-Google-Smtp-Source: ABdhPJwGri4MKQExmjGpd06cO0csoTaEcETa7dJ3YVIlJrW+leo6QafUYzIIaCgC5+79Ae4JAFESiw== X-Received: by 2002:a1c:6788:: with SMTP id b130mr9265405wmc.91.1602943566495; Sat, 17 Oct 2020 07:06:06 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id c15sm3534613wmb.27.2020.10.17.07.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:06:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 43/44] MAINTAINERS: Remove duplicated Malta test entries Date: Sat, 17 Oct 2020 16:02:42 +0200 Message-Id: <20201017140243.1078718-44-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Thomas Huth , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The Malta tests are already covered in the Malta section. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20201013101659.3557154-3-f4bug@amsat.org> --- MAINTAINERS | 2 -- 1 file changed, 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8770cd6d05a..a7f0acf8663 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -237,8 +237,6 @@ F: include/hw/intc/mips_gic.h F: include/hw/mips/ F: include/hw/misc/mips_* F: include/hw/timer/mips_gictimer.h -F: tests/acceptance/linux_ssh_mips_malta.py -F: tests/acceptance/machine_mips_malta.py F: tests/tcg/mips/ K: ^Subject:.*(?i)mips From patchwork Sat Oct 17 14:02:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11842827 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 354F31580 for ; Sat, 17 Oct 2020 14:40:15 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD51E20708 for ; Sat, 17 Oct 2020 14:40:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BlVy2jYZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD51E20708 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:54752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kTnNW-0007Wj-2B for patchwork-qemu-devel@patchwork.kernel.org; Sat, 17 Oct 2020 10:40:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kTmqc-0005Xw-Fq for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:14 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kTmqa-000491-KH for qemu-devel@nongnu.org; Sat, 17 Oct 2020 10:06:14 -0400 Received: by mail-wr1-x429.google.com with SMTP id y12so6588385wrp.6 for ; Sat, 17 Oct 2020 07:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7NPFG3sCe3Q0DWcvvpgh0QRrJIh4WkqraUDSbppp/5Q=; b=BlVy2jYZOLpKi+x8pl78DPw4PuPFNK5Hr9hii+HYldLiagJTlC0DDGRy7zPWkJs6V3 ibVI2ftO1N+gt7++lwBGO/Q4pfFz67tJf8/1lom2sc9nmN+VSWw5pKqlYobRAqPoCO2K +WMHc9bC2Ysxhl9FINkqzJcMZoZUqkPgzWrAAMgdenB0cxRJhNTKR/yGUFD1hvhdmxDG tcPdZMtRE5YtTgG4SNrIlXrjLOmBCsX1oAduAOrBFBIgBG/66SrZXxEiwGuOkJtn1rlc FntM/3Xcf2wYrC3zyqe54H7rernF6exXQpT96pyHzSEeWWDdx3obTfl+lAIv1F71RkMd dXpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7NPFG3sCe3Q0DWcvvpgh0QRrJIh4WkqraUDSbppp/5Q=; b=FNYJM+nuBwtxij7IyEBgQ6vwuSwwBZOWhRQNuJ+QyRjiv+E2WrLX73AA05pUwZ59oD Uwxg9Q0FjFdHAhN8ityhjkSCL2U5g8NpU4BOJojDyH9d10Dj2b80hjaw1YH46aFaHAiR nvsmazOi0n9Wql/kVK9awl/JOxzDIT2MwINC9odehOwjYddGUbYhIP66cNbVf/sp1YEd ikdAGyhtFMf1Ofo+Z24jqxAEl4QACzGFazmASky+jC/KtFfwQkuuiYL5x5rNDqb+TNvF lrb52xKQUnT+SM8lvV8csVB3j4Mj8qrIKiP/39EkcQ7EGjJDlnlg7Oy00wA8n2Zujf45 zpOQ== X-Gm-Message-State: AOAM531hvFtUSqBMF3vbTJ7C5HdUJ54ZTdehGqvGdP0MajeqjlRhq8Kh 9SHHkdhUvLYCXQLu77SfybVKW8rIx1s= X-Google-Smtp-Source: ABdhPJwvjfQ7VDOjq7eWWyfNjaZNjJPALCxXvEfbifxYhb2RhMAky8HIvmkfSnFx3t13BMNPBposZg== X-Received: by 2002:a5d:4051:: with SMTP id w17mr10218317wrp.24.1602943571161; Sat, 17 Oct 2020 07:06:11 -0700 (PDT) Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id y5sm8845509wrw.52.2020.10.17.07.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:06:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 44/44] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) Date: Sat, 17 Oct 2020 16:02:43 +0200 Message-Id: <20201017140243.1078718-45-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Victor Kamensky , Paul Burton , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to their corresponding physical addresses." There is no particular reason to restrict the 34Kf core model to 16 TLB entries, so raise its config to 64. This is helpful for other projects, in particular the Yocto Project: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 Reported-by: Victor Kamensky Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201016133317.553068-1-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index c735b2bf667..fb5a9b38e5d 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -254,7 +254,7 @@ const mips_def_t mips_defs[] = .CP0_PRid = 0x00019500, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA),