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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v6 1/5] hw/riscv/virt: Increase the number of interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Increase the number of interrupts to match the HiFive Unleashed board. Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 91163d6cbf..7cb2742070 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -45,7 +45,7 @@ enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, - VIRTIO_NDEV = 10 + VIRTIO_NDEV = 0x35 }; enum { From patchwork Tue Oct 30 22:17:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10661715 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD28013A4 for ; Tue, 30 Oct 2018 22:22:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC5F92ABBD for ; Tue, 30 Oct 2018 22:22:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA33E2ABC2; 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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis --- default-configs/riscv32-softmmu.mak | 6 +- default-configs/riscv64-softmmu.mak | 6 +- hw/riscv/virt.c | 111 ++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 8 +- 4 files changed, 127 insertions(+), 4 deletions(-) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 7937c69e22..3e3d195f37 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -1,7 +1,11 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y +CONFIG_PCI_XILINX=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 7937c69e22..3e3d195f37 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,7 +1,11 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y +CONFIG_PCI_XILINX=y diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c..2fbe58ba4b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,6 +39,8 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" #include "elf.h" #include @@ -55,6 +57,10 @@ static const struct MemmapEntry { [VIRT_UART0] = { 0x10000000, 0x100 }, [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, [VIRT_DRAM] = { 0x80000000, 0x0 }, + [VIRT_PCIE_MMIO] = { 0x2000000000, 0x4000000 }, + [VIRT_PCIE_PIO] = { 0x2010000, 0x40000000 }, + [VIRT_PCIE_ECAM] = { 0x40000000, 0x20000000 }, + }; static uint64_t load_kernel(const char *kernel_filename) @@ -98,6 +104,37 @@ static hwaddr load_initrd(const char *filename, uint64_t mem_size, return *start + size; } +#define INTERREUPT_MAP_WIDTH 7 + +static void create_pcie_irq_map(void *fdt, char *nodename, + uint32_t plic_phandle) +{ + int pin; + uint32_t full_irq_map[GPEX_NUM_IRQS * INTERREUPT_MAP_WIDTH] = { 0 }; + uint32_t *irq_map = full_irq_map; + + for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { + int irq_nr = PCIE_IRQ + (pin % PCI_NUM_PINS); + int i; + + uint32_t map[] = { + 0, 0, 0, + pin + 1, plic_phandle, 0, irq_nr}; + + /* Convert map to big endian */ + for (i = 0; i < INTERREUPT_MAP_WIDTH; i++) { + irq_map[i] = cpu_to_be32(map[i]); + } + irq_map += INTERREUPT_MAP_WIDTH; + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", + full_irq_map, sizeof(full_irq_map)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0, 0, 0, 0x7); +} + static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { @@ -233,6 +270,31 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, g_free(nodename); } + nodename = g_strdup_printf("/pci@%lx", + (long) memmap[VIRT_PCIE_MMIO].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3); + qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "pci-host-ecam-generic"); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, + memmap[VIRT_PCIE_ECAM].base / + PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0, + 0, memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_cells(fdt, nodename, "ranges", + memmap[VIRT_PCIE_PIO].base, + 0, memmap[VIRT_PCIE_PIO].size, + 0, memmap[VIRT_PCIE_MMIO].base, + 0, memmap[VIRT_PCIE_MMIO].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", PCIE_IRQ); + create_pcie_irq_map(fdt, nodename, plic_phandle); + nodename = g_strdup_printf("/test@%lx", (long)memmap[VIRT_TEST].base); qemu_fdt_add_subnode(fdt, nodename); @@ -262,6 +324,47 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, return fdt; } + +static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, + hwaddr ecam_base, hwaddr ecam_size, + hwaddr mmio_base, hwaddr mmio_size, + hwaddr pio_base, + DeviceState *plic, bool link_up) +{ + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *mmio_reg; + qemu_irq irq; + int i; + + dev = qdev_create(NULL, TYPE_GPEX_HOST); + + qdev_init_nofail(dev); + + ecam_alias = g_new0(MemoryRegion, 1); + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, ecam_size); + memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); + + mmio_alias = g_new0(MemoryRegion, 1); + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); + } + + return dev; +} + static void riscv_virt_board_init(MachineState *machine) { const struct MemmapEntry *memmap = virt_memmap; @@ -384,6 +487,14 @@ static void riscv_virt_board_init(MachineState *machine) qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); } + gpex_pcie_init(system_memory, + memmap[VIRT_PCIE_MMIO].base, + memmap[VIRT_PCIE_MMIO].size, + memmap[VIRT_PCIE_ECAM].base, + memmap[VIRT_PCIE_ECAM].size, + memmap[VIRT_PCIE_PIO].base, + DEVICE(s->plic), true); + serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7cb2742070..dd4feddb42 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -38,14 +38,18 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, - VIRT_DRAM + VIRT_DRAM, + VIRT_PCIE_MMIO, + VIRT_PCIE_PIO, + VIRT_PCIE_ECAM }; enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, - VIRTIO_NDEV = 0x35 + PCIE_IRQ = 0x20, /* 32 to 35 */ + VIRTIO_NDEV = 0x36 }; enum { From patchwork Tue Oct 30 22:18:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10661713 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3582713A4 for ; Tue, 30 Oct 2018 22:20:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27E792A97D for ; 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Tue, 30 Oct 2018 22:18:09 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Thread-Topic: [PATCH v6 3/5] riscv: Enable VGA and PCIE_VGA Thread-Index: AQHUcJ5wzmW6NU6gKEWEHo/9PNCsUw== Date: Tue, 30 Oct 2018 22:18:08 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.19.1 x-clientproxiedby: BYAPR03CA0013.namprd03.prod.outlook.com (2603:10b6:a02:a8::26) To MWHPR04MB0401.namprd04.prod.outlook.com (2603:10b6:300:70::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alistair.Francis@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [199.255.44.171] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; MWHPR04MB0239; 6:8nu/N2RQUlYv2t/QC0z/rffADJDv5Mp06e1wzStfCVdvtDgje8+t2PEbOcplrVyg97oJtfxzIFvFGr+xQoV6psKdIwdSV5c2U7XETm7BJlkv320evOOTlXudojxC8TBjpdIfo9B/j0soqi/2LfBwEwM6yuO5ErT4ELCmyMFaIwYy/OU9m4XAsIpz8I2BagfJBh8VAUyoikfOn/ho2v/MFBs+R1hDaMESequpv2XGVvUmDaZeAqbuWJIxWJl7kv/aatKwpP8h0Fy7u96Xj4WLM0cF5uIOpcvo7pC2x+079QUiZi86DTT4IU8vhZKScwgJ1HEhMYGF/Wwhl5AooTxgJ6wP8QcgoN6/Fd5M1VrEJngLq1jVdUw+kW3YSgUb+Xytn0zz0A1nne/6881r8Szqj/oVcr2bc27Zd0O1Uj6ZAcz7w1STqruDjuWKloVJMflyAbCUTTRbvqIonIsx9WU7qA==; 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X-Received-From: 216.71.154.42 Subject: [Qemu-devel] [PATCH v6 3/5] riscv: Enable VGA and PCIE_VGA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable compile support for VGA devices. This allows the user to conenct a display by adding '-device bochs-display -display sdl' to their command line argument. Signed-off-by: Alistair Francis --- default-configs/riscv32-softmmu.mak | 3 +++ default-configs/riscv64-softmmu.mak | 3 +++ 2 files changed, 6 insertions(+) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 3e3d195f37..05fae82f1b 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -9,3 +9,6 @@ CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y CONFIG_PCI_XILINX=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 3e3d195f37..05fae82f1b 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -9,3 +9,6 @@ CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y CONFIG_PCI_XILINX=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y From patchwork Tue Oct 30 22:18:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10661711 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7170914DE for ; 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Tue, 30 Oct 2018 22:18:18 +0000 From: Alistair Francis To: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Thread-Topic: [PATCH v6 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe Thread-Index: AQHUcJ517A5XNpjliU2rfdW3b/nlFQ== Date: Tue, 30 Oct 2018 22:18:18 +0000 Message-ID: <27888cbc7494b9e496716b3b055f0d72c93e42e5.1540937826.git.alistair.francis@wdc.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.19.1 x-clientproxiedby: BYAPR03CA0014.namprd03.prod.outlook.com (2603:10b6:a02:a8::27) To MWHPR04MB0401.namprd04.prod.outlook.com (2603:10b6:300:70::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [199.255.44.171] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; MWHPR04MB0976; 6:vMKzTFLMzdO9JECxXJPuZM3j3jDGklIL31Ty9lfScQaPm0sZ1zmYA+UQgc/R2bMyf42y2sKrGxnqvLu6GPAzePnKSgecNoHZue7R91685z6dHAq8Jg1cdmbvewpDL51151JFGdGfkbptoN9nFhOCxoGbiZbU9aRI0YjJH/fX+Rq00V4R6liW2fzYTnLCeFNMNgproctwnTTKkadSeZqED+QJ5BBQz4iuhu+4IUdpEXJPVl/Ps63sC41OEU1EVYSBATD55/q1YFGVTbIcYyrM22dD+Y2qnCzZugOXrnVbgbouyH9Hsr6Ndp54YYTO7jwER87XpmF3n5jK+Y8r1UWFUIWxP42bQLLRkAS4vroJxJ/udgRsfH9oB3hMQRuMYx+Zw0CzC0V5ZHIwmEYr3iSMAN7KiX+tiVeVEfjywUSeITbefkZJdhsv+gDxpJj/qYQN13mw8x8RnOUmr5MegNYekg==; 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X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v6 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Connect the Xilinx PCIe device based on the information in the device tree stored in the ROM of the HiFish Unleashed board. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 64 +++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 4 ++- 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ef07df2442..0c51c61082 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -45,6 +45,8 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/xilinx-pcie.h" #include "elf.h" #include @@ -61,6 +63,7 @@ static const struct MemmapEntry { [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, + [SIFIVE_U_PCIE] = { 0x2000000000, 0x4000000 }, }; #define GEM_REVISION 0x10070109 @@ -218,6 +221,32 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); g_free(nodename); + nodename = g_strdup_printf("/pci@%lx", + (long) memmap[SIFIVE_U_PCIE].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3); + qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "xlnx,axi-pcie-host-1.00.a"); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0x0, 0x0, + memmap[SIFIVE_U_PCIE].size); + qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); + qemu_fdt_setprop_cells(fdt, nodename, "ranges", 0x2000000, 0x0, + 0x40000000, 0x0, 0x40000000, 0x0, 0x20000000); + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_PCIE_IRQ); + g_free(nodename); + + nodename = g_strdup_printf("/pci@%lx/interrupt-controller", + (long) memmap[SIFIVE_U_PCIE].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x00); + qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1); + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); + g_free(nodename); + nodename = g_strdup_printf("/soc/uart@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); @@ -236,6 +265,37 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); } +static inline DeviceState * +xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr, + hwaddr cfg_base, uint64_t cfg_size, + hwaddr mmio_base, uint64_t mmio_size, + qemu_irq irq, bool link_up) +{ + DeviceState *dev; + MemoryRegion *cfg, *mmio; + + dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); + + qdev_prop_set_uint32(dev, "bus_nr", bus_nr); + qdev_prop_set_uint64(dev, "cfg_base", cfg_base); + qdev_prop_set_uint64(dev, "cfg_size", cfg_size); + qdev_prop_set_uint64(dev, "mmio_base", mmio_base); + qdev_prop_set_uint64(dev, "mmio_size", mmio_size); + qdev_prop_set_bit(dev, "link_up", link_up); + + qdev_init_nofail(dev); + + cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); + + mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0); + + qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq); + + return dev; +} + static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_u_memmap; @@ -375,6 +435,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, plic_gpios[SIFIVE_U_GEM_IRQ]); + + xilinx_pcie_init(system_memory, 0, memmap[SIFIVE_U_PCIE].base, + memmap[SIFIVE_U_PCIE].size, 0x40000000, 0x20000000, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_PCIE_IRQ), true); } static void riscv_sifive_u_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e8b4d9ffa3..e7292ea83b 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -53,12 +53,14 @@ enum { SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, - SIFIVE_U_GEM + SIFIVE_U_GEM, + SIFIVE_U_PCIE }; enum { SIFIVE_U_UART0_IRQ = 3, SIFIVE_U_UART1_IRQ = 4, + SIFIVE_U_PCIE_IRQ = 0x20, SIFIVE_U_GEM_IRQ = 0x35 }; From patchwork Tue Oct 30 22:18:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 10661723 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46CAE3CF1 for ; Tue, 30 Oct 2018 22:23:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 374672AB4F for ; Tue, 30 Oct 2018 22:23:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2AC372AB7D; Tue, 30 Oct 2018 22:23:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9284F2AB4F for ; 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X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v6 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis --- default-configs/riscv32-softmmu.mak | 1 + default-configs/riscv64-softmmu.mak | 1 + hw/riscv/virt.c | 16 +++++++++++++++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 05fae82f1b..bb3dd34606 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -9,6 +9,7 @@ CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y CONFIG_PCI_XILINX=y +CONFIG_VIRTIO_PCI=y CONFIG_VGA=y CONFIG_VGA_PCI=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 05fae82f1b..bb3dd34606 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -9,6 +9,7 @@ CONFIG_CADENCE=y CONFIG_PCI_GENERIC=y CONFIG_PCI_XILINX=y +CONFIG_VIRTIO_PCI=y CONFIG_VGA=y CONFIG_VGA_PCI=y diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2fbe58ba4b..920ca4e489 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "chardev/char.h" +#include "net/net.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" @@ -373,6 +374,8 @@ static void riscv_virt_board_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + DeviceState *dev; + PCIBus *pci_bus; char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -487,13 +490,24 @@ static void riscv_virt_board_init(MachineState *machine) qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); } - gpex_pcie_init(system_memory, + dev = gpex_pcie_init(system_memory, memmap[VIRT_PCIE_MMIO].base, memmap[VIRT_PCIE_MMIO].size, memmap[VIRT_PCIE_ECAM].base, memmap[VIRT_PCIE_ECAM].size, memmap[VIRT_PCIE_PIO].base, DEVICE(s->plic), true); + pci_bus = PCI_HOST_BRIDGE(dev)->bus; + + for (i = 0; i < nb_nics; i++) { + NICInfo *nd = &nd_table[i]; + + if (!nd->model) { + nd->model = g_strdup("virtio"); + } + + pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); + } serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,