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Mon, 19 Oct 2020 09:47:37 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 1/6] Documetation: dt-bindings: drop samsung,exynos5440-pcie binding Date: Mon, 19 Oct 2020 11:47:10 +0200 Message-Id: <20201019094715.15343-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm29nOOZMWX1Pyw0xhoHT1koGnMlEJOtCfCgkyai49baO5yeZM 7Y+amq5p6h/N6zTRsWauJeaWl5LhlOEUhTTUKLCbZlReSLt6Omr/nud5n4fn5eUlMbFJEEAq 1RmMVi1TSXAfftfgmvewM7lUGlH4OYJqyVdQjS6vgJpaLxJQ5uV7BDX21ohTo6M2gppw1uHU SIMbp6pH+3jUpx8fCKrdNUtQhb0ugnLMDGFxItraYAW0o2aWoE12PW23lOB0WacF0O6pJzx6 yR50lkjyiUllVMpMRhsem+yjmK+MSK/wy3Kv9fBywSQ0ACGJ4FH0a+mrwAB8SDE0A/Te49gk yxtk0oNzZAmgjm99+FbkjtFFcIM2gCrb+rHtiLW0RMC6cBiJDIuGjQRJ+sE49H2FYj0YbMZQ 7l0XYD2+8AKy1T/ms5gPQ1Bj8QyP9YvgSbTeeYwrC0YPbM8wFgthLDI0tWKcbiHQeM8+Dp9C 4/3NgMO+aN7dSXA4EP1xNPLYXgRvAfTG205wxAjQRH71ZuIEmvGu/1sUg/tRhzOck+ORe9rE Z2UEd6KpxV2sjG3Ayq4qjJNFqLhIzLlDUY374Xbt87HxzTVpVL5atHnRCoBW8wfxchBc87/M BIAF+DN6XZqc0UWpmRthOlmaTq+Wh6Vo0uxg4288v90r3aDv59UBAEkg2SF6rTFKxQJZpi47 bQAgEpP4iRJGPFfEolRZdg6j1Ui1ehWjGwB7SL7EXxTV/PGyGMplGcx1hklntFtTHikMyAXO QMlNJxGdw/Dva/zsNtUrMnGo+FBom21N9UXhDJKbzMMFT1ukQ5NzWcu9dLcgZvfC+fi956SX UuzGVgNsCDSS3qS5hXcFylr/+RePjoRAp2Iq9GBT4svV4fSLMnP9cWuT0WqNFtaeIfoTrt3O m43yiOIm8qbL6qq0lPK0hK9TyCIPYFqd7C8PXM6AMwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4Xd1dCb3xBp1LhS2WNGVYzD9yjtXi xq82VosVX2ayW1x42sNmcf78BnaLy7vmsFmcnXeczWLG+X1MFm9+v2C3WHvkLrtF694j7BY7 75xgduD1WDNvDaPHzll32T0WbCr12LSqk82jb8sqRo/jN7YzeXzeJBfAHqVnU5RfWpKqkJFf XGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8WqSQcFEkYrjP/cwNTBe F+hi5OSQEDCR6O45wt7FyMUhJLCUUeLVjx2sEAkZiZPTGqBsYYk/17rYIIo+MUrsfn2GESTB JmAo0fUWJMHJISLgJPF+8kVmkCJmgTXMEo1t3UwgCWGBEIkpjV3sIDaLgKrE/I47QHEODl4B W4lfWywhFshLrN5wgBnE5hSwk+hauAzMFgIq6Vo5jWUCI98CRoZVjCKppcW56bnFRnrFibnF pXnpesn5uZsYgeG/7djPLTsYu94FH2IU4GBU4uF9kN8TL8SaWFZcmXuIUYKDWUmE1+ns6Tgh 3pTEyqrUovz4otKc1OJDjKZAN01klhJNzgfGZl5JvKGpobmFpaG5sbmxmYWSOG+HwMEYIYH0 xJLU7NTUgtQimD4mDk6pBsaDIXPWzL59Iypw876dNTN6VOfttTPeZaXg2VS0+P7dUw1vS71S a18eP/vUqqiQ61BFSuMm4ZVOtjKtyQqKlV+OM2T3JMamZiddf2/9Zq4U666HMtOcTEOflwq6 HCrhlD/IL7t9w9f/XNWJ7i/3K5e0ivMUPzyxs/9GV8c/Zfbg7tLPv/yOX1FiKc5INNRiLipO BADx0pM6lQIAAA== X-CMS-MailID: 20201019094738eucas1p29b377b561089cfc3eba1755d475125b9 X-Msg-Generator: CA X-RootMTR: 20201019094738eucas1p29b377b561089cfc3eba1755d475125b9 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094738eucas1p29b377b561089cfc3eba1755d475125b9 References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for exynos5440-pcie. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/pci/samsung,exynos5440-pcie.txt | 58 ------------------- 1 file changed, 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt deleted file mode 100644 index 651d957d1051..000000000000 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung Exynos 5440 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "samsung,exynos5440-pcie" -- reg: base addresses and lengths of the PCIe controller, -- reg-names : First name should be set to "elbi". - And use the "config" instead of getting the configuration address space - from "ranges". - NOTE: When using the "config" property, reg-names must be set. -- interrupts: A list of interrupt outputs for level interrupt, - pulse interrupt, special interrupt. -- phys: From PHY binding. Phandle for the generic PHY. - Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt - -For other common properties, refer to - Documentation/devicetree/bindings/pci/designware-pcie.txt - -Example: - -SoC-specific DT Entry (with using PHY framework): - - pcie_phy0: pcie-phy@270000 { - ... - reg = <0x270000 0x1000>, <0x271000 0x40>; - reg-names = "phy", "block"; - ... - }; - - pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - clocks = <&clock 28>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <4>; - }; - -Board-specific DT Entry: - - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - }; - - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - }; From patchwork Mon Oct 19 09:47:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 11843903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0778214B7 for ; Mon, 19 Oct 2020 09:48:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C96EB2225F for ; Mon, 19 Oct 2020 09:48:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="mTNDlfZ1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728839AbgJSJsP (ORCPT ); Mon, 19 Oct 2020 05:48:15 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:36239 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728626AbgJSJsP (ORCPT ); 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Mon, 19 Oct 2020 09:47:38 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 2/6] Documetation: dt-bindings: add the samsung,exynos-pcie binding Date: Mon, 19 Oct 2020 11:47:11 +0200 Message-Id: <20201019094715.15343-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTYRiGec/Zdo7SidMUfbFUWBkq5AdJHdLMwuD0w+hPEMGcxzyp5dQ2 Z+mfzKXlstSQnBJ+JSrLz2XmNCVtudLchkIM0nREZToRnOZXam5H7d9938918zy8vDgqfMH3 wpNTM1hZKpMiErjyOgdXjcd64h5LQvL6fam63CSqSm/kU5a1fD7VuFiOUeYfhQLKZGrDqLHu 5wJqpNIgoNSmPoSyrU9jVLN+AqPyevUYpRv/iEYRdFNlE6B1FRMYXa1V0FpNgYB+0qEBtMHy BqHtWp9L2FXXiAQ2JTmTlQVHxrkmmX/1I+ka7zuTyhokB7R7qIALDskwuKJ7haqAKy4kGwHs W3jL58wigNX3rQLO2AF89qWYv1tZ6+rlcYMGALv/zvL2Ku0Nj1AHJSBDoWpOtV3HcXcyCq4s UQ4GJWtRmFOkBw7GjbwMP20MO3ke6Qd/FnzlOTRBnoYtdtvONl/4su2dk3EhI6Gqpt55LCTr Mdh6rxfjoGiYO7kMOO0GZwwdO/khuKWrQriCEkCrsRnjTCGAY7nqnUY4HDeuOU9FyQDY2h3M xWdh04NFxBFDcj+0zB1wxOi2fNpZhnIxAR/mCzn6KKwwtOyt7TePopymYctmKcI9UAmAU1Nq pBj4VvxfVg2ABniyCrk0kZWHprK3g+SMVK5ITQy6libVgu2vM7xpWOgCS6PxA4DEgWgfMZVW KBHymUx5lnQAQBwVuRPnRoZjhUQCk5XNytIkMkUKKx8AB3GeyJM4XvtbLCQTmQz2Jsums7Ld KYK7eOWAwJMbXUZkiln4Psooz5fdmD/iLjWX2saX+8R675jw1/78M8nGP1bboITuHLrr17M8 XfJNXUKJhtY+exT5GNpOlcdviZmYC9leswlu/rGHr3d4mGoDo9ctYbUhdYR1PsAwY3+/GmC+ dWVY5DJ38cSMtrk3zhQSIVbWZ8t0H3xEPHkSExqIyuTMPy6QyDU2AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4Xd1dCb3xBl8nmVksacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEv48Lzg0wFq2Qr7jcvZGpg 3CjWxcjJISFgIvFrx16WLkYuDiGBpYwS2/evY4NIyEicnNbACmELS/y51sUGUfSJUeLU8T9g RWwChhJdb7vAbBEBJ4n3ky8ygxQxC6xhlmhs62YCSQgLBEtcPDQRbBKLgKrEs87bLCA2r4Ct xLrPb6A2yEus3nCAGcTmFLCT6Fq4DMwWAqrpWjmNZQIj3wJGhlWMIqmlxbnpucVGesWJucWl eel6yfm5mxiBMbDt2M8tOxi73gUfYhTgYFTi4X2Q3xMvxJpYVlyZe4hRgoNZSYTX6ezpOCHe lMTKqtSi/Pii0pzU4kOMpkBHTWSWEk3OB8ZnXkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTE ktTs1NSC1CKYPiYOTqkGxo7dFndLyqeLvedlD1rY/HTWCfOWo+r79D2ZL233mpNonh2nsEJj 1/N5ff/CZx6Mn5/HVfsmsMTy7K2K9SFn2ORqnVf9elPXGzLpx7ZJ+2Ol5odu5z4tZXplE1/c G48fgez/2LcFHFHcvKM+7vWmBdNnR25my9RzXWx1o6k4V1T9JZvVQ6mf25VYijMSDbWYi4oT Aez6wzeXAgAA X-CMS-MailID: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d X-Msg-Generator: CA X-RootMTR: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094739eucas1p18cd4c7e5a0197393d2e7c5c6fcc2777d References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jaehoon Chung Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Signed-off-by: Jaehoon Chung [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, rewrote commit message] Signed-off-by: Marek Szyprowski --- .../bindings/pci/samsung,exynos-pcie.yaml | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..48fb569c238c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Jaehoon Chung + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + enum: + - samsung,exynos5433-pcie + + reg: + items: + - description: External Local Bus interface (ELBI) registers. + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: elbi + - const: bdi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + +required: + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - phy-names + - vdd10-supply + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>; + reg-names = "elbi", "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + num-lanes = <1>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + iterrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; From patchwork Mon Oct 19 09:47:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 11843901 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B90516C0 for ; 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Mon, 19 Oct 2020 09:47:39 +0000 (GMT) X-AuditID: cbfec7f4-65dff7000000176d-46-5f8d60bb2632 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 6C.CB.06017.BB06D8F5; Mon, 19 Oct 2020 10:47:39 +0100 (BST) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201019094738eusmtip1e96bfe74092fba0cf6337e518f7c6b67~-W7zSoZiN1561015610eusmtip1g; Mon, 19 Oct 2020 09:47:38 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 3/6] Documetation: dt-bindings: add the samsung,exynos-pcie-phy binding Date: Mon, 19 Oct 2020 11:47:12 +0200 Message-Id: <20201019094715.15343-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLKsWRmVeSWpSXmKPExsWy7djPc7q7E3rjDTZ+MLRY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wWrXuPsFvs vHOC2YHXY828NYweO2fdZfdYsKnUY9OqTjaPvi2rGD2O39jO5PF5k1wAexSXTUpqTmZZapG+ XQJXRtM3oYLzghXTzvYzNzAu4eti5OSQEDCRuL72DmsXIxeHkMAKRom7i+YyQzhfGCX6L92D ynxmlNjy7x0rTMvRp/OZQGwhgeWMEg9WW8J1zO3fxwaSYBMwlOh62wVkc3CICDhI/PhqAVLD LLCIWaKh/wgjSFxYIFLiz1JdEJNFQFVi3bc0EJNXwFZi8RwmiE3yEqs3HGAGsTkF7CS6Fi4D u01CYBm7xKr+m4wQRS4SW1+sYIGwhSVeHd/CDmHLSPzfCXImSEMzo8TDc2vZIZweRonLTTOg uq0l7pz7BXYns4CmxPpd+hBhR4mWF+vBzpQQ4JO48VYQJMwMZE7aNp0ZIswr0dEmBFGtJjHr +Dq4tQcvXIIq8ZDouykHCZyJjBJ9bzqYJjDKz0LYtYCRcRWjeGppcW56arFRXmq5XnFibnFp Xrpecn7uJkZgojn97/iXHYy7/iQdYhTgYFTi4X2Q3xMvxJpYVlyZe4hRgoNZSYTX6ezpOCHe lMTKqtSi/Pii0pzU4kOM0hwsSuK8xotexgoJpCeWpGanphakFsFkmTg4pRoYeUt6Z/BqPLrg eNVn5TvtFWezeeuqvGsDVloZR+pX2Bz58Pqu5OcZE/Zk+01/qM++82XY4qQXPx/NeHb+W+WV DSkmXiJzDe39H9tvZHeLlRWaH/xnuUBzeM+MzWaPVt445F9vH9/B89ZeVav4LKv5kUzJfK1S 49Sqgpv5c+M6NlYsP/vNMVlPiaU4I9FQi7moOBEAslznTTADAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkkeLIzCtJLcpLzFFi42I5/e/4Xd3dCb3xBjv/SFssacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEvo+mbUMF5wYppZ/uZGxiX 8HUxcnJICJhIHH06n6mLkYtDSGApo8TGP5tZIRIyEienNUDZwhJ/rnWxQRR9YpT4e2E/WIJN wFCi6y1IgpNDRMBJ4v3ki8wgRcwCa5glGtu6mUASwgLhEjO+XgOyOThYBFQl1n1LAzF5BWwl Fs9hgpgvL7F6wwFmEJtTwE6ia+EyMFsIqKRr5TSWCYx8CxgZVjGKpJYW56bnFhvpFSfmFpfm pesl5+duYgQG/7ZjP7fsYOx6F3yIUYCDUYmH90F+T7wQa2JZcWXuIUYJDmYlEV6ns6fjhHhT EiurUovy44tKc1KLDzGaAp00kVlKNDkfGJl5JfGGpobmFpaG5sbmxmYWSuK8HQIHY4QE0hNL UrNTUwtSi2D6mDg4pRoYBbz0Hi16ZvK/68EzxbPuh/4U/J/decL6kUmzNNN2tyeSOct3nnh5 tnfWxg/yV+xSdpyyPdLg9GdP9apmuVOsDl8rtk8p25QiHLgq8Wdw6PWPF263zVgmK+nfFfxH vtYh8voTz8zbW8VTXno2HNu9t39hi17ptvc8iw5tjnzWvHi5Xqdrc9w/HSWW4oxEQy3mouJE ALv+BHuUAgAA X-CMS-MailID: 20201019094739eucas1p17424b1224bf2a1a5b16c33deb4209166 X-Msg-Generator: CA X-RootMTR: 20201019094739eucas1p17424b1224bf2a1a5b16c33deb4209166 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094739eucas1p17424b1224bf2a1a5b16c33deb4209166 References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jaehoon Chung Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433 variant). Signed-off-by: Jaehoon Chung [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, rewrote commit message] Signed-off-by: Marek Szyprowski --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 000000000000..ce92d1e687e7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Jaehoon Chung + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... \ No newline at end of file From patchwork Mon Oct 19 09:47:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 11843895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C6AD14B7 for ; Mon, 19 Oct 2020 09:48:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FE4622243 for ; Mon, 19 Oct 2020 09:48:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="B6LE1xSf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728577AbgJSJsA (ORCPT ); Mon, 19 Oct 2020 05:48:00 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:36169 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728273AbgJSJr7 (ORCPT ); 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Mon, 19 Oct 2020 09:47:39 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Date: Mon, 19 Oct 2020 11:47:13 +0200 Message-Id: <20201019094715.15343-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTYRTHeXa33etqcZ2ijxYaC4ss38oPN1NTy7oQhNG3wHTT25S2KZtb KgSiOXRNy8RSM9+ysulKhmhqDb0OJ5rTnB8WKaQgWWRaLsz33K7at//5n/85v4fDgyGCBo4v li7PohRykVTI5bE7BlasQe+SS5JCl1t8iKb8NKLObOUQ9lUNh2h2VKHE2KyOS4yOtqGErbuG S4zUWrhE5aiJRfxYm0MJg3kKJQrfm1Gia3IQieGTrbWtgOyqnkLJeqOKNOqLuWRpux6QFnsn i1wy+iWg13mRqZQ0XU0pQqKTeWm6p/fQzGJ19qONITQPGG5qgRsG8XD4u4dGnVqANwP4qkiq Bbxt7QBwoeAXmymWAPy5+AzZnfhUtsJhGi8B1NSssvZGaqqagDPFxcOgdl7L1QIM88Rj4N8/ hDOD4I0IzLtvdmU8cDFcXDO52Gw8AFa0t7Kdmo9Hwd7ZKsDQ/GFLW6+L7IZHQ23DC8S5COJ6 FBq3SjlOAMQvQNO0L5P3gN8t7SijD8GtrjoWky8AcNpqQJlCB6Atv3KHcBZOWlddL0Xw4/BN dwhjx0K7QQ+Y/Qegfd7daSPb8mHHY4Sx+bBII2DSR2G15fUetm9sfOdYJOz4QCPMfcoALK6g wQPgX/0fVg+AHnhTKqVMQilPyanbwUqRTKmSS4JTMmRGsP1xhjctjrege11MAxwDwv38Lxm6 JAFHpFbmyGgAMUToyY8bGb4h4KeKcnIpRUaSQiWllDQ4iLGF3vzTjd8SBbhElEXdoqhMSrHb ZWFuvnmgfDwhwDTHKZ8Y5OcW1YZfhKl9+UMRuXccUfVxHxfs8aXZ4kJAShKrfZazkjWdiz3X CuZP0p/7N/BIL1vdk+cX1ef8Am2b4omZM41XOjWyE/37pCX9A1FBX8eCLt+lz6ccK/MWXALr 8Rgai+kWDh9xn7Z5hVeSILTi6kxETouQrUwThQUiCqXoH9PeHRU0AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4Xd09Cb3xBv+WsVgsacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEvo2duN3tBZ1nFtL+n2BsY 16Z1MXJySAiYSNyc+JO1i5GLQ0hgKaPEzRf72CESMhInpzWwQtjCEn+udbFBFH1ilNjR9Acs wSZgKNH1FiTBySEi4CTxfvJFZpAiZoE1zBKNbd1MIAlhgQSJp1vOs4DYLAKqElO3rAGzeQVs JQ48nckIsUFeYvWGA8wgNqeAnUTXwmVgthBQTdfKaSwTGPkWMDKsYhRJLS3OTc8tNtIrTswt Ls1L10vOz93ECIyBbcd+btnB2PUu+BCjAAejEg/vg/yeeCHWxLLiytxDjBIczEoivE5nT8cJ 8aYkVlalFuXHF5XmpBYfYjQFOmois5Rocj4wPvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7GCAmk J5akZqemFqQWwfQxcXBKNTCeebugfLvDhCP1zecKdrvHrGQ2veC6Yinbg4NRgZcnzP65Mftl g7z+/tDzxyMyYhyvMN1++DVrrxVvcKTLJStezkgGIbvAiR8PCn1QE39TuWLpL7a3UesPzDER OvFvOntDfuPVD4vb1WbtP7FpzrJnBrWKuvqJTYe4fTRMZ8eJZQV/2tFU/IlHiaU4I9FQi7mo OBEABMGNgJcCAAA= X-CMS-MailID: 20201019094740eucas1p10ea264deb2cd185858d0dfdd9f6ed6fe X-Msg-Generator: CA X-RootMTR: 20201019094740eucas1p10ea264deb2cd185858d0dfdd9f6ed6fe X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094740eucas1p10ea264deb2cd185858d0dfdd9f6ed6fe References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jaehoon Chung Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY variant found in the Exynos5433 SoCs. Signed-off-by: Jaehoon Chung [mszyprow: reworked the driver to support only Exynos5433 variant, rebased onto current kernel code, rewrote commit message] Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++---------------- 1 file changed, 112 insertions(+), 192 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c index 7e28b1aea0d1..d91de323dd0e 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -4,70 +4,41 @@ * * Phy provider for PCIe controller on Exynos SoC series * - * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd. * Jaehoon Chung */ -#include #include -#include -#include #include -#include -#include #include #include #include #include -/* PCIe Purple registers */ -#define PCIE_PHY_GLOBAL_RESET 0x000 -#define PCIE_PHY_COMMON_RESET 0x004 -#define PCIE_PHY_CMN_REG 0x008 -#define PCIE_PHY_MAC_RESET 0x00c -#define PCIE_PHY_PLL_LOCKED 0x010 -#define PCIE_PHY_TRSVREG_RESET 0x020 -#define PCIE_PHY_TRSV_RESET 0x024 - -/* PCIe PHY registers */ -#define PCIE_PHY_IMPEDANCE 0x004 -#define PCIE_PHY_PLL_DIV_0 0x008 -#define PCIE_PHY_PLL_BIAS 0x00c -#define PCIE_PHY_DCC_FEEDBACK 0x014 -#define PCIE_PHY_PLL_DIV_1 0x05c -#define PCIE_PHY_COMMON_POWER 0x064 -#define PCIE_PHY_COMMON_PD_CMN BIT(3) -#define PCIE_PHY_TRSV0_EMP_LVL 0x084 -#define PCIE_PHY_TRSV0_DRV_LVL 0x088 -#define PCIE_PHY_TRSV0_RXCDR 0x0ac -#define PCIE_PHY_TRSV0_POWER 0x0c4 -#define PCIE_PHY_TRSV0_PD_TSV BIT(7) -#define PCIE_PHY_TRSV0_LVCC 0x0dc -#define PCIE_PHY_TRSV1_EMP_LVL 0x144 -#define PCIE_PHY_TRSV1_RXCDR 0x16c -#define PCIE_PHY_TRSV1_POWER 0x184 -#define PCIE_PHY_TRSV1_PD_TSV BIT(7) -#define PCIE_PHY_TRSV1_LVCC 0x19c -#define PCIE_PHY_TRSV2_EMP_LVL 0x204 -#define PCIE_PHY_TRSV2_RXCDR 0x22c -#define PCIE_PHY_TRSV2_POWER 0x244 -#define PCIE_PHY_TRSV2_PD_TSV BIT(7) -#define PCIE_PHY_TRSV2_LVCC 0x25c -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 -#define PCIE_PHY_TRSV3_RXCDR 0x2ec -#define PCIE_PHY_TRSV3_POWER 0x304 -#define PCIE_PHY_TRSV3_PD_TSV BIT(7) -#define PCIE_PHY_TRSV3_LVCC 0x31c - -struct exynos_pcie_phy_data { - const struct phy_ops *ops; -}; +#define PCIE_PHY_OFFSET(x) ((x) * 0x4) + +/* Sysreg FSYS register offsets and bits for Exynos5433 */ +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208 +#define PCIE_MAC_RESET_MASK 0xFF +#define PCIE_MAC_RESET BIT(4) +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010 +#define PCIE_REFCLK_GATING_EN BIT(0) +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020 +#define PCIE_PHY_RESET BIT(0) +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040 +#define PCIE_GLOBAL_RESET BIT(0) +#define PCIE_REFCLK BIT(1) +#define PCIE_REFCLK_MASK 0x16 +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5) + +/* PMU PCIE PHY isolation control */ +#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730 /* For Exynos pcie phy */ struct exynos_pcie_phy { - const struct exynos_pcie_phy_data *drv_data; - void __iomem *phy_base; - void __iomem *blk_base; /* For exynos5440 */ + void __iomem *base; + struct regmap *pmureg; + struct regmap *fsysreg; }; static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) @@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) writel(val, base + offset); } -static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset) -{ - return readl(base + offset); -} - -/* For Exynos5440 specific functions */ -static int exynos5440_pcie_phy_init(struct phy *phy) +/* Exynos5433 specific functions */ +static int exynos5433_pcie_phy_init(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - /* DCC feedback control off */ - exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); - - /* set TX/RX impedance */ - exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); - - /* set 50Mhz PHY clock */ - exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); - exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); - - /* set TX Differential output for lane 0 */ - exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); - - /* set TX Pre-emphasis Level Control for lane 0 to minimum */ - exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); - - /* set RX clock and data recovery bandwidth */ - exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR); - - /* change TX Pre-emphasis Level Control for lanes */ - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL); - - /* set LVCC */ - exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC); - - /* pulse for common reset */ - exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET); - udelay(500); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET); - + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, + PCIE_PHY_RESET, 1); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, + PCIE_MAC_RESET, 0); + + /* PHY refclk 24MHz */ + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_REFCLK_MASK, PCIE_REFCLK); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_GLOBAL_RESET, 0); + + + exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3)); + + /* band gap reference on */ + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20)); + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b)); + + /* jitter tunning */ + exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4)); + exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7)); + exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21)); + exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14)); + exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15)); + exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36)); + + /* D0 uninit.. */ + exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D)); + + /* 24MHz */ + exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9)); + exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA)); + exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC)); + exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF)); + exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16)); + exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A)); + exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23)); + exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24)); + + exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26)); + exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7)); + exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43)); + exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44)); + exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48)); + exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54)); + exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31)); + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32)); + + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, + PCIE_PHY_RESET, 0); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, + PCIE_MAC_RESET_MASK, PCIE_MAC_RESET); return 0; } -static int exynos5440_pcie_phy_power_on(struct phy *phy) +static int exynos5433_pcie_phy_power_on(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - u32 val; - - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); - val &= ~PCIE_PHY_COMMON_PD_CMN; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); - val &= ~PCIE_PHY_TRSV0_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); - val &= ~PCIE_PHY_TRSV1_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); - val &= ~PCIE_PHY_TRSV2_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); - val &= ~PCIE_PHY_TRSV3_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); + regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, + BIT(0), 1); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_APP_REQ_EXIT_L1_MODE, 0); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, + PCIE_REFCLK_GATING_EN, 0); return 0; } -static int exynos5440_pcie_phy_power_off(struct phy *phy) +static int exynos5433_pcie_phy_power_off(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - u32 val; - - if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val, - (val != 0), 1, 500)) { - dev_err(&phy->dev, "PLL Locked: 0x%x\n", val); - return -ETIMEDOUT; - } - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); - val |= PCIE_PHY_COMMON_PD_CMN; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); - val |= PCIE_PHY_TRSV0_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); - val |= PCIE_PHY_TRSV1_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); - val |= PCIE_PHY_TRSV2_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); - val |= PCIE_PHY_TRSV3_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, + PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN); + regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, + BIT(0), 0); return 0; } -static int exynos5440_pcie_phy_reset(struct phy *phy) -{ - struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET); - exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET); - - return 0; -} - -static const struct phy_ops exynos5440_phy_ops = { - .init = exynos5440_pcie_phy_init, - .power_on = exynos5440_pcie_phy_power_on, - .power_off = exynos5440_pcie_phy_power_off, - .reset = exynos5440_pcie_phy_reset, +static const struct phy_ops exynos5433_phy_ops = { + .init = exynos5433_pcie_phy_init, + .power_on = exynos5433_pcie_phy_power_on, + .power_off = exynos5433_pcie_phy_power_off, .owner = THIS_MODULE, }; -static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = { - .ops = &exynos5440_phy_ops, -}; - static const struct of_device_id exynos_pcie_phy_match[] = { { - .compatible = "samsung,exynos5440-pcie-phy", - .data = &exynos5440_pcie_phy_data, + .compatible = "samsung,exynos5433-pcie-phy", }, {}, }; @@ -232,30 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev) struct exynos_pcie_phy *exynos_phy; struct phy *generic_phy; struct phy_provider *phy_provider; - struct resource *res; - const struct exynos_pcie_phy_data *drv_data; - - drv_data = of_device_get_match_data(dev); - if (!drv_data) - return -ENODEV; exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL); if (!exynos_phy) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - exynos_phy->phy_base = devm_ioremap_resource(dev, res); - if (IS_ERR(exynos_phy->phy_base)) - return PTR_ERR(exynos_phy->phy_base); + exynos_phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(exynos_phy->base)) + return PTR_ERR(exynos_phy->base); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - exynos_phy->blk_base = devm_ioremap_resource(dev, res); - if (IS_ERR(exynos_phy->blk_base)) - return PTR_ERR(exynos_phy->blk_base); + exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,pmu-syscon"); + if (IS_ERR(exynos_phy->pmureg)) { + dev_err(&pdev->dev, "PMU regmap lookup failed.\n"); + return PTR_ERR(exynos_phy->pmureg); + } - exynos_phy->drv_data = drv_data; + exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,fsys-sysreg"); + if (IS_ERR(exynos_phy->fsysreg)) { + dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n"); + return PTR_ERR(exynos_phy->fsysreg); + } - generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops); + generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops); if (IS_ERR(generic_phy)) { dev_err(dev, "failed to create PHY\n"); return PTR_ERR(generic_phy); @@ -275,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = { .suppress_bind_attrs = true, } }; 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Mon, 19 Oct 2020 09:47:40 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Date: Mon, 19 Oct 2020 11:47:14 +0200 Message-Id: <20201019094715.15343-6-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsWy7djP87p7EnrjDfZPtbFY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wWrXuPsFvs vHOC2YHXY828NYweO2fdZfdYsKnUY9OqTjaPvi2rGD2O39jO5PF5k1wAexSXTUpqTmZZapG+ XQJXxt0fP1gL7s9jrOiac4GlgbGrlbGLkZNDQsBEYtHMa8xdjFwcQgIrGCU+z++Fcr4wSjzs uA3lfGaUaJ6wkgWmZeWlbUwQieWMEn0nHjLBtVzo3sIEUsUmYCjR9baLrYuRg0NEwEHix1cL kBpmgUXMEg39R8CWCwvESCx8fIcJpIZFQFVicVcwSJhXwFbi7tpOZohl8hKrNxwAszkF7CS6 Fi4Du0hCYBW7RMfXy1BPuEjsurmbCcIWlnh1fAs7hC0j8X/nfCaIhmagf86tZYdwehglLjfN gOq2lrhz7hfYpcwCmhLrd+lDhB0lnvefYgEJSwjwSdx4KwgSZgYyJ22bzgwR5pXoaBOCqFaT mHV8HdzagxcuQd3vIfHz3mN2SPhMZJS49HU28wRG+VkIyxYwMq5iFE8tLc5NTy02zEst1ytO zC0uzUvXS87P3cQITDun/x3/tIPx66WkQ4wCHIxKPLwP8nvihVgTy4orcw8xSnAwK4nwOp09 HSfEm5JYWZValB9fVJqTWnyIUZqDRUmc13jRy1ghgfTEktTs1NSC1CKYLBMHp1QDo8LrPEur yx8W9jiUPFZr/PNwZoRT8TsLBeGca1eMIqf4v98RuLL4+F3VnrodKuXm3Ws3rne/9lzfvCnX 62RVdcjmP5ndD+86VlifzzVf9GXypF9nyra932FS0xPTeUGscN1znuKzCq0M7loFyQt+XTIt OxaYXKl1Q33vnI1VBz9rcDtofBZ7pcRSnJFoqMVcVJwIAIHoc283AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42I5/e/4Xd09Cb3xBpt3aFosacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEv4+6PH6wF9+cxVnTNucDS wNjVytjFyMkhIWAisfLSNqYuRi4OIYGljBLL5jQxQyRkJE5Oa2CFsIUl/lzrYoMo+sQocWRj OxNIgk3AUKLrLUiCk0NEwEni/eSLzCBFzAJrmCUa27rBioQFoiT+/VwFtI6Dg0VAVWJxVzBI mFfAVuLu2k6oZfISqzccALM5BewkuhYuA7OFgGq6Vk5jmcDIt4CRYRWjSGppcW56brGRXnFi bnFpXrpecn7uJkZgFGw79nPLDsaud8GHGAU4GJV4eB/k98QLsSaWFVfmHmKU4GBWEuF1Ons6 Tog3JbGyKrUoP76oNCe1+BCjKdBNE5mlRJPzgRGaVxJvaGpobmFpaG5sbmxmoSTO2yFwMEZI ID2xJDU7NbUgtQimj4mDU6qBsSTKIb+wPyJyi8UPvoeXZyklh752so7SSJHju/DE9+RZ5k+R eXfi9kkv+PEybWvZIYnJ09ZVz/eyq7d4l360WGdaYkQI0xm7mX83SkTsvia1ud3k/i/j/8bW EhG/c9+VciRo9N08IOIQc/OM2q+itdLJL59FlmQ+ETs53VPqksmWFcs3ftjwQomlOCPRUIu5 qDgRAJ3c8XWYAgAA X-CMS-MailID: 20201019094740eucas1p2cd873b29bc19708f9a712d955cba62fe X-Msg-Generator: CA X-RootMTR: 20201019094740eucas1p2cd873b29bc19708f9a712d955cba62fe X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094740eucas1p2cd873b29bc19708f9a712d955cba62fe References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jaehoon Chung Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe variant found in the Exynos5433 SoCs. The main difference in Exynos5433 variant is lack of the MSI support (the MSI interrupt is not even routed to the CPU). Signed-off-by: Jaehoon Chung [mszyprow: reworked the driver to support only Exynos5433 variant, simplified code, rebased onto current kernel code, added regulator support, converted to the regular platform driver, removed MSI related code, rewrote commit message] Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/pci/controller/dwc/Kconfig | 3 +- drivers/pci/controller/dwc/pci-exynos.c | 358 ++++++++++-------------- drivers/pci/quirks.c | 1 + 3 files changed, 145 insertions(+), 217 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index bc049865f8e0..ade07abd23c9 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -84,8 +84,7 @@ config PCIE_DW_PLAT_EP config PCI_EXYNOS bool "Samsung Exynos PCIe controller" - depends on SOC_EXYNOS5440 || COMPILE_TEST - depends on PCI_MSI_IRQ_DOMAIN + depends on ARCH_EXYNOS || COMPILE_TEST select PCIE_DW_HOST config PCI_IMX6 diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 242683cde04a..58056fbdc2fa 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -2,26 +2,23 @@ /* * PCIe host controller driver for Samsung Exynos SoCs * - * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd. * https://www.samsung.com * * Author: Jingoo Han + * Jaehoon Chung */ #include #include -#include #include #include #include #include -#include #include #include #include -#include -#include -#include +#include #include "pcie-designware.h" @@ -37,102 +34,47 @@ #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 -#define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_PWR_RESET 0x018 +#define PCIE_SW_WAKE 0x018 +#define PCIE_BUS_EN BIT(1) #define PCIE_CORE_RESET 0x01c #define PCIE_CORE_RESET_ENABLE BIT(0) #define PCIE_STICKY_RESET 0x020 #define PCIE_NONSTICKY_RESET 0x024 #define PCIE_APP_INIT_RESET 0x028 #define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x064 +#define PCIE_ELBI_RDLH_LINKUP 0x074 +#define PCIE_ELBI_XMLH_LINKUP BIT(4) #define PCIE_ELBI_LTSSM_ENABLE 0x1 #define PCIE_ELBI_SLV_AWMISC 0x11c #define PCIE_ELBI_SLV_ARMISC 0x120 #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) -struct exynos_pcie_mem_res { - void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */ -}; - -struct exynos_pcie_clk_res { - struct clk *clk; - struct clk *bus_clk; -}; +/* DBI register */ +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN BIT(0) struct exynos_pcie { - struct dw_pcie *pci; - struct exynos_pcie_mem_res *mem_res; - struct exynos_pcie_clk_res *clk_res; - const struct exynos_pcie_ops *ops; - int reset_gpio; - + struct dw_pcie pci; + void __iomem *elbi_base; + struct clk *clk; + struct clk *bus_clk; struct phy *phy; + struct regulator_bulk_data supplies[2]; }; -struct exynos_pcie_ops { - int (*get_mem_resources)(struct platform_device *pdev, - struct exynos_pcie *ep); - int (*get_clk_resources)(struct exynos_pcie *ep); - int (*init_clk_resources)(struct exynos_pcie *ep); - void (*deinit_clk_resources)(struct exynos_pcie *ep); -}; - -static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev, - struct exynos_pcie *ep) -{ - struct dw_pcie *pci = ep->pci; - struct device *dev = pci->dev; - - ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); - if (!ep->mem_res) - return -ENOMEM; - - ep->mem_res->elbi_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ep->mem_res->elbi_base)) - return PTR_ERR(ep->mem_res->elbi_base); - - return 0; -} - -static int exynos5440_pcie_get_clk_resources(struct exynos_pcie *ep) -{ - struct dw_pcie *pci = ep->pci; - struct device *dev = pci->dev; - - ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL); - if (!ep->clk_res) - return -ENOMEM; - - ep->clk_res->clk = devm_clk_get(dev, "pcie"); - if (IS_ERR(ep->clk_res->clk)) { - dev_err(dev, "Failed to get pcie rc clock\n"); - return PTR_ERR(ep->clk_res->clk); - } - - ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(ep->clk_res->bus_clk)) { - dev_err(dev, "Failed to get pcie bus clock\n"); - return PTR_ERR(ep->clk_res->bus_clk); - } - - return 0; -} - -static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep) +static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) { - struct dw_pcie *pci = ep->pci; - struct device *dev = pci->dev; + struct device *dev = ep->pci.dev; int ret; - ret = clk_prepare_enable(ep->clk_res->clk); + ret = clk_prepare_enable(ep->clk); if (ret) { dev_err(dev, "cannot enable pcie rc clock"); return ret; } - ret = clk_prepare_enable(ep->clk_res->bus_clk); + ret = clk_prepare_enable(ep->bus_clk); if (ret) { dev_err(dev, "cannot enable pcie bus clock"); goto err_bus_clk; @@ -141,24 +83,17 @@ static int exynos5440_pcie_init_clk_resources(struct exynos_pcie *ep) return 0; err_bus_clk: - clk_disable_unprepare(ep->clk_res->clk); + clk_disable_unprepare(ep->clk); return ret; } -static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie *ep) +static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) { - clk_disable_unprepare(ep->clk_res->bus_clk); - clk_disable_unprepare(ep->clk_res->clk); + clk_disable_unprepare(ep->bus_clk); + clk_disable_unprepare(ep->clk); } -static const struct exynos_pcie_ops exynos5440_pcie_ops = { - .get_mem_resources = exynos5440_pcie_get_mem_resources, - .get_clk_resources = exynos5440_pcie_get_clk_resources, - .init_clk_resources = exynos5440_pcie_init_clk_resources, - .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources, -}; - static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) { writel(val, base + reg); @@ -173,67 +108,57 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_AWMISC); + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); if (on) val |= PCIE_ELBI_SLV_DBI_ENABLE; else val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); } static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_SLV_ARMISC); + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); if (on) val |= PCIE_ELBI_SLV_DBI_ENABLE; else val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); } static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); val &= ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_PWR_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); } static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_CORE_RESET); + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); val |= PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET); -} - -static void exynos_pcie_assert_reset(struct exynos_pcie *ep) -{ - struct dw_pcie *pci = ep->pci; - struct device *dev = pci->dev; - - if (ep->reset_gpio >= 0) - devm_gpio_request_one(dev, ep->reset_gpio, - GPIOF_OUT_INIT_HIGH, "RESET"); + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); } static int exynos_pcie_establish_link(struct exynos_pcie *ep) { - struct dw_pcie *pci = ep->pci; + struct dw_pcie *pci = &ep->pci; struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; + u32 val; if (dw_pcie_link_up(pci)) { dev_err(dev, "Link already up\n"); @@ -243,19 +168,25 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep) exynos_pcie_assert_core_reset(ep); phy_reset(ep->phy); - - exynos_pcie_writel(ep->mem_res->elbi_base, 1, - PCIE_PWR_RESET); - phy_power_on(ep->phy); phy_init(ep->phy); exynos_pcie_deassert_core_reset(ep); + + val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); + val &= ~PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + + /* + * Enable DBI_RO_WR_EN bit. + * - When set to 1, some RO and HWinit bits are wriatble from + * the local application through the DBI. + */ + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN); dw_pcie_setup_rc(pp); - exynos_pcie_assert_reset(ep); /* assert LTSSM enable */ - exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE, + exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE); /* check if the link is up or not */ @@ -270,18 +201,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_PULSE); - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE); -} - -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) -{ - u32 val; - - /* enable INTX interrupt */ - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE); + val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -292,26 +213,14 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -static void exynos_pcie_msi_init(struct exynos_pcie *ep) -{ - struct dw_pcie *pci = ep->pci; - struct pcie_port *pp = &pci->pp; - u32 val; - - dw_pcie_msi_init(pp); - - /* enable MSI interrupt */ - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL); - val |= IRQ_MSI_ENABLE; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL); -} - -static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep) +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - exynos_pcie_enable_irq_pulse(ep); + u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; - if (IS_ENABLED(CONFIG_PCI_MSI)) - exynos_pcie_msi_init(ep); + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -372,11 +281,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci) struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val; - val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP); - if (val == PCIE_ELBI_LTSSM_ENABLE) - return 1; - - return 0; + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + return (val & PCIE_ELBI_XMLH_LINKUP); } static int exynos_pcie_host_init(struct pcie_port *pp) @@ -386,10 +292,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &exynos_pci_ops; - exynos_pcie_establish_link(ep); - exynos_pcie_enable_interrupts(ep); - - return 0; + exynos_pcie_enable_irq_pulse(ep); + return exynos_pcie_establish_link(ep); } static const struct dw_pcie_host_ops exynos_pcie_host_ops = { @@ -399,28 +303,22 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = { static int __init exynos_add_pcie_port(struct exynos_pcie *ep, struct platform_device *pdev) { - struct dw_pcie *pci = ep->pci; + struct dw_pcie *pci = &ep->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; int ret; - pp->irq = platform_get_irq(pdev, 1); + pp->irq = platform_get_irq(pdev, 0); if (pp->irq < 0) return pp->irq; ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, - IRQF_SHARED, "exynos-pcie", ep); + IRQF_SHARED, "exynos-pcie", ep); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; } - if (IS_ENABLED(CONFIG_PCI_MSI)) { - pp->msi_irq = platform_get_irq(pdev, 0); - if (pp->msi_irq < 0) - return pp->msi_irq; - } - pp->ops = &exynos_pcie_host_ops; ret = dw_pcie_host_init(pp); @@ -438,10 +336,9 @@ static const struct dw_pcie_ops dw_pcie_ops = { .link_up = exynos_pcie_link_up, }; -static int __init exynos_pcie_probe(struct platform_device *pdev) +static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct dw_pcie *pci; struct exynos_pcie *ep; struct device_node *np = dev->of_node; int ret; @@ -450,42 +347,49 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) if (!ep) return -ENOMEM; - pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); - if (!pci) - return -ENOMEM; - - pci->dev = dev; - pci->ops = &dw_pcie_ops; + ep->pci.dev = dev; + ep->pci.ops = &dw_pcie_ops; - ep->pci = pci; - ep->ops = (const struct exynos_pcie_ops *) - of_device_get_match_data(dev); + ep->phy = devm_of_phy_get(dev, np, NULL); + if (IS_ERR(ep->phy)) + return PTR_ERR(ep->phy); - ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + /* External Local Bus interface (ELBI) registers */ + ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(ep->elbi_base)) + return PTR_ERR(ep->elbi_base); - ep->phy = devm_of_phy_get(dev, np, NULL); - if (IS_ERR(ep->phy)) { - if (PTR_ERR(ep->phy) != -ENODEV) - return PTR_ERR(ep->phy); + /* Data Bus Interface (DBI) registers */ + ep->pci.dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); + if (IS_ERR(ep->pci.dbi_base)) + return PTR_ERR(ep->pci.dbi_base); - ep->phy = NULL; + ep->clk = devm_clk_get(dev, "pcie"); + if (IS_ERR(ep->clk)) { + dev_err(dev, "Failed to get pcie rc clock\n"); + return PTR_ERR(ep->clk); } - if (ep->ops && ep->ops->get_mem_resources) { - ret = ep->ops->get_mem_resources(pdev, ep); - if (ret) - return ret; + ep->bus_clk = devm_clk_get(dev, "pcie_bus"); + if (IS_ERR(ep->bus_clk)) { + dev_err(dev, "Failed to get pcie bus clock\n"); + return PTR_ERR(ep->bus_clk); } - if (ep->ops && ep->ops->get_clk_resources && - ep->ops->init_clk_resources) { - ret = ep->ops->get_clk_resources(ep); - if (ret) - return ret; - ret = ep->ops->init_clk_resources(ep); - if (ret) - return ret; - } + ep->supplies[0].supply = "vdd18"; + ep->supplies[1].supply = "vdd10"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), + ep->supplies); + if (ret) + return ret; + + ret = exynos_pcie_init_clk_resources(ep); + if (ret) + return ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + if (ret) + return ret; platform_set_drvdata(pdev, ep); @@ -497,9 +401,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) fail_probe: phy_exit(ep->phy); + exynos_pcie_deinit_clk_resources(ep); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); - if (ep->ops && ep->ops->deinit_clk_resources) - ep->ops->deinit_clk_resources(ep); return ret; } @@ -507,32 +411,56 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev) { struct exynos_pcie *ep = platform_get_drvdata(pdev); - if (ep->ops && ep->ops->deinit_clk_resources) - ep->ops->deinit_clk_resources(ep); + phy_power_off(ep->phy); + phy_exit(ep->phy); + exynos_pcie_deinit_clk_resources(ep); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); return 0; } +static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev) +{ + struct exynos_pcie *ep = dev_get_drvdata(dev); + + phy_power_off(ep->phy); + phy_exit(ep->phy); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + + return 0; +} + +static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev) +{ + struct exynos_pcie *ep = dev_get_drvdata(dev); + struct dw_pcie *pci = &ep->pci; + struct pcie_port *pp = &pci->pp; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + if (ret) + return ret; + /* exynos_pcie_host_init controls ep->phy */ + return exynos_pcie_host_init(pp); +} + +static const struct dev_pm_ops exynos_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq, + exynos_pcie_resume_noirq) +}; + static const struct of_device_id exynos_pcie_of_match[] = { - { - .compatible = "samsung,exynos5440-pcie", - .data = &exynos5440_pcie_ops - }, - {}, + { .compatible = "samsung,exynos5433-pcie", }, + { }, }; static struct platform_driver exynos_pcie_driver = { + .probe = exynos_pcie_probe, .remove = __exit_p(exynos_pcie_remove), .driver = { .name = "exynos-pcie", .of_match_table = exynos_pcie_of_match, + .pm = &exynos_pcie_pm_ops, }, }; - -/* Exynos PCIe driver does not allow module unload */ - -static int __init exynos_pcie_init(void) -{ - return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); -} -subsys_initcall(exynos_pcie_init); +builtin_platform_driver(exynos_pcie_driver); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f70692ac79c5..8b93f0bba1f2 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2522,6 +2522,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disab DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); /* Disable MSI on chipsets that are known to not support it */ static void quirk_disable_msi(struct pci_dev *dev) From patchwork Mon Oct 19 09:47:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 11843913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9379C16BC for ; Mon, 19 Oct 2020 09:48:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69DEC2224D for ; Mon, 19 Oct 2020 09:48:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="PoE5kynM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727641AbgJSJsa (ORCPT ); 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Mon, 19 Oct 2020 09:47:40 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Date: Mon, 19 Oct 2020 11:47:15 +0200 Message-Id: <20201019094715.15343-7-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019094715.15343-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTURzGO7t3u3cXZ9dpeViRMbQoyLcsLqQyRWJEHyToQ4Hp0psz3Wab s+xDDM2Xpmn2RR2hNtN0atoUy5XlZDhruUmSjXJRkZKVqWlivlS7XrNvv//zf57zHA4HR4RG rgjPUObQaqUsS8wj0J7BX64DfSnXk8MH56KoO/lyqs7m5FLu5SIu1bxQg1EjE2U8yuXqxKhR yy0eNVxr51HVricc6tvKZ4xqt3kwqrDPhlG940OIRCBtq20D0l6DB5PWm7VSs+kaT1rebQJS u/sBRzpv3pWInSai0+isjFxaHRabQsgHuxbR7KWgS5MtXzk6UCnSAz4OySjY396IMiwkmwEs HPHTA8LLCwCuPS9F2WEewCrbHOdfomn26sbiLoAFy6vczYhnyMpjXDwyAuqn9V7G8QBSApd+ UowHIY0I1FXYAOPxJ0/C1oYaLsMoGQLLPeb1BgEZA1uGPmJsWxBs7exHGOaTsVB/uwlhDoJk EwYfzX5CWVMCLLbpAMv+8Iu9eyO8E/7preOwgQIAPzjbMXYoA3A0v3ojcQSOO5fXr4qQ+2CH JYyV46B7qhZlZEj6Qve0HyMjXrzZU4WwsgCWFAlZ9x5osN/brLWOvERYlsL7HYsI+0CVAJb2 z3BvgCDD/7J6AEwgkNZqFOm0JlJJXwzVyBQarTI9NFWlMAPvz3H8ti88BJbVswOAxIHYR/Be VZYs5MpyNXmKAQBxRBwgiB92nBEK0mR5l2m1KlmtzaI1A2AHjooDBQeNU0lCMl2WQ2fSdDat /rfl4HyRDpQ7HRdUM+CEIYMoeNfaKelG88nHFGFwCwmr4Zlxi4+u+xR/t49pMtw3JtHNn8tU /sgdMCccU56PdlyZeyrpshjfFhvHDxEr8Q1d2rbg7y758Sxi696kmfa1YGe59cVY0GGLOxWt efXm3FFH3LioornFoWwci3w9sb1kW0iCGNXIZRH7EbVG9hejNuGuNQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4Xd29Cb3xBre/CFosacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL1r1H2C12 3jnB7MDrsWbeGkaPnbPusnss2FTqsWlVJ5tH35ZVjB7Hb2xn8vi8SS6APUrPpii/tCRVISO/ uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7MstUjfLkEv49jmbywFP+Qrnq18zdTA OFGqi5GTQ0LARGLZhxaWLkYuDiGBpYwS7e8+sEMkZCROTmtghbCFJf5c62KDKPrEKLF373o2 kASbgKFE19suMFtEwEni/eSLzCBFzAJrmCUa27qZQBLCAsESz35+AZvKIqAq0Xd3E1icV8BW YuWJR1Db5CVWbzjADGJzCthJdC1cBmYLAdV0rZzGMoGRbwEjwypGkdTS4tz03GIjveLE3OLS vHS95PzcTYzAGNh27OeWHYxd74IPMQpwMCrx8D7I74kXYk0sK67MPcQowcGsJMLrdPZ0nBBv SmJlVWpRfnxRaU5q8SFGU6CjJjJLiSbnA+MzryTe0NTQ3MLS0NzY3NjMQkmct0PgYIyQQHpi SWp2ampBahFMHxMHp1QDY6Lhj30l1obKM7Yazlr5Sag65qdtYm6NH1+V2/WemnUnL1/e2pGX ztwZ//ux69lWu67L2o+96mb83H6bKUlxUVr7Cx+OC6crdjFcPaS60iFslvJiHvOCns5Zunf3 675bKXWxV/r8lN/xt+/cDTS1fpi4lNci8k1nQNPxaoFZ9bP7sn+nTnz/X4mlOCPRUIu5qDgR AJeb1f2XAgAA X-CMS-MailID: 20201019094741eucas1p1b4934cd5024a18804fcee921294acee0 X-Msg-Generator: CA X-RootMTR: 20201019094741eucas1p1b4934cd5024a18804fcee921294acee0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201019094741eucas1p1b4934cd5024a18804fcee921294acee0 References: <20201019094715.15343-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jaehoon Chung Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC). Signed-off-by: Jaehoon Chung [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split] Signed-off-by: Marek Szyprowski --- .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +- .../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 9df7c65593a1..32a6518517e5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -329,7 +329,7 @@ }; pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 829fea23d4ab..ef45ef86c48d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -969,6 +969,25 @@ bus-width = <4>; }; +&pcie { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, + <&cmu_top CLK_MOUT_SCLK_PCIE_100>; + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <100000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pcie_phy { + status = "okay"; +}; + &ppmu_d0_general { status = "okay"; events { @@ -1085,8 +1104,11 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; + pcie_wlanen: pcie-wlanen { + PIN(INPUT, gpj2-0, UP, FAST_SR4); + }; + initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); PIN(INPUT, gpj2-1, DOWN, FAST_SR1); PIN(INPUT, gpj2-2, DOWN, FAST_SR1); }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8eb4576da8f3..be2d1753d1d1 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1029,6 +1029,11 @@ reg = <0x145f0000 0x1038>; }; + syscon_fsys: syscon@156f0000 { + compatible = "syscon"; + reg = <0x156f0000 0x1044>; + }; + gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; @@ -1830,6 +1835,37 @@ status = "disabled"; }; }; + + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, + <0x0c000000 0x1000>; + reg-names = "elbi", "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, + <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + num-lanes = <1>; + bus-range = <0x00 0xff>; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + status = "disabled"; + }; }; timer: timer {