From patchwork Mon Oct 19 18:23:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11844905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F26D16BC for ; Mon, 19 Oct 2020 18:22:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C9C6223B0 for ; Mon, 19 Oct 2020 18:22:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bFyiA3Ag" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730552AbgJSSWq (ORCPT ); Mon, 19 Oct 2020 14:22:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730464AbgJSSWq (ORCPT ); Mon, 19 Oct 2020 14:22:46 -0400 Received: from mail-ot1-x344.google.com (mail-ot1-x344.google.com [IPv6:2607:f8b0:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571ECC0613D1 for ; Mon, 19 Oct 2020 11:22:46 -0700 (PDT) Received: by mail-ot1-x344.google.com with SMTP id m22so558908ots.4 for ; Mon, 19 Oct 2020 11:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8WNcSTvyJjqPsluOX/aQHxo6wZkO11EjVoorR/ZeenI=; b=bFyiA3AgOGUPXSmlD9ln5iZpm2IIkGqCKw/60r0m/Cx4zD4T3E0nqY3ega31Z0G4VI HDUVN+RNPyfDT0q1cl1jJmiVwmTvX9jinwXYJYbBO3AndeqrWxw9dVVpqQzIYbBazf7H sFyncVWqYaHCD3gaVlMmsB9+whr4jlJXjuZGiOiz6r6vM7Capkd+ZH8KYvwXBixNTfkz snT5x1MjjB3Tqh6MJxwHwZXcrbpI/im+BZUPMW/HSglDnM1XQeQHpOfD//3cc8O2jngy gy+dOM9EIubZPx/PXHr2KXGetlHK0fHHNO46kQjJzJg3dJ32eb+R5nzuubOOtwvCFcYe 17Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8WNcSTvyJjqPsluOX/aQHxo6wZkO11EjVoorR/ZeenI=; b=UMI32iOUuzDi/PLXgWC4EDSHoLywbUYkSFDVRCJCbDbjVXs8hVAccZ21eij6nWE5mA I3mSTg7BUe08bY8k0ZSS4eObqxRWK5/MFNz7YjcIS4583VcODuJk+LfyqkKmG5vw1Kn0 FCBdFwQSCQBG5s+g6Mk8ORQDqYrj0x3pKkqbUXL2HXZUZ1q6lfCvVTmpWcxOv1e0xjpY SKlECi5UyUtTGGabYryJIagbWAkvnN2uIuQAVD6esRPbM5q8O2aUT/r1wQfZN+nmaZ7W eDxJS4VCE0yITDcA8RuXh87KYvUGx/iFz2HOZvee+uMW2QZzj/Fqy/Cn+w2x3Ir1aCGu wOLg== X-Gm-Message-State: AOAM532QxFYIA6AOQTxugNQuhzO7A83rz0hWeqPLRZKSlFaQyYyLEQvJ hR90dOnTzzVgu9HNlGuUQU+MoQ== X-Google-Smtp-Source: ABdhPJzVeqVCQDNjLcs4loM+bM++jSYOB3qz5YDAugy+gXljNRXkI2CN8pviTsuIzrWxZhciQsuOTw== X-Received: by 2002:a05:6830:2368:: with SMTP id r8mr915212oth.75.1603131765704; Mon, 19 Oct 2020 11:22:45 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id o8sm175296oog.47.2020.10.19.11.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 11:22:45 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Sai Prakash Ranjan , Jordan Crouse , Thierry Reding , Rob Clark Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 1/3] iommu/arm-smmu: Allow implementation specific write_s2cr Date: Mon, 19 Oct 2020 11:23:21 -0700 Message-Id: <20201019182323.3162386-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019182323.3162386-1-bjorn.andersson@linaro.org> References: <20201019182323.3162386-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The firmware found in some Qualcomm platforms intercepts writes to the S2CR register in order to replace the BYPASS type with FAULT. Further more it treats faults at this level as catastrophic and restarts the device. Add support for providing implementation specific versions of the S2CR write function, to allow the Qualcomm driver to work around this behavior. Reviewed-by: Robin Murphy Signed-off-by: Bjorn Andersson --- Changes since v4: - Return early instead of indenting the rest of the function drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 ++++++++++--- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index dad7fa86fbd4..bcbacf22331d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -929,9 +929,16 @@ static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) { struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; - u32 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, s2cr->type) | - FIELD_PREP(ARM_SMMU_S2CR_CBNDX, s2cr->cbndx) | - FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); + u32 reg; + + if (smmu->impl && smmu->impl->write_s2cr) { + smmu->impl->write_s2cr(smmu, idx); + return; + } + + reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, s2cr->type) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, s2cr->cbndx) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && smmu->smrs[idx].valid) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 1a746476927c..b71647eaa319 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -436,6 +436,7 @@ struct arm_smmu_impl { int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, struct device *dev, int start); + void (*write_s2cr)(struct arm_smmu_device *smmu, int idx); }; #define INVALID_SMENDX -1 From patchwork Mon Oct 19 18:23:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11844911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41E9A16BC for ; Mon, 19 Oct 2020 18:23:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C485223AC for ; Mon, 19 Oct 2020 18:23:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OTz9mUw0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727328AbgJSSW7 (ORCPT ); Mon, 19 Oct 2020 14:22:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730710AbgJSSWt (ORCPT ); Mon, 19 Oct 2020 14:22:49 -0400 Received: from mail-ot1-x342.google.com (mail-ot1-x342.google.com [IPv6:2607:f8b0:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A73CDC0613D0 for ; Mon, 19 Oct 2020 11:22:47 -0700 (PDT) Received: by mail-ot1-x342.google.com with SMTP id h62so525325oth.9 for ; Mon, 19 Oct 2020 11:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y5fNqoL1fwVXzRoGLdhjgGjKn0H5ZhfiH9MEwllD/6E=; b=OTz9mUw0OYOkF+/xpWHYVhItGhBW6akviDkDx1yCTgro7wI2gTIkIonv6xdt4B4uuw gslPeIfjwSYj39iPXBJZAhq9tJruKkYVR5wwfJV1IzfXuat2vAQGzRQw+D94UU/BHXrt anK2LjGHLKW1i17ayHJh3wwgG8K8VTsZwP4vzNvCKrQwXq/2cHt8ldkIqSgXz4P8lOTp 20q8teCg7ioBGrKxxo24rhD/R02SS7Tj5vr4kJAFoS6HvIHKZ0fLjCD7BIPN2eph2BB+ zHL3pVc+idQf+fYjuc+FLxmnc9JvxuLOMQw6u8U2BR4TevDJnbKT7Gduugq+W1ZYotXV P6ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y5fNqoL1fwVXzRoGLdhjgGjKn0H5ZhfiH9MEwllD/6E=; b=E7jbYyD6gSDZAHxLkplu6FUHFIo0Rb1fLWymFqxoNCF9sqkw2qNyPpIsXOtoOcEDEn vm6VtzuAiW0MjUOkKjGQ/9NIGB1xs1epF+/iinJhPZNUtHzRbfDMMLHReXegzXUqJ0U4 7qfDjPWGAnov+wUehFpJql22zglC/UjqYAkAUnJHrVTyWh+W02VEQ1J1Omj/KiRwoN0l 8kSFXTC3UiIrYzh0K//UINC0Bk6CenS/uXxXfYiv7GeA08T3YJAvf4IB2ZDo07jbFvxE QiCDxjpI0ENo5O+ylWT7I83p1e9UzjwpLM2Pjj8CINsRvSEhZFD8bUZ/k1M0Ppn3lv1J n+RQ== X-Gm-Message-State: AOAM5332ZAHyYpfw2sTela3IifPzvHKUYCKFTWurYaV3mF2Rf5CJzm8/ L/O5jsBFL/dz0va1V3MfnmtIQ6GsjWN+UA== X-Google-Smtp-Source: ABdhPJz3wQQ65x7rCRGuRiOD/lEinJpwbkX3sUptNu3HmaIQTCVTBlcQfpdKY5yqjTfNAFucQx80DQ== X-Received: by 2002:a05:6830:19fd:: with SMTP id t29mr868207ott.307.1603131767028; Mon, 19 Oct 2020 11:22:47 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id o8sm175296oog.47.2020.10.19.11.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 11:22:46 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Sai Prakash Ranjan , Jordan Crouse , Thierry Reding , Rob Clark Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 2/3] iommu/arm-smmu-qcom: Read back stream mappings Date: Mon, 19 Oct 2020 11:23:22 -0700 Message-Id: <20201019182323.3162386-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019182323.3162386-1-bjorn.andersson@linaro.org> References: <20201019182323.3162386-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm boot loader configures stream mapping for the peripherals that it accesses and in particular it sets up the stream mapping for the display controller to be allowed to scan out a splash screen or EFI framebuffer. Read back the stream mappings during initialization and make the arm-smmu driver maintain the streams in bypass mode. Signed-off-by: Bjorn Andersson Acked-by: Robin Murphy --- Changes since v4: - Don't increment s2cr[i]->count, as this is not actually needed to survive probe deferral drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index be4318044f96..48627fcf6bed 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -23,6 +23,28 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { } }; +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) +{ + u32 smr; + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + } + } + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -61,6 +83,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; From patchwork Mon Oct 19 18:23:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11844909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBFA914B4 for ; Mon, 19 Oct 2020 18:22:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB0DA223AC for ; Mon, 19 Oct 2020 18:22:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YrXdztVk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730723AbgJSSWt (ORCPT ); Mon, 19 Oct 2020 14:22:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730654AbgJSSWs (ORCPT ); Mon, 19 Oct 2020 14:22:48 -0400 Received: from mail-oi1-x242.google.com (mail-oi1-x242.google.com [IPv6:2607:f8b0:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6BD0C0613CE for ; Mon, 19 Oct 2020 11:22:48 -0700 (PDT) Received: by mail-oi1-x242.google.com with SMTP id l85so931468oih.10 for ; Mon, 19 Oct 2020 11:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3LEDkBR8wJEGqVwvG1n0vRZnt/gLCojl7HrdvEA23Ug=; b=YrXdztVk2xUzJpFj9keaplNRccfTfjsSp/1YpeMFBVOGa098MtUAjHt61JjJfsvx/w 7EKLabdjT74UjcZyARJs/+dEFCBrXaKQUCXVdXINEZn74DjZFX9xZpHprPKxlyFl4v7q 1IXwJueTvIPnVUUy5jqry7hlVBoPJstOWFATwNXXfQfByZWagKZZAej5cizJzQP0llFM cVHzvgqxTsGL3FeHLVjhsIybaxWtM6L8hPG5pnNywmmUeiEieclplkHhmKrxZGxFkFnh obpbsliy1aQ0//16iq5tEFV3B3LLNNHnDcGgNnXATsxulFTVxLPxNIkr7OJSSHCcd6uS UJog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3LEDkBR8wJEGqVwvG1n0vRZnt/gLCojl7HrdvEA23Ug=; b=cbqR1aufDGFGQ5reaX2MDFpHjUalya5Dcx3ivzAtmzdPe8+eN1qIO5r0Q/JVOk2Y0/ asdaikPOCpMzN2eCCfBj6A/MQB+iWa6AcmWDMdLaz8Vr/psEiKqTAjhw6vmbYdY3TT4w eDY2div9WYVd8oggeHJ9Q5NXmcyHnwqVKWmuBAsGAAXIGJ93+5CqxsBOVB+BvT0pG4Ql V2ky2pa5CKayk7zHqRFZ5aH1D6V+a8+NgcYztom6RxNa9AKIo4Qtlp6uNV0fnh7cSeLp AhOLZ1RmGihWzVv0BDYWeaEQW2ZoHxk7bobuUxKN02wkpJGGh4AuPRHoNJobgXhiMjSK GNlw== X-Gm-Message-State: AOAM531oWO6N7JYA1c+qczyOhIHm/Q1jXL/u2eTkFQcnzaUCXJ3wl7/m bHatQPxX2MWjT6UN5GSz6vJa1w== X-Google-Smtp-Source: ABdhPJz2Xt6yCi4zpBwEAH7Rya8QNBfEhDx9AF+q00be7ONZJMUUj3jtzUAoihEPhpft+Di3dh/oKQ== X-Received: by 2002:aca:b5c6:: with SMTP id e189mr495877oif.47.1603131768050; Mon, 19 Oct 2020 11:22:48 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id o8sm175296oog.47.2020.10.19.11.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 11:22:47 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Sai Prakash Ranjan , Jordan Crouse , Thierry Reding , Rob Clark Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v5 3/3] iommu/arm-smmu-qcom: Implement S2CR quirk Date: Mon, 19 Oct 2020 11:23:23 -0700 Message-Id: <20201019182323.3162386-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019182323.3162386-1-bjorn.andersson@linaro.org> References: <20201019182323.3162386-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The firmware found in some Qualcomm platforms intercepts writes to S2CR in order to replace bypass type streams with fault; and ignore S2CR updates of type fault. Detect this behavior and implement a custom write_s2cr function in order to trick the firmware into supporting bypass streams by the means of configuring the stream for translation using a reserved and disabled context bank. Also circumvent the problem of configuring faulting streams by configuring the stream as bypass. Signed-off-by: Bjorn Andersson Acked-by: Robin Murphy --- Changes since v4: - Made the bypass_cbndx an integer... - Separated out the "quirk enabled or not" into a bool, rather than reusing (the valid) context bank 0 to represent this. - Dropped the unused EXIDS handling. drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 48627fcf6bed..66ba4870659f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -10,8 +10,15 @@ struct qcom_smmu { struct arm_smmu_device smmu; + bool bypass_quirk; + u8 bypass_cbndx; }; +static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) +{ + return container_of(smmu, struct qcom_smmu, smmu); +} + static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, { .compatible = "qcom,mdp4" }, @@ -25,9 +32,33 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { + unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + u32 reg; u32 smr; int i; + /* + * With some firmware versions writes to S2CR of type FAULT are + * ignored, and writing BYPASS will end up written as FAULT in the + * register. Perform a write to S2CR to detect if this is the case and + * if so reserve a context bank to emulate bypass streams. + */ + reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); + arm_smmu_gr0_write(smmu, last_s2cr, reg); + reg = arm_smmu_gr0_read(smmu, last_s2cr); + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { + qsmmu->bypass_quirk = true; + qsmmu->bypass_cbndx = smmu->num_context_banks - 1; + + set_bit(qsmmu->bypass_cbndx, smmu->context_map); + + reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); + arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); + } + for (i = 0; i < smmu->num_mapping_groups; i++) { smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); @@ -45,6 +76,41 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) return 0; } +static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) +{ + struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + u32 cbndx = s2cr->cbndx; + u32 type = s2cr->type; + u32 reg; + + if (qsmmu->bypass_quirk) { + if (type == S2CR_TYPE_BYPASS) { + /* + * Firmware with quirky S2CR handling will substitute + * BYPASS writes with FAULT, so point the stream to the + * reserved context bank and ask for translation on the + * stream + */ + type = S2CR_TYPE_TRANS; + cbndx = qsmmu->bypass_cbndx; + } else if (type == S2CR_TYPE_FAULT) { + /* + * Firmware with quirky S2CR handling will ignore FAULT + * writes, so trick it to write FAULT by asking for a + * BYPASS. + */ + type = S2CR_TYPE_BYPASS; + cbndx = 0xff; + } + } + + reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -86,6 +152,7 @@ static const struct arm_smmu_impl qcom_smmu_impl = { .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, + .write_s2cr = qcom_smmu_write_s2cr, }; struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)