From patchwork Tue Oct 20 15:39:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11847223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7AE117EC for ; Tue, 20 Oct 2020 15:40:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0F4C22256 for ; Tue, 20 Oct 2020 15:40:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oPgVstJm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436476AbgJTPj7 (ORCPT ); Tue, 20 Oct 2020 11:39:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436585AbgJTPj7 (ORCPT ); Tue, 20 Oct 2020 11:39:59 -0400 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CD0BC0613CE for ; Tue, 20 Oct 2020 08:39:59 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id x13so1386019pfa.9 for ; Tue, 20 Oct 2020 08:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=j+khgH0MVIdJPaYX4utAX0es0a1KBkt69gVm+UB8Z4U=; b=oPgVstJm/GTDbaGWM7jcq/Uo9Nnh4x77ot8se5J5bt5HR2KA1Lv2KzToDfz2aWTXh5 aBP9E9az9VUt8LNXiCa9JVwdeN/xYFseaM551GO61zDyPfyT819yoES8CApi4r0KkAYX YgdV2mhla3gRtXIAUMpHFKvXTcv8XlYT6hRfFdGP8oPg2v8xJUtsYI7FVzpTrQ6fXZpU pFFOC1XJM3apbzky92WspPyFvG+3NDh7XOl+SJJMLhARV5uUzdVIVdtEZzOntoZot2YQ nLfyONeMnPQAjwjyd61WW04hToRgXaiFgFXFv6sW+0gppLYA//JEQEhskovL1d/013Gg QGsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=j+khgH0MVIdJPaYX4utAX0es0a1KBkt69gVm+UB8Z4U=; b=TnTg3jtGBw/6ng7IVzsqQAg1NsUPtgp7tDsHeKfpnKg3AufeCy3iXUr0zWvd8Z21y7 Ct2u2gE+yZNHGEVRM5JEPAsRfHJQetmIRoCycad12keEIBA+NKMldE4VjmJ8wPLmunQ5 8DOZOUnGgvw0fNQUzX3/I9HunowyuUfL7hY6857brmcgN9zQG4xHpSrQtrZWCnoxpXif vS/kL/UuMb0RYMqKR8Qj1aGd49oiFYsGTk4LUaUAl4RadFjrrwFYv4fFL64Wqpvoo5wO bPoTKNOaVf+u3DXRJk88lUF3YZG/7I8ZrCfI3c2AwDevQkM2g9T+Almc1XIL5hav3OLi szMg== X-Gm-Message-State: AOAM533Wf5EpaGtrqMcBa+SA19XywBDKWN3cTDEiIsY7NzYaRb0yQXMJ gYd7JyNN4lvAOlQ9Y9LrPDNW X-Google-Smtp-Source: ABdhPJzZqwElgQxECe0/n3fGOzHgIe5k5ae035R+ZBZfDJg9xvXgmNdTqVBPRdbUmkUqoOT0c6GzvA== X-Received: by 2002:a65:690b:: with SMTP id s11mr3162192pgq.327.1603208398420; Tue, 20 Oct 2020 08:39:58 -0700 (PDT) Received: from Mani-XPS-13-9360.localdomain ([2409:4072:6c87:595a:f155:68:b391:69]) by smtp.gmail.com with ESMTPSA id r19sm2304961pjo.23.2020.10.20.08.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 08:39:57 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 1/2] dt-bindings: arm: cpus: Document 'qcom,freq-domain' property Date: Tue, 20 Oct 2020 21:09:43 +0530 Message-Id: <20201020153944.18047-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree documentation for 'qcom,freq-domain' property specific to Qualcomm CPUs. This property is used to reference the CPUFREQ node along with Domain ID (0/1). Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 1222bf1831fa..f40564bf004f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -290,6 +290,12 @@ properties: * arm/msm/qcom,kpss-acc.txt + qcom,freq-domain: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + CPUs supporting freq-domain must set their "qcom,freq-domain" property + with phandle to a cpufreq_hw node followed by the Domain ID(0/1). + rockchip,pmu: $ref: '/schemas/types.yaml#/definitions/phandle' description: | From patchwork Tue Oct 20 15:39:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11847225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5504C17D5 for ; Tue, 20 Oct 2020 15:40:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 140C82224A for ; Tue, 20 Oct 2020 15:40:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gorOocGf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436674AbgJTPkG (ORCPT ); Tue, 20 Oct 2020 11:40:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436671AbgJTPkF (ORCPT ); Tue, 20 Oct 2020 11:40:05 -0400 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9623C0613CE for ; Tue, 20 Oct 2020 08:40:05 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id t4so1200989plq.13 for ; Tue, 20 Oct 2020 08:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hwouX8woVh+Q6HrDNSE9yfwdkGO5vLYoKBeAXW/VZiM=; b=gorOocGfPtkuGwmnxjIoV2PmmWuI97mCB+pPzbe60U2bIA7sciuTCSMQU/RsFWG+A4 xhuK44SKablc0LkNQP7oFMdNkelTa854rn+WetqB+PvO8c6a3EQokj08M5gkQsvbt6O6 ffGLodeqtZ3zlmQxjhSi+tnYWsLf7vwtr6mhb+hBG/pno1uapbsjYvmrYl7x7CEfHO34 pdmHMqhcjmAfE1nENZYPlfgG9ED6ml8M3aRJ30qAQnhoKFAQ5Sy+eGNXyFsCEBX8MHsE bozDO5GMj0f2yIcKfdIWvdpHMuJcetCAkV3bWVDoUrRWuRRkV2udUJuBe0XLlzYpjD40 WeSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hwouX8woVh+Q6HrDNSE9yfwdkGO5vLYoKBeAXW/VZiM=; b=e/egGnKkspORoPe4LSRsva8gkt98WCwJnvMMZSkkbxMrI9UFn+vPUJO3HbamuEW8ga DrUMPBKPqw5OzPXpO4xQKFmnzI7FSAPfrp50KRV5O2RZjxRXikRZrvD9x3eSHxg3mhgA 4RwKRKKneNiJI5Fi/kLGk6MtcDKptgy3F3UW/lksHkgAlJXtHnJuzzPdy29IArv0xUeS Ld520kKH+u6PFHE8GCVHbfyk6gwOGktroxTiv0LJKUbts5hK6j+FIzI+XA/j0owyLoGP OTi57lSLps3e9ORjt0w2onECpVIa0fsaYHmh5LWI51hFRbozL7JdXKtw+gVQe6AeWnES xLug== X-Gm-Message-State: AOAM530WHle0EAS2RMxBDbnQP50AF0ZJ6lvFKlHsmSCz6IgatOXDWnOu F6uJBo6/ENawvbIoEO1JwF+5 X-Google-Smtp-Source: ABdhPJzrONiNsSPv56sKx0n8v2U5xuCV5rjJDWBNb+TqNrCT8wfwwVlCr7AglcPNGE35CcJPelNnpA== X-Received: by 2002:a17:90a:b30b:: with SMTP id d11mr3164776pjr.163.1603208405082; Tue, 20 Oct 2020 08:40:05 -0700 (PDT) Received: from Mani-XPS-13-9360.localdomain ([2409:4072:6c87:595a:f155:68:b391:69]) by smtp.gmail.com with ESMTPSA id r19sm2304961pjo.23.2020.10.20.08.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 08:40:04 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 2/2] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings Date: Tue, 20 Oct 2020 21:09:44 +0530 Message-Id: <20201020153944.18047-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201020153944.18047-1-manivannan.sadhasivam@linaro.org> References: <20201020153944.18047-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert Qualcomm cpufreq devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Added "qcom,freq-domain" property to ARM CPU binding. .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204 ++++++++++++++++++ 2 files changed, 204 insertions(+), 172 deletions(-) delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index 9299028ee712..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,172 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequency -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". - -- clocks - Usage: required - Value type: From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: From common clock binding. - Definition: must be "xo", "alternate". - -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -- #freq-domain-cells: - Usage: required. - Definition: Number of cells in a freqency domain specifier. - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property with -phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch -DCVS state together. - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; - reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml new file mode 100644 index 000000000000..bc81b6203e27 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Manivannan Sadhasivam + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw + + - description: v2 of CPUFREQ HW (EPSS) + items: + - enum: + - qcom,sm8250-cpufreq-epss + - const: qcom,cpufreq-epss + + reg: + minItems: 2 + maxItems: 3 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: freq-domain0 + - const: freq-domain1 + - const: freq-domain2 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + '#freq-domain-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster + // switch DCVS state together. + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + }; +...