From patchwork Wed Oct 21 20:12:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11849701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 982291580 for ; Wed, 21 Oct 2020 20:11:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65AE62419A for ; Wed, 21 Oct 2020 20:11:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AnGy9r3R" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505132AbgJUULv (ORCPT ); Wed, 21 Oct 2020 16:11:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505126AbgJUULu (ORCPT ); Wed, 21 Oct 2020 16:11:50 -0400 Received: from mail-ot1-x342.google.com (mail-ot1-x342.google.com [IPv6:2607:f8b0:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF3D6C0613D6 for ; Wed, 21 Oct 2020 13:11:49 -0700 (PDT) Received: by mail-ot1-x342.google.com with SMTP id f10so3033776otb.6 for ; Wed, 21 Oct 2020 13:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qB8P/6WO1D6RZP2Pmqy7a+v/iyOu8tobujQ8YoHYu9I=; b=AnGy9r3RaoiobqjMi1OhPVgQAkMoaUMobsDw3HMdNpbDxPb8FNA4oJzYnCIeq/+Mhy ycqSFIMTNOrkzeSBI/hljp9SxfKD7XP/GTtZJ6S7EE7XU7t5gRrr/YBJXdP3cGmY210s Fp2JT+PeoDJX8YWBCV9wDAeTrtZDRJAAoIMmRVR2ep4lcBcRSQbcm87zfy+h0Ne/0Kiv TUn7O67/Me13fRrKkigibHhCpJgzr2r1cMWaE/3ijIl/Cg7SH+MX9NQpcXG0FhO+vuQD gd2zBWGH5qii83CBsGnxkf/t5exldlS09wgDEkU5YiHri6G8YLFRNo2d3//6WmiZxM1o 8iGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qB8P/6WO1D6RZP2Pmqy7a+v/iyOu8tobujQ8YoHYu9I=; b=DD3vjg9LEBjMX10dc8yW1cCUSl2rFCWiZ04nc0a1FKnStioRBNIfybOAHwlW+3SyT6 X8CWOdNynoiP0vWYjpr1aZY3nTxp8Wnuodu6OZ75ZYi1aRl082o5pviX+nyIkFTn0hDV GnoRas5uWQzh6jL8mNynUT7kq0CIVHNsvePx+O9g4STTNL4b8H2CoCsb4kxhGRMD+GBF LER8hNXJK0zEQ2Wf56pamE16fF+sV9gy4MLl+6AaaqvOTNQXZZIa01zZbqPBQAOV7r/9 JSVyEw81XbObM4QaJWJ7WWa88aVD/KMdW3RW6Jp/Cl/t2D3/8UunwiBBLS6511oriZbF 80hA== X-Gm-Message-State: AOAM532pHgeiOYMOAmh/yZ1DV7baziAR6mWm+Vl3hUMXAaqwDRZLbL+I /UycI+aetE7D3SNmm6uyWl3aHQ== X-Google-Smtp-Source: ABdhPJyDgqkT/pt/hrWNYpqUXUrfNe7GQUKRCVxdMSeS1moog0IYT2oQ9rDKMKSIAWkGLUbyusJ6SA== X-Received: by 2002:a9d:73c6:: with SMTP id m6mr3795879otk.105.1603311109298; Wed, 21 Oct 2020 13:11:49 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id t5sm838166otl.22.2020.10.21.13.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 13:11:48 -0700 (PDT) From: Bjorn Andersson To: Pavel Machek , Dan Murphy , Rob Herring , Andy Gross , Bjorn Andersson , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lee Jones , Martin Botka Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org Subject: [PATCH v6 1/4] dt-bindings: leds: Add Qualcomm Light Pulse Generator binding Date: Wed, 21 Oct 2020 13:12:21 -0700 Message-Id: <20201021201224.3430546-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201021201224.3430546-1-bjorn.andersson@linaro.org> References: <20201021201224.3430546-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds the binding document describing the three hardware blocks related to the Light Pulse Generator found in a wide range of Qualcomm PMICs. Signed-off-by: Bjorn Andersson --- Changes since v5: - None .../bindings/leds/leds-qcom-lpg.yaml | 170 ++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml diff --git a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml new file mode 100644 index 000000000000..5ccf0f3d8f1b --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Light Pulse Generator + +maintainers: + - Bjorn Andersson + +description: > + The Qualcomm Light Pulse Generator consists of three different hardware blocks; + a ramp generator with lookup table, the light pulse generator and a three + channel current sink. These blocks are found in a wide range of Qualcomm PMICs. + +properties: + compatible: + enum: + - qcom,pm8916-pwm + - qcom,pm8941-lpg + - qcom,pm8994-lpg + - qcom,pmi8994-lpg + - qcom,pmi8998-lpg + + "#pwm-cells": + const: 2 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,power-source: + $ref: /schemas/types.yaml#definitions/uint32 + description: > + power-source used to drive the output, as defined in the datasheet. + Should be specified if the TRILED block is present + enum: + - 0 + - 1 + - 3 + + multi-led: + type: object + $ref: leds-class-multicolor.yaml# + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + + properties: + "qcom,dtest": + $ref: /schemas/types.yaml#definitions/uint32-array + description: > + configures the output into an internal test line of the pmic. Specified + by a list of u32 pairs, one pair per channel, where each pair denotes the + test line to drive and the second configures how the value should be + outputed, as defined in the datasheet + minItems: 2 + maxItems: 2 + + required: + - reg + +patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + properties: + "qcom,dtest": + $ref: /schemas/types.yaml#definitions/uint32-array + description: > + configures the output into an internal test line of the pmic. Specified + by a list of u32 pairs, one pair per channel, where each pair denotes the + test line to drive and the second configures how the value should be + outputed, as defined in the datasheet + minItems: 2 + maxItems: 2 + + required: + - reg + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + led@1 { + reg = <1>; + label = "green:user1"; + }; + + led@2 { + reg = <2>; + label = "green:user0"; + default-state = "on"; + }; + + led@3 { + reg = <3>; + label = "green:user2"; + }; + + led@4 { + reg = <4>; + label = "green:user3"; + + qcom,dtest = <4 1>; + }; + }; + - | + #include + + lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + multi-led { + color = ; + label = "rgb:notification"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; + }; + - | + lpg { + compatible = "qcom,pm8916-pwm"; + #pwm-cells = <2>; + }; +... From patchwork Wed Oct 21 20:12:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11849703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7177914B4 for ; Wed, 21 Oct 2020 20:11:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30E2124198 for ; Wed, 21 Oct 2020 20:11:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XPrpX2eD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505142AbgJUULx (ORCPT ); Wed, 21 Oct 2020 16:11:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505135AbgJUULw (ORCPT ); Wed, 21 Oct 2020 16:11:52 -0400 Received: from mail-ot1-x342.google.com (mail-ot1-x342.google.com [IPv6:2607:f8b0:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EEEAC0613D5 for ; Wed, 21 Oct 2020 13:11:51 -0700 (PDT) Received: by mail-ot1-x342.google.com with SMTP id 32so3054004otm.3 for ; Wed, 21 Oct 2020 13:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oodlSNxO/ySemIeyezX7eBwlZ/EFFo7QAsf7rpgR3WY=; b=XPrpX2eDZ4Z0XcZydx2EpCNy0pf7uYo4a6MYeM7YqVeUZSl5XGLEnQvhtN+HagDssr kAMwUF5J5/zmEcqkYeZQoccJdJvlDMKezGEqcXpwum9mM8qryTGHPfRQQ2aX8+H/UxYd vIKm8ROndDk+qf/KsjCHSpCuMftlaCiMmcORDnb/eHlVkT85DReNuiRg1j7uKcMxma+6 pfsh7vvkkmniW5mNlkVmrpOl2gbyoK8jmBpdXGzbpkIzp26Dh2lQDdPRq6RtjPCLEjNF lydPskozxfEP7U+BgndIgZTaPvSk0Kbj2cMQ8rOMVs9eCUAxXzAymh2scUnlDVqrD0Z+ KN4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oodlSNxO/ySemIeyezX7eBwlZ/EFFo7QAsf7rpgR3WY=; b=pZiJwGKUg2Np9cKH80eklFSNE95ApW7Ply2wwTZ2ZZbw7Gq37bD2yDBaCDM+sck5hZ GrsKRp/pJrqQ8F9ZvHob0jTRIeY5Y5RlRVUOaFZ6mv6MjKdiMtR4Vhr1YlMohw/WJuuq 01PRnSaFqYHee8fCVYrZ3jZ26sKmB8yChBV0VTHySNKeVuB79O9YuwvHu3fFprxGq3FZ TrvNS3mgreLsmpTg/uHLd1DWNfXzpziVH6QT2doCuL8oCOungHKLexSTYP3C/N72hIQr N9qCjPiLRiByKXS2ZlZRPKUTyFbGVpQ2tKCRKUqOtLYo4saq6i5zOIYQxdvPzY+XhwVj m6Qw== X-Gm-Message-State: AOAM532RcSx8zOlNUjn61Q/+w+E6LHio6pDNcbs4uuG1wK16nmFGuViM Y4xA+WjEVg1CYjAZ2xuiAOX/IQ== X-Google-Smtp-Source: ABdhPJxbgEbHJ0mr0GekKJiZXS5cu7Paw1X/TAwWrXa8AEzZJllZlzkoC+8Rt09NwZDqGaJwOG/kkw== X-Received: by 2002:a05:6830:3081:: with SMTP id f1mr3583414ots.269.1603311110771; Wed, 21 Oct 2020 13:11:50 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id t5sm838166otl.22.2020.10.21.13.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 13:11:50 -0700 (PDT) From: Bjorn Andersson To: Pavel Machek , Dan Murphy , Rob Herring , Andy Gross , Bjorn Andersson , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lee Jones , Martin Botka Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org Subject: [PATCH v6 2/4] leds: Add driver for Qualcomm LPG Date: Wed, 21 Oct 2020 13:12:22 -0700 Message-Id: <20201021201224.3430546-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201021201224.3430546-1-bjorn.andersson@linaro.org> References: <20201021201224.3430546-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Light Pulse Generator (LPG) is a PWM-block found in a wide range of PMICs from Qualcomm. It can operate on fixed parameters or based on a lookup-table, altering the duty cycle over time - which provides the means for e.g. hardware assisted transitions of LED brightness. Signed-off-by: Bjorn Andersson Tested-by: Luca Weiss --- Changes since v5: - Make sure to not used the state of the last channel in a group to determine if the current sink should be active for all channels in the group. - Replacement of unsigned -1 with UINT_MAX - Work around potential overflow by using larger data types, instead of separate code paths - Use cpu_to_l16() rather than hand rolling them - Minor style cleanups drivers/leds/Kconfig | 9 + drivers/leds/Makefile | 1 + drivers/leds/leds-qcom-lpg.c | 1190 ++++++++++++++++++++++++++++++++++ 3 files changed, 1200 insertions(+) create mode 100644 drivers/leds/leds-qcom-lpg.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 849d3c5f908e..d500648c586f 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -803,6 +803,15 @@ config LEDS_POWERNV To compile this driver as a module, choose 'm' here: the module will be called leds-powernv. +config LEDS_QCOM_LPG + tristate "LED support for Qualcomm LPG" + depends on LEDS_CLASS_MULTICOLOR + depends on OF + depends on SPMI + help + This option enables support for the Light Pulse Generator found in a + wide variety of Qualcomm PMICs. + config LEDS_SYSCON bool "LED support for LEDs on system controllers" depends on LEDS_CLASS=y diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 73e603e1727e..52d0ea26fc35 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_LEDS_PCA963X) += leds-pca963x.o obj-$(CONFIG_LEDS_PM8058) += leds-pm8058.o obj-$(CONFIG_LEDS_POWERNV) += leds-powernv.o obj-$(CONFIG_LEDS_PWM) += leds-pwm.o +obj-$(CONFIG_LEDS_QCOM_LPG) += leds-qcom-lpg.o obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o diff --git a/drivers/leds/leds-qcom-lpg.c b/drivers/leds/leds-qcom-lpg.c new file mode 100644 index 000000000000..86131a65d2c5 --- /dev/null +++ b/drivers/leds/leds-qcom-lpg.c @@ -0,0 +1,1190 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020 Linaro Ltd + * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPG_PATTERN_CONFIG_REG 0x40 +#define LPG_SIZE_CLK_REG 0x41 +#define LPG_PREDIV_CLK_REG 0x42 +#define PWM_TYPE_CONFIG_REG 0x43 +#define PWM_VALUE_REG 0x44 +#define PWM_ENABLE_CONTROL_REG 0x46 +#define PWM_SYNC_REG 0x47 +#define LPG_RAMP_DURATION_REG 0x50 +#define LPG_HI_PAUSE_REG 0x52 +#define LPG_LO_PAUSE_REG 0x54 +#define LPG_HI_IDX_REG 0x56 +#define LPG_LO_IDX_REG 0x57 +#define PWM_SEC_ACCESS_REG 0xd0 +#define PWM_DTEST_REG(x) (0xe2 + (x) - 1) + +#define TRI_LED_SRC_SEL 0x45 +#define TRI_LED_EN_CTL 0x46 +#define TRI_LED_ATC_CTL 0x47 + +#define LPG_LUT_REG(x) (0x40 + (x) * 2) +#define RAMP_CONTROL_REG 0xc8 + +struct lpg_channel; +struct lpg_data; + +/** + * struct lpg - LPG device context + * @dev: struct device for LPG device + * @map: regmap for register access + * @pwm: PWM-chip object, if operating in PWM mode + * @lut_base: base address of the LUT block (optional) + * @lut_size: number of entries in the LUT block + * @lut_bitmap: allocation bitmap for LUT entries + * @triled_base: base address of the TRILED block (optional) + * @triled_src: power-source for the TRILED + * @channels: list of PWM channels + * @num_channels: number of @channels + */ +struct lpg { + struct device *dev; + struct regmap *map; + + struct pwm_chip pwm; + + const struct lpg_data *data; + + u32 lut_base; + u32 lut_size; + unsigned long *lut_bitmap; + + u32 triled_base; + u32 triled_src; + + struct lpg_channel *channels; + unsigned int num_channels; +}; + +/** + * struct lpg_channel - per channel data + * @lpg: reference to parent lpg + * @base: base address of the PWM channel + * @triled_mask: mask in TRILED to enable this channel + * @lut_mask: mask in LUT to start pattern generator for this channel + * @in_use: channel is exposed to LED framework + * @color: color of the LED attached to this channel + * @dtest_line: DTEST line for output, or 0 if disabled + * @dtest_value: DTEST line configuration + * @pwm_value: duty (in microseconds) of the generated pulses, overridden by LUT + * @enabled: output enabled? + * @period_us: period (in microseconds) of the generated pulses + * @pwm_size: resolution of the @pwm_value, 6 or 9 bits + * @clk: base frequency of the clock generator + * @pre_div: divider of @clk + * @pre_div_exp: exponential divider of @clk + * @ramp_enabled: duty cycle is driven by iterating over lookup table + * @ramp_ping_pong: reverse through pattern, rather than wrapping to start + * @ramp_oneshot: perform only a single pass over the pattern + * @ramp_reverse: iterate over pattern backwards + * @ramp_duration_ms: length (in milliseconds) of one pattern run + * @ramp_lo_pause_ms: pause (in milliseconds) before iterating over pattern + * @ramp_hi_pause_ms: pause (in milliseconds) after iterating over pattern + * @pattern_lo_idx: start index of associated pattern + * @pattern_hi_idx: last index of associated pattern + */ +struct lpg_channel { + struct lpg *lpg; + + u32 base; + unsigned int triled_mask; + unsigned int lut_mask; + + bool in_use; + + int color; + + u32 dtest_line; + u32 dtest_value; + + u16 pwm_value; + bool enabled; + + unsigned int period_us; + unsigned int pwm_size; + unsigned int clk; + unsigned int pre_div; + unsigned int pre_div_exp; + + bool ramp_enabled; + bool ramp_ping_pong; + bool ramp_oneshot; + bool ramp_reverse; + unsigned long ramp_duration_ms; + unsigned long ramp_lo_pause_ms; + unsigned long ramp_hi_pause_ms; + + unsigned int pattern_lo_idx; + unsigned int pattern_hi_idx; +}; + +/** + * struct lpg_led - logical LED object + * @lpg: lpg context reference + * @cdev: LED class device + * @mcdev: Multicolor LED class device + * @num_channels: number of @channels + * @channels: list of channels associated with the LED + */ +struct lpg_led { + struct lpg *lpg; + + struct led_classdev cdev; + struct led_classdev_mc mcdev; + + unsigned int num_channels; + struct lpg_channel *channels[]; +}; + +/** + * struct lpg_channel_data - per channel initialization data + * @base: base address for PWM channel registers + * @triled_mask: bitmask for controlling this channel in TRILED + */ +struct lpg_channel_data { + unsigned int base; + u8 triled_mask; +}; + +/** + * struct lpg_data - initialization data + * @lut_base: base address of LUT block + * @lut_size: number of entries in LUT + * @triled_base: base address of TRILED + * @pwm_9bit_mask: bitmask for switching from 6bit to 9bit pwm + * @num_channels: number of channels in LPG + * @channels: list of channel initialization data + */ +struct lpg_data { + unsigned int lut_base; + unsigned int lut_size; + unsigned int triled_base; + unsigned int pwm_9bit_mask; + int num_channels; + struct lpg_channel_data *channels; +}; + +static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable) +{ + /* Skip if we don't have a triled block */ + if (!lpg->triled_base) + return 0; + + return regmap_update_bits(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, + mask, enable); +} + +static int lpg_lut_store(struct lpg *lpg, struct led_pattern *pattern, + size_t len, unsigned int *lo_idx, unsigned int *hi_idx) +{ + unsigned int idx; + __le16 val; + int i; + + /* Hardware does not behave when LO_IDX == HI_IDX */ + if (len == 1) + return -EINVAL; + + idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, + 0, len, 0); + if (idx >= lpg->lut_size) + return -ENOMEM; + + for (i = 0; i < len; i++) { + val = cpu_to_le16(pattern[i].brightness); + + regmap_bulk_write(lpg->map, lpg->lut_base + LPG_LUT_REG(idx + i), + &val, sizeof(val)); + } + + bitmap_set(lpg->lut_bitmap, idx, len); + + *lo_idx = idx; + *hi_idx = idx + len - 1; + + return 0; +} + +static void lpg_lut_free(struct lpg *lpg, unsigned int lo_idx, unsigned int hi_idx) +{ + int len; + + if (lo_idx == hi_idx) + return; + + len = hi_idx - lo_idx + 1; + bitmap_clear(lpg->lut_bitmap, lo_idx, len); +} + +static int lpg_lut_sync(struct lpg *lpg, unsigned int mask) +{ + return regmap_write(lpg->map, lpg->lut_base + RAMP_CONTROL_REG, mask); +} + +#define NUM_PWM_PREDIV 4 +#define NUM_PWM_CLK 3 +#define NUM_EXP 7 + +static const unsigned int lpg_clk_table[NUM_PWM_PREDIV][NUM_PWM_CLK] = { + { + 1 * (NSEC_PER_SEC / 1024), + 1 * (NSEC_PER_SEC / 32768), + 1 * (NSEC_PER_SEC / 19200000), + }, + { + 3 * (NSEC_PER_SEC / 1024), + 3 * (NSEC_PER_SEC / 32768), + 3 * (NSEC_PER_SEC / 19200000), + }, + { + 5 * (NSEC_PER_SEC / 1024), + 5 * (NSEC_PER_SEC / 32768), + 5 * (NSEC_PER_SEC / 19200000), + }, + { + 6 * (NSEC_PER_SEC / 1024), + 6 * (NSEC_PER_SEC / 32768), + 6 * (NSEC_PER_SEC / 19200000), + }, +}; + +/* + * PWM Frequency = Clock Frequency / (N * T) + * or + * PWM Period = Clock Period * (N * T) + * where + * N = 2^9 or 2^6 for 9-bit or 6-bit PWM size + * T = Pre-divide * 2^m, where m = 0..7 (exponent) + * + * This is the formula to figure out m for the best pre-divide and clock: + * (PWM Period / N) = (Pre-divide * Clock Period) * 2^m + */ +static void lpg_calc_freq(struct lpg_channel *chan, unsigned int period_us) +{ + int n, m, clk, div; + int best_m, best_div, best_clk; + unsigned int last_err, cur_err, min_err; + unsigned int tmp_p, period_n; + + if (period_us == chan->period_us) + return; + + /* PWM Period / N */ + if (period_us < UINT_MAX / NSEC_PER_USEC) + n = 6; + else + n = 9; + + period_n = ((u64)period_us * NSEC_PER_USEC) >> n; + + min_err = UINT_MAX; + last_err = UINT_MAX; + best_m = 0; + best_clk = 0; + best_div = 0; + for (clk = 0; clk < NUM_PWM_CLK; clk++) { + for (div = 0; div < NUM_PWM_PREDIV; div++) { + /* period_n = (PWM Period / N) */ + /* tmp_p = (Pre-divide * Clock Period) * 2^m */ + tmp_p = lpg_clk_table[div][clk]; + for (m = 0; m <= NUM_EXP; m++) { + cur_err = abs(period_n - tmp_p); + if (cur_err < min_err) { + min_err = cur_err; + best_m = m; + best_clk = clk; + best_div = div; + } + + if (m && cur_err > last_err) + /* Break for bigger cur_err */ + break; + + last_err = cur_err; + tmp_p <<= 1; + } + } + } + + /* Use higher resolution */ + if (best_m >= 3 && n == 6) { + n += 3; + best_m -= 3; + } + + chan->clk = best_clk; + chan->pre_div = best_div; + chan->pre_div_exp = best_m; + chan->pwm_size = n; + + chan->period_us = period_us; +} + +static void lpg_calc_duty(struct lpg_channel *chan, unsigned int duty_us) +{ + unsigned int max = (1 << chan->pwm_size) - 1; + unsigned int val = div_u64((u64)duty_us << chan->pwm_size, chan->period_us); + + chan->pwm_value = min(val, max); +} + +static void lpg_apply_freq(struct lpg_channel *chan) +{ + unsigned long val; + struct lpg *lpg = chan->lpg; + + if (!chan->enabled) + return; + + /* Clock register values are off-by-one from lpg_clk_table */ + val = chan->clk + 1; + + if (chan->pwm_size == 9) + val |= lpg->data->pwm_9bit_mask; + + regmap_write(lpg->map, chan->base + LPG_SIZE_CLK_REG, val); + + val = chan->pre_div << 5 | chan->pre_div_exp; + regmap_write(lpg->map, chan->base + LPG_PREDIV_CLK_REG, val); +} + +#define LPG_ENABLE_GLITCH_REMOVAL BIT(5) + +static void lpg_enable_glitch(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG, + LPG_ENABLE_GLITCH_REMOVAL, 0); +} + +static void lpg_disable_glitch(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG, + LPG_ENABLE_GLITCH_REMOVAL, + LPG_ENABLE_GLITCH_REMOVAL); +} + +static void lpg_apply_pwm_value(struct lpg_channel *chan) +{ + __le16 val = cpu_to_le16(chan->pwm_value); + struct lpg *lpg = chan->lpg; + + if (!chan->enabled) + return; + + regmap_bulk_write(lpg->map, chan->base + PWM_VALUE_REG, &val, sizeof(val)); +} + +#define LPG_PATTERN_CONFIG_LO_TO_HI BIT(4) +#define LPG_PATTERN_CONFIG_REPEAT BIT(3) +#define LPG_PATTERN_CONFIG_TOGGLE BIT(2) +#define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1) +#define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0) + +static void lpg_apply_lut_control(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + unsigned int hi_pause; + unsigned int lo_pause; + unsigned int step; + unsigned int conf = 0; + unsigned int lo_idx = chan->pattern_lo_idx; + unsigned int hi_idx = chan->pattern_hi_idx; + int pattern_len; + + if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx) + return; + + pattern_len = hi_idx - lo_idx + 1; + + step = DIV_ROUND_UP(chan->ramp_duration_ms, pattern_len); + hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step); + lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step); + + if (!chan->ramp_reverse) + conf |= LPG_PATTERN_CONFIG_LO_TO_HI; + if (!chan->ramp_oneshot) + conf |= LPG_PATTERN_CONFIG_REPEAT; + if (chan->ramp_ping_pong) + conf |= LPG_PATTERN_CONFIG_TOGGLE; + if (chan->ramp_hi_pause_ms) + conf |= LPG_PATTERN_CONFIG_PAUSE_HI; + if (chan->ramp_lo_pause_ms) + conf |= LPG_PATTERN_CONFIG_PAUSE_LO; + + regmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf); + regmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx); + regmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx); + + regmap_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, step); + regmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause); + regmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause); +} + +#define LPG_ENABLE_CONTROL_OUTPUT BIT(7) +#define LPG_ENABLE_CONTROL_BUFFER_TRISTATE BIT(5) +#define LPG_ENABLE_CONTROL_SRC_PWM BIT(2) +#define LPG_ENABLE_CONTROL_RAMP_GEN BIT(1) + +static void lpg_apply_control(struct lpg_channel *chan) +{ + unsigned int ctrl; + struct lpg *lpg = chan->lpg; + + ctrl = LPG_ENABLE_CONTROL_BUFFER_TRISTATE; + + if (chan->enabled) + ctrl |= LPG_ENABLE_CONTROL_OUTPUT; + + if (chan->pattern_lo_idx != chan->pattern_hi_idx) + ctrl |= LPG_ENABLE_CONTROL_RAMP_GEN; + else + ctrl |= LPG_ENABLE_CONTROL_SRC_PWM; + + regmap_write(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, ctrl); + + /* + * Due to LPG hardware bug, in the PWM mode, having enabled PWM, + * We have to write PWM values one more time. + */ + if (chan->enabled) + lpg_apply_pwm_value(chan); +} + +#define LPG_SYNC_PWM BIT(0) + +static void lpg_apply_sync(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + regmap_write(lpg->map, chan->base + PWM_SYNC_REG, LPG_SYNC_PWM); +} + +static void lpg_apply_dtest(struct lpg_channel *chan) +{ + struct lpg *lpg = chan->lpg; + + if (!chan->dtest_line) + return; + + regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5); + regmap_write(lpg->map, chan->base + PWM_DTEST_REG(chan->dtest_line), + chan->dtest_value); +} + +static void lpg_apply(struct lpg_channel *chan) +{ + lpg_disable_glitch(chan); + lpg_apply_freq(chan); + lpg_apply_pwm_value(chan); + lpg_apply_control(chan); + lpg_apply_sync(chan); + lpg_apply_lut_control(chan); + lpg_enable_glitch(chan); +} + +static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev, + struct mc_subled *subleds) +{ + enum led_brightness brightness; + struct lpg_channel *chan; + unsigned int triled_enabled = 0; + unsigned int triled_mask = 0; + unsigned int lut_mask = 0; + unsigned int duty_us; + struct lpg *lpg = led->lpg; + int i; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + brightness = subleds[i].brightness; + + if (brightness == LED_OFF) { + chan->enabled = false; + chan->ramp_enabled = false; + } else if (chan->pattern_lo_idx != chan->pattern_hi_idx) { + lpg_calc_freq(chan, NSEC_PER_USEC); + + chan->enabled = true; + chan->ramp_enabled = true; + + lut_mask |= chan->lut_mask; + triled_enabled |= chan->triled_mask; + } else { + lpg_calc_freq(chan, NSEC_PER_USEC); + + duty_us = brightness * chan->period_us / cdev->max_brightness; + lpg_calc_duty(chan, duty_us); + chan->enabled = true; + chan->ramp_enabled = false; + + triled_enabled |= chan->triled_mask; + } + + triled_mask |= chan->triled_mask; + + lpg_apply(chan); + } + + /* Toggle triled lines */ + if (triled_mask) + triled_set(lpg, triled_mask, triled_enabled); + + /* Trigger start of ramp generator(s) */ + if (lut_mask) + lpg_lut_sync(lpg, lut_mask); +} + +static void lpg_brightness_single_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + struct mc_subled info; + + info.brightness = value; + lpg_brightness_set(led, cdev, &info); +} + +static void lpg_brightness_mc_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + led_mc_calc_color_components(mc, value); + lpg_brightness_set(led, cdev, mc->subled_info); +} + +static int lpg_blink_set(struct lpg_led *led, + unsigned long delay_on, unsigned long delay_off) +{ + struct lpg_channel *chan; + unsigned int period_us; + unsigned int duty_us; + int i; + + if (!delay_on && !delay_off) { + delay_on = 500; + delay_off = 500; + } + + duty_us = delay_on * USEC_PER_MSEC; + period_us = (delay_on + delay_off) * USEC_PER_MSEC; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + + lpg_calc_freq(chan, period_us); + lpg_calc_duty(chan, duty_us); + + chan->enabled = true; + chan->ramp_enabled = false; + + lpg_apply(chan); + } + + return 0; +} + +static int lpg_blink_single_set(struct led_classdev *cdev, + unsigned long *delay_on, unsigned long *delay_off) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + + return lpg_blink_set(led, *delay_on, *delay_off); +} + +static int lpg_blink_mc_set(struct led_classdev *cdev, + unsigned long *delay_on, unsigned long *delay_off) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + return lpg_blink_set(led, *delay_on, *delay_off); +} + +static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *pattern, + u32 len, int repeat) +{ + struct lpg_channel *chan; + struct lpg *lpg = led->lpg; + unsigned int hi_pause; + unsigned int lo_pause; + unsigned int lo_idx; + unsigned int hi_idx; + bool ping_pong = true; + int brightness_a; + int brightness_b; + int ret; + int i; + + /* Only support oneshot or indefinite loops, due to limited pattern space */ + if (repeat != -1 && repeat != 1) + return -EINVAL; + + /* + * The LPG plays patterns with at a fixed pace, a "low pause" can be + * performed before the pattern and a "high pause" after. In order to + * save space the pattern can be played in "ping pong" mode, in which + * the pattern is first played forward, then "high pause" is applied, + * then the pattern is played backwards and finally the "low pause" is + * applied. + * + * The delta_t of the first entry is used to determine the pace of the + * pattern. + * + * If the specified pattern is a palindrome the ping pong mode is + * enabled. In this scenario the delta_t of the last entry determines + * the "low pause" time and the delta_t of the middle entry (i.e. the + * last in the programmed pattern) determines the "high pause". If the + * pattern consists of an odd number of values, no "high pause" is + * used. + * + * When ping pong mode is not selected, the delta_t of the last entry + * is used as "high pause". No "low pause" is used. + * + * delta_t of any other members of the pattern is ignored. + */ + + /* Detect palindromes and use "ping pong" to reduce LUT usage */ + for (i = 0; i < len / 2; i++) { + brightness_a = pattern[i].brightness; + brightness_b = pattern[len - i - 1].brightness; + + if (brightness_a != brightness_b) { + ping_pong = false; + break; + } + } + + if (ping_pong) { + if (len % 2) + hi_pause = 0; + else + hi_pause = pattern[len + 1 / 2].delta_t; + lo_pause = pattern[len - 1].delta_t; + + len = (len + 1) / 2; + } else { + hi_pause = pattern[len - 1].delta_t; + lo_pause = 0; + } + + ret = lpg_lut_store(lpg, pattern, len, &lo_idx, &hi_idx); + if (ret < 0) + goto out; + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + + chan->ramp_duration_ms = pattern[0].delta_t * len; + chan->ramp_ping_pong = ping_pong; + chan->ramp_oneshot = repeat != -1; + + chan->ramp_lo_pause_ms = lo_pause; + chan->ramp_hi_pause_ms = hi_pause; + + chan->pattern_lo_idx = lo_idx; + chan->pattern_hi_idx = hi_idx; + } + +out: + return ret; +} + +static int lpg_pattern_single_set(struct led_classdev *cdev, + struct led_pattern *pattern, u32 len, + int repeat) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + int ret; + + ret = lpg_pattern_set(led, pattern, len, repeat); + if (ret < 0) + return ret; + + lpg_brightness_single_set(cdev, LED_FULL); + + return 0; +} + +static int lpg_pattern_mc_set(struct led_classdev *cdev, + struct led_pattern *pattern, u32 len, + int repeat) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + int ret; + + ret = lpg_pattern_set(led, pattern, len, repeat); + if (ret < 0) + return ret; + + led_mc_calc_color_components(mc, LED_FULL); + lpg_brightness_set(led, cdev, mc->subled_info); + + return 0; +} + +static int lpg_pattern_clear(struct lpg_led *led) +{ + struct lpg_channel *chan; + struct lpg *lpg = led->lpg; + int i; + + chan = led->channels[0]; + lpg_lut_free(lpg, chan->pattern_lo_idx, chan->pattern_hi_idx); + + for (i = 0; i < led->num_channels; i++) { + chan = led->channels[i]; + chan->pattern_lo_idx = 0; + chan->pattern_hi_idx = 0; + } + + return 0; +} + +static int lpg_pattern_single_clear(struct led_classdev *cdev) +{ + struct lpg_led *led = container_of(cdev, struct lpg_led, cdev); + + return lpg_pattern_clear(led); +} + +static int lpg_pattern_mc_clear(struct led_classdev *cdev) +{ + struct led_classdev_mc *mc = lcdev_to_mccdev(cdev); + struct lpg_led *led = container_of(mc, struct lpg_led, mcdev); + + return lpg_pattern_clear(led); +} + +static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpg *lpg = container_of(chip, struct lpg, pwm); + struct lpg_channel *chan = &lpg->channels[pwm->hwpwm]; + + return chan->in_use ? -EBUSY : 0; +} + +static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct lpg *lpg = container_of(chip, struct lpg, pwm); + struct lpg_channel *chan = &lpg->channels[pwm->hwpwm]; + + lpg_calc_freq(chan, div_u64(state->period, NSEC_PER_USEC)); + lpg_calc_duty(chan, div_u64(state->duty_cycle, NSEC_PER_USEC)); + chan->enabled = state->enabled; + + lpg_apply(chan); + + triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0); + + return 0; +} + +static const struct pwm_ops lpg_pwm_ops = { + .request = lpg_pwm_request, + .apply = lpg_pwm_apply, + .owner = THIS_MODULE, +}; + +static int lpg_add_pwm(struct lpg *lpg) +{ + int ret; + + lpg->pwm.base = -1; + lpg->pwm.dev = lpg->dev; + lpg->pwm.npwm = lpg->num_channels; + lpg->pwm.ops = &lpg_pwm_ops; + + ret = pwmchip_add(&lpg->pwm); + if (ret) + dev_err(lpg->dev, "failed to add PWM chip: ret %d\n", ret); + + return ret; +} + +static int lpg_parse_channel(struct lpg *lpg, struct device_node *np, + struct lpg_channel **channel) +{ + struct lpg_channel *chan; + u32 dtest[2]; + u32 color = LED_COLOR_ID_GREEN; + u32 reg; + int ret; + + ret = of_property_read_u32(np, "reg", ®); + if (ret || !reg || reg > lpg->num_channels) { + dev_err(lpg->dev, "invalid reg of %pOFn\n", np); + return -EINVAL; + } + + chan = &lpg->channels[reg - 1]; + chan->in_use = true; + + ret = of_property_read_u32(np, "color", &color); + if (ret < 0 && ret != -EINVAL) + return ret; + + chan->color = color; + + ret = of_property_read_u32_array(np, "qcom,dtest", dtest, 2); + if (ret < 0 && ret != -EINVAL) { + dev_err(lpg->dev, "malformed qcom,dtest of %pOFn\n", np); + return ret; + } else if (!ret) { + chan->dtest_line = dtest[0]; + chan->dtest_value = dtest[1]; + } + + *channel = chan; + + return 0; +} + +static int lpg_add_led(struct lpg *lpg, struct device_node *np) +{ + struct led_classdev *cdev; + struct device_node *child; + struct mc_subled *info; + struct lpg_led *led; + const char *state; + int num_channels; + u32 color = 0; + int ret; + int i; + + ret = of_property_read_u32(np, "color", &color); + if (ret < 0 && ret != -EINVAL) + return ret; + + if (color == LED_COLOR_ID_MULTI) + num_channels = of_get_available_child_count(np); + else + num_channels = 1; + + led = devm_kzalloc(lpg->dev, struct_size(led, channels, num_channels), GFP_KERNEL); + if (!led) + return -ENOMEM; + + led->lpg = lpg; + led->num_channels = num_channels; + + if (color == LED_COLOR_ID_MULTI) { + info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + i = 0; + for_each_available_child_of_node(np, child) { + ret = lpg_parse_channel(lpg, child, &led->channels[i]); + if (ret < 0) + return ret; + + info[i].color_index = led->channels[i]->color; + info[i].intensity = LED_FULL; + i++; + } + + led->mcdev.subled_info = info; + led->mcdev.num_colors = num_channels; + + cdev = &led->mcdev.led_cdev; + cdev->brightness_set = lpg_brightness_mc_set; + cdev->blink_set = lpg_blink_mc_set; + + /* Register pattern accessors only if we have a LUT block */ + if (lpg->lut_base) { + cdev->pattern_set = lpg_pattern_mc_set; + cdev->pattern_clear = lpg_pattern_mc_clear; + } + } else { + ret = lpg_parse_channel(lpg, np, &led->channels[0]); + if (ret < 0) + return ret; + + cdev = &led->cdev; + cdev->brightness_set = lpg_brightness_single_set; + cdev->blink_set = lpg_blink_single_set; + + /* Register pattern accessors only if we have a LUT block */ + if (lpg->lut_base) { + cdev->pattern_set = lpg_pattern_single_set; + cdev->pattern_clear = lpg_pattern_single_clear; + } + } + + /* Use label else node name */ + cdev->name = of_get_property(np, "label", NULL) ? : np->name; + cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL); + cdev->max_brightness = 255; + + if (!of_property_read_string(np, "default-state", &state) && + !strcmp(state, "on")) + cdev->brightness = LED_FULL; + else + cdev->brightness = LED_OFF; + + cdev->brightness_set(cdev, cdev->brightness); + + if (color == LED_COLOR_ID_MULTI) + ret = devm_led_classdev_multicolor_register(lpg->dev, &led->mcdev); + else + ret = devm_led_classdev_register(lpg->dev, &led->cdev); + if (ret) + dev_err(lpg->dev, "unable to register %s\n", cdev->name); + + return ret; +} + +static int lpg_init_channels(struct lpg *lpg) +{ + const struct lpg_data *data = lpg->data; + int i; + + lpg->num_channels = data->num_channels; + lpg->channels = devm_kcalloc(lpg->dev, data->num_channels, + sizeof(struct lpg_channel), GFP_KERNEL); + if (!lpg->channels) + return -ENOMEM; + + for (i = 0; i < data->num_channels; i++) { + lpg->channels[i].lpg = lpg; + lpg->channels[i].base = data->channels[i].base; + lpg->channels[i].triled_mask = data->channels[i].triled_mask; + lpg->channels[i].lut_mask = BIT(i); + } + + return 0; +} + +static int lpg_init_triled(struct lpg *lpg) +{ + struct device_node *np = lpg->dev->of_node; + int ret; + + /* Skip initialization if we don't have a triled block */ + if (!lpg->data->triled_base) + return 0; + + lpg->triled_base = lpg->data->triled_base; + + ret = of_property_read_u32(np, "qcom,power-source", &lpg->triled_src); + if (ret || lpg->triled_src == 2 || lpg->triled_src > 3) { + dev_err(lpg->dev, "invalid power source\n"); + return -EINVAL; + } + + /* Disable automatic trickle charge LED */ + regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0); + + /* Configure power source */ + regmap_write(lpg->map, lpg->triled_base + TRI_LED_SRC_SEL, lpg->triled_src); + + /* Default all outputs to off */ + regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0); + + return 0; +} + +static int lpg_init_lut(struct lpg *lpg) +{ + const struct lpg_data *data = lpg->data; + size_t bitmap_size; + + if (!data->lut_base) + return 0; + + lpg->lut_base = data->lut_base; + lpg->lut_size = data->lut_size; + + bitmap_size = BITS_TO_LONGS(lpg->lut_size) * sizeof(unsigned long); + lpg->lut_bitmap = devm_kzalloc(lpg->dev, bitmap_size, GFP_KERNEL); + + bitmap_clear(lpg->lut_bitmap, 0, lpg->lut_size); + return lpg->lut_bitmap ? 0 : -ENOMEM; +} + +static int lpg_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct lpg *lpg; + int ret; + int i; + + lpg = devm_kzalloc(&pdev->dev, sizeof(*lpg), GFP_KERNEL); + if (!lpg) + return -ENOMEM; + + lpg->data = of_device_get_match_data(&pdev->dev); + if (!lpg->data) + return -EINVAL; + + lpg->dev = &pdev->dev; + + lpg->map = dev_get_regmap(pdev->dev.parent, NULL); + if (!lpg->map) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + ret = lpg_init_channels(lpg); + if (ret < 0) + return ret; + + ret = lpg_init_triled(lpg); + if (ret < 0) + return ret; + + ret = lpg_init_lut(lpg); + if (ret < 0) + return ret; + + for_each_available_child_of_node(pdev->dev.of_node, np) { + ret = lpg_add_led(lpg, np); + if (ret) + return ret; + } + + for (i = 0; i < lpg->num_channels; i++) + lpg_apply_dtest(&lpg->channels[i]); + + ret = lpg_add_pwm(lpg); + if (ret) + return ret; + + platform_set_drvdata(pdev, lpg); + + return 0; +} + +static int lpg_remove(struct platform_device *pdev) +{ + struct lpg *lpg = platform_get_drvdata(pdev); + + pwmchip_remove(&lpg->pwm); + + return 0; +} + +static const struct lpg_data pm8916_pwm_data = { + .pwm_9bit_mask = BIT(2), + + .num_channels = 1, + .channels = (struct lpg_channel_data[]) { + { .base = 0xbc00 }, + }, +}; + +static const struct lpg_data pm8941_lpg_data = { + .lut_base = 0xb000, + .lut_size = 64, + + .triled_base = 0xd000, + + .pwm_9bit_mask = 3 << 4, + + .num_channels = 8, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300 }, + { .base = 0xb400 }, + { .base = 0xb500, .triled_mask = BIT(5) }, + { .base = 0xb600, .triled_mask = BIT(6) }, + { .base = 0xb700, .triled_mask = BIT(7) }, + { .base = 0xb800 }, + }, +}; + +static const struct lpg_data pm8994_lpg_data = { + .lut_base = 0xb000, + .lut_size = 64, + + .pwm_9bit_mask = 3 << 4, + + .num_channels = 6, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300 }, + { .base = 0xb400 }, + { .base = 0xb500 }, + { .base = 0xb600 }, + }, +}; + +static const struct lpg_data pmi8994_lpg_data = { + .lut_base = 0xb000, + .lut_size = 24, + + .triled_base = 0xd000, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 4, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100, .triled_mask = BIT(5) }, + { .base = 0xb200, .triled_mask = BIT(6) }, + { .base = 0xb300, .triled_mask = BIT(7) }, + { .base = 0xb400 }, + }, +}; + +static const struct lpg_data pmi8998_lpg_data = { + .lut_base = 0xb000, + .lut_size = 49, + + .pwm_9bit_mask = BIT(4), + + .num_channels = 6, + .channels = (struct lpg_channel_data[]) { + { .base = 0xb100 }, + { .base = 0xb200 }, + { .base = 0xb300, .triled_mask = BIT(5) }, + { .base = 0xb400, .triled_mask = BIT(6) }, + { .base = 0xb500, .triled_mask = BIT(7) }, + { .base = 0xb600 }, + }, +}; + +static const struct of_device_id lpg_of_table[] = { + { .compatible = "qcom,pm8916-pwm", .data = &pm8916_pwm_data }, + { .compatible = "qcom,pm8941-lpg", .data = &pm8941_lpg_data }, + { .compatible = "qcom,pm8994-lpg", .data = &pm8994_lpg_data }, + { .compatible = "qcom,pmi8994-lpg", .data = &pmi8994_lpg_data }, + { .compatible = "qcom,pmi8998-lpg", .data = &pmi8998_lpg_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpg_of_table); + +static struct platform_driver lpg_driver = { + .probe = lpg_probe, + .remove = lpg_remove, + .driver = { + .name = "qcom-spmi-lpg", + .of_match_table = lpg_of_table, + }, +}; +module_platform_driver(lpg_driver); + +MODULE_DESCRIPTION("Qualcomm LPG LED driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Oct 21 20:12:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11849707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF08314B4 for ; Wed, 21 Oct 2020 20:12:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C76B524181 for ; Wed, 21 Oct 2020 20:12:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rpbvkLyJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505164AbgJUUMB (ORCPT ); Wed, 21 Oct 2020 16:12:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505149AbgJUULy (ORCPT ); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id t5sm838166otl.22.2020.10.21.13.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 13:11:51 -0700 (PDT) From: Bjorn Andersson To: Pavel Machek , Dan Murphy , Rob Herring , Andy Gross , Bjorn Andersson , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lee Jones , Martin Botka Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org Subject: [PATCH v6 3/4] arm64: dts: qcom: pm(i)8994: Add mpp and lpg blocks Date: Wed, 21 Oct 2020 13:12:23 -0700 Message-Id: <20201021201224.3430546-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201021201224.3430546-1-bjorn.andersson@linaro.org> References: <20201021201224.3430546-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pm8994 contains a 6 LPG channels and the pmi8994 contains 4 MPP channels and a 4 channel LPG, with TRILED and LUT blocks. Add nodes for these blocks. Signed-off-by: Bjorn Andersson --- Changes since v5: - None arch/arm64/boot/dts/qcom/pm8994.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/pmi8994.dtsi | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 7e4f777746cb..b5bef687aa3c 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -86,6 +86,15 @@ pmic@1 { #address-cells = <1>; #size-cells = <0>; + pm8994_lpg: lpg { + compatible = "qcom,pm8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + pm8994_spmi_regulators: regulators { compatible = "qcom,pm8994-regulators"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index e5ed28ab9b2d..23f41328d191 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -19,6 +19,17 @@ pmi8994_gpios: gpios@c000 { interrupt-controller; #interrupt-cells = <2>; }; + + pmi8994_mpps: mpps@a000 { + compatible = "qcom,pm8994-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + }; }; pmic@3 { @@ -27,6 +38,15 @@ pmic@3 { #address-cells = <1>; #size-cells = <0>; + pmi8994_lpg: lpg@b100 { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; #address-cells = <1>; From patchwork Wed Oct 21 20:12:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11849705 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 315F81580 for ; Wed, 21 Oct 2020 20:11:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 045DE24630 for ; Wed, 21 Oct 2020 20:11:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Bsil/4/V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505160AbgJUUL4 (ORCPT ); Wed, 21 Oct 2020 16:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505134AbgJUULz (ORCPT ); Wed, 21 Oct 2020 16:11:55 -0400 Received: from mail-oi1-x242.google.com (mail-oi1-x242.google.com [IPv6:2607:f8b0:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9BABC0613D4 for ; Wed, 21 Oct 2020 13:11:53 -0700 (PDT) Received: by mail-oi1-x242.google.com with SMTP id n3so3473616oie.1 for ; Wed, 21 Oct 2020 13:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h3IjEKBycl4AdV4pHmY8x7WaZ0Ptwe7SpKSP+5fA0v0=; b=Bsil/4/VIe8KiAFM+fsJ3dsLu5fJ+LYGHFp8iH99zcx6Djp2uzo6FD2YjXSd82lkVg piz/Xirt+WifCSz0l7gLClPZiP14tb0WYUyQ1zMTlVmshXF5Pz67/vDfyp2wt9XTPsFA Fki4xWfLpSGf3CdTu/ToVli9ItQoWdBLKslbw39xMVutqkMO5lA39tyHb0vI3OtID41X G7EuxKdKKEWeAa1c1hB4lNV0Et9TDTU7mqWIovKwHX1KCyWvWgOWqKJpPaMRWW8ursu2 CFBMyaLzPkkNQwauUzoy+G+anTLhUQY3fTNYAeSL6JKYR/OZo6RewIblcuW9ngtEzREg XCLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h3IjEKBycl4AdV4pHmY8x7WaZ0Ptwe7SpKSP+5fA0v0=; b=kFQXaaTBEKZM83DfTSX5lP5mgCEjUMJcnvcDp0q/cco9MdCsR5nkWMkeJfJeixUmd0 o5IaEI4QBLS4gaGZ75PgBaItDbrx718SLd87qUiAzCSP7LdcOLqJWrEi85MNYjSSTGdZ 2G0RAz0HcwgeILYeP27ODJYAT6SgyDp/RzA6yXNttkzQ714Rrl6aL41r3YDrwQrqq50r MwPZSHT22AtLDGVHtDNt/WLqWsGMn1wl+qq7UimNc3AA8XqbhLwJq94rDO2/Wx9MmqwD KvOdGYIruHq39FXNRItdWksOtkr7NALfKibzif1qQyJZ1lstozob9I7qkc67PkF1sgl2 DlAw== X-Gm-Message-State: AOAM533Uq9hHopE32/JvlsD18Fa7yMJKf1Q+EzvKtc4EvklteqNLBP6W s9JAWddmMJ1U+7TGNUPOoWd3Jw== X-Google-Smtp-Source: ABdhPJwpXwGpMMY0lOzWhIQyAznwBP9uD5c44odQWyNTc7tB26G8V2bFUSw/A6eCXg3EraLWJUhDoQ== X-Received: by 2002:aca:442:: with SMTP id 63mr3195841oie.111.1603311113085; Wed, 21 Oct 2020 13:11:53 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id t5sm838166otl.22.2020.10.21.13.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2020 13:11:52 -0700 (PDT) From: Bjorn Andersson To: Pavel Machek , Dan Murphy , Rob Herring , Andy Gross , Bjorn Andersson , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lee Jones , Martin Botka Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org Subject: [PATCH v6 4/4] arm64: dts: qcom: Add user LEDs on db820c Date: Wed, 21 Oct 2020 13:12:24 -0700 Message-Id: <20201021201224.3430546-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201021201224.3430546-1-bjorn.andersson@linaro.org> References: <20201021201224.3430546-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The db820c has 4 "user LEDs", all connected to the PMI8994. The first three are connected to the three current sinks provided by the TRILED and the fourth is connected to MPP2. By utilizing the DTEST bus the MPP is fed the control signal from the fourth LPG block, providing a consistent interface to the user. Signed-off-by: Bjorn Andersson --- Changes since v5: - None arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 49 ++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index defcbd15edf9..7e51677d256e 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -8,6 +8,7 @@ #include "pmi8994.dtsi" #include #include +#include #include #include #include @@ -682,6 +683,54 @@ pinconf { }; }; +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4 { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + label = "green:user1"; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + label = "green:user0"; + default-state = "on"; + }; + + led@3 { + reg = <3>; + label = "green:user2"; + }; + + led@4 { + reg = <4>; + label = "green:user3"; + + qcom,dtest = <4 1>; + }; +}; + &pmi8994_spmi_regulators { vdd_gfx: s2@1700 { reg = <0x1700 0x100>;