From patchwork Thu Oct 22 07:43:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E546014B7 for ; Thu, 22 Oct 2020 07:44:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71CA121707 for ; Thu, 22 Oct 2020 07:44:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tvOAhnqU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71CA121707 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVGl-0002SQ-An for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:44:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVG1-00013V-FP; Thu, 22 Oct 2020 03:43:34 -0400 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:44568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFn-0007cz-Fq; Thu, 22 Oct 2020 03:43:31 -0400 Received: by mail-lf1-x144.google.com with SMTP id b1so1009021lfp.11; Thu, 22 Oct 2020 00:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EMHtwtlOhgQ1h5Kmz8jinmABS0h3Twjiwzgmx6BiYTU=; b=tvOAhnqUEF1HR4dLtrw58AK6xtuIa2JtxZJ1MFWLmXr6bn5I2O02Dxl506H6tiQ59a gyFjDcOtUJmZYHOK9ZOTh9n1gRUBPZ5dUAXuZL93gCwbfGRlpvWl5eQAblWPAlfs9VgD mULMrldSLBAYC7PjF1YTBrxyK9DxXZaQRn3QPmk5NFnnVEbMddVd/Zy3tH9EpJXw2p3A QKL0gJJ2Gk8N5oXBLuc2tHz3eKyIH60wNEPIeE0tUjT5puQGRV709G+XeRpTvRLyEv1/ eWrHiXkVwAtI3R0zgJLOR1Lw7CwCt1WpBwWybXa171QHSVOzJd42+z8ZroBcf+iDMLSO b2Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EMHtwtlOhgQ1h5Kmz8jinmABS0h3Twjiwzgmx6BiYTU=; b=VGIdFaobhwf/OR3Vv3xXBWsQjxc0Qq4ExUjIekIMILKv/vF5BqzDV0pySengWyNzvJ MaKtEeKFUN275/hXObtO+HUxUbJ4QDT8FRtPLZ/lf1jR6S9lOpMFAfMo4JrLzkxgmBN+ RYH7K5frJMH9bPiXtMp1qj+/D1t9zhbJVPTk43VdG5kMRWD1oXGgueQlNQ05tavu99Vv zHzs6KzCID2VaK+CmGQGcBQwm8S0ii93I3piCpYimhX1TSKaTTPmxRUOzznDYc+3Q9T+ Qv5kDYCBtTdlBinn9cfyukW2V6bLJHeK+AlhbJpkUxHhCvUzGvgfRPRNrdeR4J2GGSFY Kcqw== X-Gm-Message-State: AOAM533ACh5nZ/deZ3LtdKgpUNIArdmyUJHcQK1fVoVbYGxrnZEmTcEK Cgk/uoT3eVj1TlT62OyGEBQqboVUVJbPc/Ie1Ok= X-Google-Smtp-Source: ABdhPJyd/QwastSqdAsDDFHUsfUCjskdU96trIYqGFLW2H70YzG7Ze6Bfysdz/jIgYSu9CflfxT1lw== X-Received: by 2002:a19:7e53:: with SMTP id z80mr376945lfc.72.1603352596199; Thu, 22 Oct 2020 00:43:16 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:15 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 1/6] [RISCV_PM] Add J-extension into RISC-V Date: Thu, 22 Oct 2020 10:43:04 +0300 Message-Id: <20201022074309.3210-2-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::144; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x144.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..4e305249b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de275782e6..eca611a367 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -277,6 +278,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_counters; bool ext_ifencei; From patchwork Thu Oct 22 07:43:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03B9914B7 for ; Thu, 22 Oct 2020 07:44:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E78221707 for ; Thu, 22 Oct 2020 07:44:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cCMbALbB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6E78221707 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVGm-0002Sx-C7 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:44:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVFw-00012n-U9; Thu, 22 Oct 2020 03:43:29 -0400 Received: from mail-lj1-x242.google.com ([2a00:1450:4864:20::242]:33787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFn-0007dD-H3; Thu, 22 Oct 2020 03:43:27 -0400 Received: by mail-lj1-x242.google.com with SMTP id c21so906243ljj.0; Thu, 22 Oct 2020 00:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NhA/Yx4IzGlO7kzPXnIit66vJX4zfC+2x0DyLT9E1sw=; b=cCMbALbBv3nbjdyPebvSOo/M3Kcy+76+B/culcERpzCOOnrmonm4VxrPHDff+bYJ7l iFONFB9AU/2veSE/eA513vfEJmIAsGjUM78JjkmOtVLeGXbm3mdWbndHVWnZr6+PxJQT XTSMuBd3Raz2tWdYZMUqGAEHOpAHCuu94PoaVxVSyImYA9hXKgdilT5NYENtRVSP2Xt6 lvwMOhzCv9xofsY+XcorBsa6MF5WYoRpzx1lT1iUtqGFCFsf2ln/VCI3m60INKg2VHp1 pCX1rSdkDA/tzh8PCtuAUhMlspY8rGGQ3SZmsdB33gpSsl779ttrooocQn+u7ToBf+Zq z6FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NhA/Yx4IzGlO7kzPXnIit66vJX4zfC+2x0DyLT9E1sw=; b=VBPzZybjp4rmL5bSGZeSmNDmp2JtM7S3Y7N2gXClxyhj1/1HoIH5caaJso2TB6NMOI EOWD6iRbC7XaRdoqJNtzMVRNe6Zdx5Gel9KQyJnH0My6sBi4+eZ/GZQ+6BTVCuffjRGx swkCqV8zEifUFipe+Z+ofHL1PcXtqmdJ8QIpep37+o779KLulnwuGY1uF5ahUY8IfxdA qubxwyEDBEM8MOxccUGoYDqk/k8XKqzt2cIszlxbPl9kkTah829kEGuKV7YReMK/Uc1A mQP4ZWeG/ftJdwdFEEah4qZA3icHLqKwlIdWxFBIgQRUUqOlMIVSsss5ENcUU4DPVDm8 jP+Q== X-Gm-Message-State: AOAM533PW0jYjr6kUtCpBKWqlcZ6jUYM5UjJ2Zup9d313fht3P+0+dYf Y39oVgYf9abgwTB+mBgMyAk= X-Google-Smtp-Source: ABdhPJwK+nt0hiLyRq9OpJTmPaVkl3e3KzG8+ovKqrV87WTpt40c2f9VAKfpWfSM/MO+a+Jf0nsuTg== X-Received: by 2002:a2e:2c18:: with SMTP id s24mr540654ljs.264.1603352597303; Thu, 22 Oct 2020 00:43:17 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:16 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Date: Thu, 22 Oct 2020 10:43:05 +0300 Message-Id: <20201022074309.3210-3-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::242; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x242.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 ++ target/riscv/cpu_bits.h | 66 ++++++++++ target/riscv/csr.c | 271 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 352 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e305249b3..db72f5cf59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_j) { + env->mmte |= PM_EXT_INITIAL; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eca611a367..c236f01fff 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -226,6 +226,18 @@ struct CPURISCVState { /* True if in debugger mode. */ bool debugger; + + /* + * CSRs for PM + * TODO: move these csr to appropriate groups + */ + target_ulong mmte; + target_ulong mpmmask; + target_ulong mpmbase; + target_ulong spmmask; + target_ulong spmbase; + target_ulong upmmask; + target_ulong upmbase; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..84c93c77ae 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -354,6 +354,21 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f +/* Custom user register */ +#define CSR_UMTE 0x8c0 +#define CSR_UPMMASK 0x8c1 +#define CSR_UPMBASE 0x8c2 + +/* Custom machine register */ +#define CSR_MMTE 0x7c0 +#define CSR_MPMMASK 0x7c1 +#define CSR_MPMBASE 0x7c2 + +/* Custom supervisor register */ +#define CSR_SMTE 0x9c0 +#define CSR_SPMMASK 0x9c1 +#define CSR_SPMBASE 0x9c2 + /* Legacy Machine Protection and Translation (priv v1.9.1) */ #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 @@ -604,4 +619,55 @@ #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) + +/* general mte CSR bits*/ +#define PM_ENABLE 0x00000001ULL +#define PM_CURRENT 0x00000002ULL +#define PM_XS_MASK 0x00000003ULL + +/* PM XS bits values */ +#define PM_EXT_DISABLE 0x00000000ULL +#define PM_EXT_INITIAL 0x00000001ULL +#define PM_EXT_CLEAN 0x00000002ULL +#define PM_EXT_DIRTY 0x00000003ULL + +/* offsets for every pair of control bits per each priv level */ +#define XS_OFFSET 0ULL +#define U_OFFSET 2ULL +#define S_OFFSET 4ULL +#define M_OFFSET 6ULL + +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) + +/* mmte CSR bits */ +#define MMTE_PM_XS_BITS PM_XS_BITS +#define MMTE_U_PM_ENABLE U_PM_ENABLE +#define MMTE_U_PM_CURRENT U_PM_CURRENT +#define MMTE_S_PM_ENABLE S_PM_ENABLE +#define MMTE_S_PM_CURRENT S_PM_CURRENT +#define MMTE_M_PM_ENABLE M_PM_ENABLE +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \ + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \ + MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS) + +/* smte CSR bits */ +#define SMTE_PM_XS_BITS PM_XS_BITS +#define SMTE_U_PM_ENABLE U_PM_ENABLE +#define SMTE_U_PM_CURRENT U_PM_CURRENT +#define SMTE_S_PM_ENABLE S_PM_ENABLE +#define SMTE_S_PM_CURRENT S_PM_CURRENT +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \ + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \ + SMTE_PM_XS_BITS) + +/* umte CSR bits */ +#define UMTE_U_PM_ENABLE U_PM_ENABLE +#define UMTE_U_PM_CURRENT U_PM_CURRENT +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT) + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..e4839c8fc9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -140,6 +140,11 @@ static int any(CPURISCVState *env, int csrno) return 0; } +static int umode(CPURISCVState *env, int csrno) +{ + return -!riscv_has_ext(env, RVU); +} + static int smode(CPURISCVState *env, int csrno) { return -!riscv_has_ext(env, RVS); @@ -1250,6 +1255,257 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* + * Functions to access Pointer Masking feature registers + * We have to check if current priv lvl could modify + * csr in given mode + */ +static int check_pm_current_disabled(CPURISCVState *env, int csrno) +{ + int csr_priv = get_field(csrno, 0xC00); + /* + * If priv lvls differ that means we're accessing csr from higher priv lvl, + * so allow the access + */ + if (env->priv != csr_priv) { + return 0; + } + int cur_bit_pos; + switch (env->priv) { + case PRV_M: + /* m-mode is always allowed to modify registers, so allow */ + return 0; + case PRV_S: + cur_bit_pos = S_PM_CURRENT; + break; + case PRV_U: + cur_bit_pos = U_PM_CURRENT; + break; + default: + g_assert_not_reached(); + } + int pm_current = get_field(env->mmte, cur_bit_pos); + /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */ + return !pm_current; +} + +static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } + *val = env->mmte & MMTE_MASK; + return 0; +} + +static int write_mmte(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + target_ulong wpri_val = val & MMTE_MASK; + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + env->mmte = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_smte(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } + *val = env->mmte & SMTE_MASK; + return 0; +} + +static int write_smte(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + target_ulong wpri_val = val & SMTE_MASK; + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + target_ulong new_val = val | (env->mmte & ~SMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_umte(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } + *val = env->mmte & UMTE_MASK; + return 0; +} + +static int write_umte(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + target_ulong wpri_val = val & UMTE_MASK; + assert(val == wpri_val); + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + target_ulong new_val = val | (env->mmte & ~UMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->mpmmask; + return 0; +} + +static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + env->mpmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->spmmask; + return 0; +} + +static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + env->spmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->upmmask; + return 0; +} + +static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + env->upmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->mpmbase; + return 0; +} + +static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + env->mpmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->spmbase; + return 0; +} + +static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + env->spmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + *val = env->upmbase; + return 0; +} + +static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val) +{ + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + if (check_pm_current_disabled(env, csrno)) { + return 0; + } + env->upmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} #endif /* @@ -1471,6 +1727,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, + /* User Pointer Masking */ + [CSR_UMTE] = { umode, read_umte, write_umte }, + [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask }, + [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase }, + + /* Machine Pointer Masking */ + [CSR_MMTE] = { any, read_mmte, write_mmte }, + [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask }, + [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase }, + + /* Supervisor Pointer Masking */ + [CSR_SMTE] = { smode, read_smte, write_smte }, + [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask }, + [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase }, + /* Performance Counters */ [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, From patchwork Thu Oct 22 07:43:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850449 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0F58157C for ; Thu, 22 Oct 2020 07:48:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45A9821D43 for ; Thu, 22 Oct 2020 07:48:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fbUlSsoN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45A9821D43 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:33808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVKu-0007Is-7j for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:48:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVG0-00013S-VM; Thu, 22 Oct 2020 03:43:34 -0400 Received: from mail-lf1-x143.google.com ([2a00:1450:4864:20::143]:44568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFp-0007dI-CT; Thu, 22 Oct 2020 03:43:30 -0400 Received: by mail-lf1-x143.google.com with SMTP id b1so1009123lfp.11; Thu, 22 Oct 2020 00:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGcClsENfMRlEEj1DdXzesuzsrG1w6qHhs9fkCduQVY=; b=fbUlSsoNarvg6cRPA/XasjZJdKwbAF8Uif/N50wZWi9TrLuCwdlXS0Cis0ycV6PHKo bJ8Fag//1YASkwSt4ikcUItrhgDd7UaJN4JGrnfCUXFNYRL2HfnicnDkWHrPLweyuDz/ F7ehlRny9CIbukczYpSa+jjSK3cyB2komcZReI6tSPbhBenGdlSE/D2vJrgLBGREYqKt WKO8a8GXq8t4NxpQ81+S0rpdx6sN/hWrKK814ECg/toohMEn0kczASovt52mBS0clF1g QraoG527c93icI9IX36rcROlgHkfDemL1cmv6d9yJcWWzaLaQo6CH2Mdp+B5iX9NV+9V ntxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGcClsENfMRlEEj1DdXzesuzsrG1w6qHhs9fkCduQVY=; b=GMQnI4I9wpyWVOLAz3Paj1hCrYaJZGw0MHlOMNX/0ZgKql59l/Q3iTkKZZKAlQ5Yfb +fuYcaC8Pr07f7TNOoNaKmINVHZojVPqJTddAlxpZIKUOdQZLWUy/mEfA9Hnaf+p8EA7 vao2J/6TTqUP4TnKnzmZUriB1+rC2fvqL6pCu9HtUaxf7vgG+ICHAOfh24gY2ETDUIfA MgReul7JLd4z0bmXRnATom1ijelGgTvlm6QiSSTodCHyPpQh0IAhAE7ZiPmRrETs8K4Z ++NaWpfQb5Ja/viApPcPZODM6OyNFh1dLFutR8Vi1RJQOKAB8J+c55fTRQh4vOytLMpV zCWA== X-Gm-Message-State: AOAM533pv5Pnf8TAsA+nUtGK2A17tf190VrGqk4gArcfHyVCAcKqmSnp jroYY5SnYpguQZ0rH6cUntQ= X-Google-Smtp-Source: ABdhPJyET/SiBiKPYXFwBOv5uwKOKQlweJRhx7u33e1gxtaLrJP6Dn8+0UygCCrcufHxJAA+b2FEQg== X-Received: by 2002:ac2:5dea:: with SMTP id z10mr452470lfq.468.1603352598322; Thu, 22 Oct 2020 00:43:18 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:17 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Date: Thu, 22 Oct 2020 10:43:06 +0300 Message-Id: <20201022074309.3210-4-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::143; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x143.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db72f5cf59..1c00d9ea26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVJ)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + switch (env->priv) { + case PRV_U: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", + env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", + env->upmmask); + break; + case PRV_S: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", + env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", + env->spmmask); + break; + case PRV_M: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", + env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", + env->mpmmask); + break; + default: + assert(0 && "Unreachable"); + } + } #endif for (i = 0; i < 32; i++) { From patchwork Thu Oct 22 07:43:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850431 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51D2216C0 for ; Thu, 22 Oct 2020 07:44:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6D4A223FB for ; Thu, 22 Oct 2020 07:44:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WLh8jfmZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6D4A223FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVGo-0002Zr-Qz for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:44:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVFv-00012i-Ck; Thu, 22 Oct 2020 03:43:27 -0400 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:36932) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFp-0007dy-CL; Thu, 22 Oct 2020 03:43:26 -0400 Received: by mail-lj1-x244.google.com with SMTP id i2so894072ljg.4; Thu, 22 Oct 2020 00:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lc9QIvOC4BQ5aEV3wggBnbdGYDm7vcPEJjFI1O17k4M=; b=WLh8jfmZOcS0TFpmvT7cYT5DH32sUASC7+EO74hJoty5cetTIAhhRhx9HB9wUbsbdo C7LjqGoNfa3ZDp1nU/akQtDIeKiIc9MmtDJsr+7fgbGx+DSwva+7SyE9FL73B4ocSx5M yNUtUyuhMMyY1+NX/26xmAALaFJ6l0/0PTpzU7p1d70j9VTJlQnhviRAL3p15oNQ8LVM PEXsXM1I/3pFPNDrzexZV7MLr4a/0Blizu2XzslYwO2eHGy4dGwMGSBT8jIijKEVgXZY /tdnap8S4kaQqpN1u+RO8dwoZbqOaI3jlFuiWptrSPYeEvy/S/zGQGJxT8YB0yycWNRM xxuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lc9QIvOC4BQ5aEV3wggBnbdGYDm7vcPEJjFI1O17k4M=; b=ZE9QZm+Pq9hopeDWuX9t3kc9QJdUU9Mk8PqpA2Zu5J9QmigLL16f3C53zZFUHqowNG Y5XlUT4BetVzihMBy55gPG3VkYDW6PQeCfSVNVKT+NGZBta3+LOrSJ01DHJP+qdPl8mp RsHhmvoywkeNI+MtQwdJzx9VKWGB8S6f2cuxiIrkIF1ZN9uvXvwy+GJeC6R1nJuFkLlg fBHXbCC4BEnIzkMQ5LJFNZ3Ln8CuPjdohk1X2RE7YQZOdEZXgfBcwHnBOJjAw2zCILyP wIPHBuRcMbD1AI0anahjFCBHHfQJluXv81oEgGSYjtc24WPeGKs0O5sTTLazY7sV+A3f gXkg== X-Gm-Message-State: AOAM530T5+NeREpC/puTRSsVWQkFDF1N8H4k/bK/iMerxJ4HdgEXgGyD zXOmQd9BRsoM4VPzSg8/l0E= X-Google-Smtp-Source: ABdhPJzTwqO6B1l8wvaB6SjeXtpKmOHKSXHj6IFfmlSQ5WgDm0P4NYDcyG8uxO96HVvTdta44MgL+g== X-Received: by 2002:a2e:94d0:: with SMTP id r16mr471785ljh.292.1603352599347; Thu, 22 Oct 2020 00:43:19 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:18 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Date: Thu, 22 Oct 2020 10:43:07 +0300 Message-Id: <20201022074309.3210-5-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::244; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x244.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, GAPPY_SUBJECT=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c | 14 ++++++++++++++ 5 files changed, 23 insertions(+) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index be8a9f06dd..5559e347ba 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l2 = gen_new_label(); gen_get_gpr(src1, a->rs1); + gen_pm_adjust_address(ctx, src1, src1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); gen_get_gpr(src2, a->rs2); @@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, gen_get_gpr(src1, a->rs1); gen_get_gpr(src2, a->rs2); + gen_pm_adjust_address(ctx, src1, src1); (*func)(src2, src1, src2, ctx->mem_idx, mop); gen_set_gpr(a->rd, src2); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 4f832637fa..935342f66d 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 3dfec8211d..04b3c3eb3d 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); @@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index d04ca0394c..bee7f6be46 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); gen_set_gpr(a->rd, t1); @@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) TCGv dat = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + gen_pm_adjust_address(ctx, t0, t0); gen_get_gpr(dat, a->rs2); tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..a7cbf909f3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +/* + * Temp stub: generates address adjustment for PointerMasking + */ +static void gen_pm_adjust_address(DisasContext *s, + TCGv_i64 dst, + TCGv_i64 src) +{ + tcg_gen_mov_i64(dst, src); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. @@ -380,6 +390,7 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; if (memop < 0) { @@ -400,6 +411,7 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, TCGv dat = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); gen_get_gpr(dat, rs2); int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; @@ -459,6 +471,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); switch (opc) { case OPC_RISC_FLW: @@ -498,6 +511,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + gen_pm_adjust_address(ctx, t0, t0); switch (opc) { case OPC_RISC_FSW: From patchwork Thu Oct 22 07:43:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7CB77157C for ; Thu, 22 Oct 2020 07:46:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09CCD21707 for ; Thu, 22 Oct 2020 07:46:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O150Mi3Z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09CCD21707 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVIV-0005Ap-Ud for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:46:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVFy-00013K-Ud; Thu, 22 Oct 2020 03:43:32 -0400 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:45206) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFr-0007eO-7K; Thu, 22 Oct 2020 03:43:30 -0400 Received: by mail-lf1-x144.google.com with SMTP id r127so1003423lff.12; Thu, 22 Oct 2020 00:43:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wX2ZkHWZTsLegDRadNX3/LscZ8sVu41yZQYaAwn+M+o=; b=O150Mi3Z+iFES1xFesMALZdlhDkbZuLlwEEkZRIbkCGDTMJUR8/WWE2fkkG7YellBO kr05sAGUnw2wZpd0OY/M3m+zzCiV6SxlV29IooT7YqCKB2VEI3QP7PZbznl7aqv0TX7m mMTKsWdH+gf0WM73vUrr2Z27aOr1R+WzRi59nuJBubvHhfcGYKJyR0YmiFjr/ovYUcHi snaDivmcDIgebjkF80ZDSMKUPOe3HdguxKbzb+CpyCp2aJGbl194+mlvr3XCOMwawXbL O6Hy2M0oPeAb4i9epUhLZcFIl06TTT4SwYqd1DVr5U+ASCIvsI3zpuYLDvdDqORKbkuC RTEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wX2ZkHWZTsLegDRadNX3/LscZ8sVu41yZQYaAwn+M+o=; b=LCU1awahURMmfZG6T+JMH0lXD/gzL7C1hHTrHGCzUr38ytGy94WkL/lCMseqiysKDy A6+raK8Ha/vrNcYHc+63IXFlYIdNSaXtPLO0ljd+1rIlPLfiMSQD6tFGW7DXkZHzrFSe sBO2FaE0d33rNE2B2qPGd5e/yJrTkPSz1kYtCV833XNB0FXYrcS0KkoFiLbtRTWFMDim H65MY4VGYRxtt6fyiaUv6BDzGU+4Myhk5jzGL3+tYKhcQomU3yZQRgH0lSZfhEJwPB46 Xuf8BLX/eyfYAFL9MK2i2Ioh7d+CP4CSMqt4cmmOldx8VzV8p/0oioCAnPoFUeZP5gjG ugvw== X-Gm-Message-State: AOAM532lAuDXbbJuMeDYp8uIYykBD20o5mgMrhNQ2TQuNnizO4yWAS1J 2J4WLxDYfi1wkJZhWX0B3is= X-Google-Smtp-Source: ABdhPJxP/5gvT5cC/9VLF8Raud+8sU8Xa+Bngo+1k+Z4ydhTm4V5AOcip3Uap2hwe43wtSv1pwF29Q== X-Received: by 2002:a19:c690:: with SMTP id w138mr374616lff.409.1603352600430; Thu, 22 Oct 2020 00:43:20 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:19 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Date: Thu, 22 Oct 2020 10:43:08 +0300 Message-Id: <20201022074309.3210-6-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::144; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x144.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/cpu.h | 19 +++++++++++++++++++ target/riscv/translate.c | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c236f01fff..13accaa232 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -386,6 +386,7 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) FIELD(TB_FLAGS, LMUL, 3, 2) FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) +FIELD(TB_FLAGS, PM_ENABLED, 9, 1) /* * A simplification for VLMAX @@ -432,6 +433,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, if (riscv_cpu_fp_enabled(env)) { flags |= env->mstatus & MSTATUS_FS; } + if (riscv_has_ext(env, RVJ)) { + int priv = cpu_mmu_index(env, false); + bool pm_enabled = false; + switch (priv) { + case PRV_U: + pm_enabled = env->mmte & U_PM_ENABLE; + break; + case PRV_S: + pm_enabled = env->mmte & S_PM_ENABLE; + break; + case PRV_M: + pm_enabled = env->mmte & M_PM_ENABLE; + break; + default: + g_assert_not_reached(); + } + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); + } #endif *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a7cbf909f3..b3e7b93bc9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* globals for PM CSRs */ +static TCGv pm_mask[4]; +static TCGv pm_base[4]; #include "exec/gen-icount.h" @@ -63,6 +66,10 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + /* PointerMasking extension */ + bool pm_enabled; + TCGv pm_mask; + TCGv pm_base; } DisasContext; #ifdef TARGET_RISCV64 @@ -102,13 +109,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) } /* - * Temp stub: generates address adjustment for PointerMasking + * Generates address adjustment for PointerMasking */ static void gen_pm_adjust_address(DisasContext *s, TCGv_i64 dst, TCGv_i64 src) { - tcg_gen_mov_i64(dst, src); + if (!s->pm_enabled) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else { + tcg_gen_andc_i64(dst, src, s->pm_mask); + tcg_gen_or_i64(dst, dst, s->pm_base); + } } /* @@ -826,6 +839,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + int priv = cpu_mmu_index(env, false); + ctx->pm_mask = pm_mask[priv]; + ctx->pm_base = pm_base[priv]; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -945,4 +962,17 @@ void riscv_translate_init(void) "load_res"); load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), "load_val"); + /* Assign PM CSRs to tcg globals */ + pm_mask[PRV_U] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); + pm_base[PRV_U] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); + pm_mask[PRV_S] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); + pm_base[PRV_S] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); + pm_mask[PRV_M] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); + pm_base[PRV_M] = + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); } From patchwork Thu Oct 22 07:43:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11850437 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E18F21580 for ; Thu, 22 Oct 2020 07:46:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CD3321707 for ; Thu, 22 Oct 2020 07:46:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PRVMlwH3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CD3321707 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVVIZ-0005Gv-Fi for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Oct 2020 03:46:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVVG6-00014r-3q; Thu, 22 Oct 2020 03:43:38 -0400 Received: from mail-lj1-x243.google.com ([2a00:1450:4864:20::243]:36932) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kVVFr-0007eb-8g; Thu, 22 Oct 2020 03:43:37 -0400 Received: by mail-lj1-x243.google.com with SMTP id i2so894145ljg.4; Thu, 22 Oct 2020 00:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O+goKHHTPNQf+byU52c8msGIZZ/A616sN7JzkzNgsEM=; b=PRVMlwH3p9cdDtK/AJjNTto6KpeLjgX0dzV39nTWtIGeQQBLVi65h5aun2g4RA8nhf lRW4AmyV1C2HDSn7t+oqfo0mVRpCfTUIfWseFi9YAsY9aZh2j2/RJ4XJWguOthgxw51r 9NL7u0VspkU+pxFuCq+gsvdM10aUiEvZSZe50ZIrCoHDCHNvC835qYXanB4fsVKo4t+b C0+zy9nlN/OVThqggR6JHQ+RuTIu8d26Myyrp6kBWxreHmMX10ep1jDtDzsI5XFJqQpl zrG5aPo5vFXepnMjYkl+6CmIK8Kev60HMUkjbkS5532VVW87B55OudRXcYyREzlr2GpE ePPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O+goKHHTPNQf+byU52c8msGIZZ/A616sN7JzkzNgsEM=; b=b6ILhd0Mmjraenu/mgas4+14kRAkDEsJXU2jx7Cs38vHah/Tz25MXvLkrF/FODErMd gkW4MXHOi1u3xhbPxdrwud8QXIJK07qp8OYmdCh1gXpsLqySiaIUCvXoKySOcjnvNDKo 6K8XtMvza6Ik+E7P3qwowHjBGNmBysTmg2560f8hvjhzS8M3jGGVnta2j60hJlgax/wC J8rMW9qxNrk0jib6Sdffrao3rsZsmeW4h5eEuFoEj0qO3Q5Bu9C9kfrmoekBAKYYwo2y l6NpZXD4KAw1eFSTFS1v8k4oYEmYGCImr84V6IAPYKSioAqyRYJRuffi//SrES3/yInw oJfw== X-Gm-Message-State: AOAM5323X6kv5CR5Gw7nxSSuAK0iV39IIV8Ir1DH2o3I744Ol2us5FQn psHD6CtUDtmq5HpG437e7EU= X-Google-Smtp-Source: ABdhPJxTOrqgaVLzeKl/VvMQW/Bc2T5j2fVDZFWAjonNuJ+3L1Yyj3kEKpNOjivNK47y6+8HDzHwbQ== X-Received: by 2002:a2e:9d3:: with SMTP id 202mr518428ljj.449.1603352601388; Thu, 22 Oct 2020 00:43:21 -0700 (PDT) Received: from neptune.lab ([46.39.229.104]) by smtp.googlemail.com with ESMTPSA id n19sm138887lfe.142.2020.10.22.00.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 00:43:20 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v5 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Date: Thu, 22 Oct 2020 10:43:09 +0300 Message-Id: <20201022074309.3210-7-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201022074309.3210-1-space.monkey.delivers@gmail.com> References: <20201022074309.3210-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::243; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1c00d9ea26..56633c14eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -465,6 +465,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.ext_j) { env->mmte |= PM_EXT_INITIAL; + target_misa |= RVJ; } if (cpu->cfg.ext_v) { target_misa |= RVV;