From patchwork Thu Oct 22 22:27:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11851979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F015C388F9 for ; Thu, 22 Oct 2020 22:25:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2054724631 for ; Thu, 22 Oct 2020 22:25:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2054724631 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30A7A6E416; Thu, 22 Oct 2020 22:25:51 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E56C6E409 for ; Thu, 22 Oct 2020 22:25:44 +0000 (UTC) IronPort-SDR: A745oDMFs/XWYebinqN6ivgE+8U7Cy+OhYgf0mfhCQxWg8X8sJhXebB6Sa632aUun9GqEsu8ZM 9aG4yM6PzBYA== X-IronPort-AV: E=McAfee;i="6000,8403,9782"; a="155386819" X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="155386819" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2020 15:25:42 -0700 IronPort-SDR: WbCbhPEZ+WLYZTB8XS1F69cx5kkQwtrudlApTFqBFY/vOVVRt2F+I0v6zpYQUdRyRBZe68FvAU 01+0IIajpvRw== X-IronPort-AV: E=Sophos;i="5.77,404,1596524400"; d="scan'208";a="534153962" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 22 Oct 2020 15:25:42 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Oct 2020 15:27:05 -0700 Message-Id: <20201022222709.29386-8-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201022222709.29386-1-manasi.d.navare@intel.com> References: <20201022222709.29386-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++++ drivers/gpu/drm/i915/display/intel_vrr.c | 38 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 3 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 09811be08cfe..391c51979334 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -49,6 +49,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vdsc.h" +#include "intel_vrr.h" struct ddi_buf_trans { u32 trans1; /* balance leg enable, de-emph level */ @@ -4046,6 +4047,10 @@ static void intel_enable_ddi(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, crtc_state); + /* Enable VRR if requested through CRTC property */ + if (crtc_state->vrr.enable) + intel_vrr_enable(encoder, crtc_state); + intel_enable_pipe(crtc_state); intel_crtc_vblank_on(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 56114f535f94..7f1353bac583 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -64,3 +64,41 @@ intel_vrr_compute_config(struct intel_dp *intel_dp, crtc_state->vrr.vtotalmax); } +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + u32 trans_vrr_ctl = 0, trans_vrr_vmax = 0, trans_vrr_vmin = 0, trans_vrr_flipline = 0, trans_push = 0; + u16 framestart_to_pipelinefull_linecnt = 0; + + framestart_to_pipelinefull_linecnt = + min_t(u16, 255, (crtc_state->vrr.vtotalmin - adjusted_mode->crtc_vdisplay)); + + trans_vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_IGN_MAX_SHIFT | + VRR_CTL_FLIP_LINE_EN | VRR_CTL_LINE_COUNT(framestart_to_pipelinefull_linecnt) | + VRR_CTL_SW_FULLLINE_COUNT; + + /* Programming adjustments for 0 based regs */ + trans_vrr_vmax = crtc_state->vrr.vtotalmax - 1; + trans_vrr_vmin = crtc_state->vrr.vtotalmin - 1; + trans_vrr_flipline = crtc_state->vrr.vtotalmin - 1; + + trans_push = TRANS_PUSH_EN; + + intel_de_write(dev_priv, TRANS_VRR_VMIN(pipe), trans_vrr_vmin); + intel_de_write(dev_priv, TRANS_VRR_VMAX(pipe), trans_vrr_vmax); + intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(pipe), trans_vrr_flipline); + intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push); + + drm_dbg(&dev_priv->drm, "Enabling VRR on pipe (%c)\n", pipe_name(pipe)); + drm_dbg(&dev_priv->drm, "VRR Parameters: Vblank - Min = %d, Max = %d Flipline Count = %d, CTL Reg = 0x%08x, TRANS PUSH reg = 0x%08x", + crtc_state->vrr.vtotalmin, crtc_state->vrr.vtotalmax, + crtc_state->vrr.vtotalmin, trans_vrr_ctl, + trans_push); +} + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 1e6fe8fe92ec..05d982d6fbae 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -17,5 +17,7 @@ struct intel_dp; bool intel_is_vrr_capable(struct drm_connector *connector); void intel_vrr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */