From patchwork Fri Oct 23 08:24:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852489 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B3FB92C for ; Fri, 23 Oct 2020 08:25:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4394A20EDD for ; Fri, 23 Oct 2020 08:25:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UCTeVW1D"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GxoWL/Kv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4394A20EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UQK+uJPGXPc5C7Ludd5Cin+TcdzGys257iD/bFwzkus=; b=UCTeVW1D584U9Rfk1inGrbSxB 1GiT8t7eXwPKGi5d3f2G+iUWSbnivGJMAXONrIK7IrK9cf25bUynfE6zzOHcitkdp0gUyD7emru3R vX2p6SnL8b1e4jXnUOcSwuqoAPhEKQNWcNnNaLrKViD4vgJ3+KYz+a3uh+5vbWiTqzd6xiiBbLZUt 8iXbKe9MPGNNWwKwMrpZ8hR6xZlzPJojPf1Yhu5fVpjLheHUoqsWRCxTEL3pio77u/p+xjj0Kb+Is EQ03hhTSQDFx7WyNgvclp3bRMAckr/WOV/bcNQqZ8oQUaL1KIGS9uEh4+mObq+cZ/+hyXjlemYf6L i6G31i7SQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsNy-0008BB-Tj; Fri, 23 Oct 2020 08:25:18 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsNv-00088K-Qr; Fri, 23 Oct 2020 08:25:17 +0000 X-UUID: f34a7a2f930548ae880044e46c58f6dd-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Pp2yMZzQPe4Sa/3E0kj2dbjDK6yen97nX3nJul0cmAY=; b=GxoWL/KvZuxkZHu9DO6H2Dw4lYVLhRvYuR2JpvXH93xlYhMl3585LSWYSelxY37VzBEZfWibH/yTnaPem59Hvqt0CLa4vsVL1hkqlDB0c3wJOJQhdKJelUUv/AG4shmTSW6d4YoT2TO89RHG9Dp3+ppeuxeo7sKLphEc9WPzVKg=; X-UUID: f34a7a2f930548ae880044e46c58f6dd-20201023 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 423551166; Fri, 23 Oct 2020 00:25:05 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 01:25:02 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:55 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:55 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , "Lorenzo Pieralisi" , Subject: [PATCH v1 1/6] cpufreq: mediatek-hw: Add support for CPUFREQ HW Date: Fri, 23 Oct 2020 16:24:48 +0800 Message-ID: <1603441493-18554-2-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_042516_147771_379D2C2D X-CRM114-Status: GOOD ( 28.76 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Add cpufreq HW support. Signed-off-by: Hector.Yuan --- drivers/cpufreq/Kconfig.arm | 12 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mediatek-cpufreq-hw.c | 276 +++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index cb72fb5..b9d17c5 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -123,6 +123,18 @@ config ARM_MEDIATEK_CPUFREQ help This adds the CPUFreq driver support for MediaTek SoCs. +config ARM_MEDIATEK_CPUFREQ_HW + tristate "MediaTek CPUFreq HW driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + default m + help + Support for the CPUFreq HW driver. + Some MediaTek chipsets have a HW engine to offload the steps + necessary for changing the frequency of the CPUs. Firmware loaded + in this engine exposes a programming interface to the OS. + The driver implements the cpufreq interface for this HW engine. + Say Y if you want to support CPUFreq HW. + config ARM_OMAP2PLUS_CPUFREQ bool "TI OMAP2+" depends on ARCH_OMAP2PLUS diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index f1b7e3d..ffc61cd 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o +obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ_HW) += mediatek-cpufreq-hw.o obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c new file mode 100644 index 0000000..74449da --- /dev/null +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LUT_MAX_ENTRIES 32U +#define LUT_FREQ GENMASK(11, 0) +#define LUT_ROW_SIZE 0x4 + +enum { + REG_LUT_TABLE, + REG_ENABLE, + REG_PERF_STATE, + + REG_ARRAY_SIZE, +}; + +struct cpufreq_mtk { + struct cpufreq_frequency_table *table; + void __iomem *reg_bases[REG_ARRAY_SIZE]; + cpumask_t related_cpus; +}; + +static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = { + [REG_LUT_TABLE] = 0x0, + [REG_ENABLE] = 0x84, + [REG_PERF_STATE] = 0x88, +}; + +static struct cpufreq_mtk *mtk_freq_domain_map[NR_CPUS]; + +static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + struct cpufreq_mtk *c = policy->driver_data; + + writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); + + return 0; +} + +static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) +{ + struct cpufreq_mtk *c; + unsigned int index; + + c = mtk_freq_domain_map[cpu]; + + index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); + index = min(index, LUT_MAX_ENTRIES - 1); + + return c->table[index].frequency; +} + +static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) +{ + struct cpufreq_mtk *c; + + c = mtk_freq_domain_map[policy->cpu]; + if (!c) { + pr_err("No scaling support for CPU%d\n", policy->cpu); + return -ENODEV; + } + + cpumask_copy(policy->cpus, &c->related_cpus); + + policy->freq_table = c->table; + policy->driver_data = c; + + /* HW should be in enabled state to proceed now */ + writel_relaxed(0x1, c->reg_bases[REG_ENABLE]); + + return 0; +} + +static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) +{ + struct cpufreq_mtk *c; + + c = mtk_freq_domain_map[policy->cpu]; + if (!c) { + pr_err("No scaling support for CPU%d\n", policy->cpu); + return -ENODEV; + } + + /* HW should be in paused state now */ + writel_relaxed(0x0, c->reg_bases[REG_ENABLE]); + + return 0; +} + +static struct cpufreq_driver cpufreq_mtk_hw_driver = { + .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | + CPUFREQ_HAVE_GOVERNOR_PER_POLICY, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = mtk_cpufreq_hw_target_index, + .get = mtk_cpufreq_hw_get, + .init = mtk_cpufreq_hw_cpu_init, + .exit = mtk_cpufreq_hw_cpu_exit, + .name = "mtk-cpufreq-hw", + .attr = cpufreq_generic_attr, +}; + +static int mtk_cpu_create_freq_table(struct platform_device *pdev, + struct cpufreq_mtk *c) +{ + struct device *dev = &pdev->dev; + void __iomem *base_table; + u32 data, i, freq, prev_freq = 0; + + c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1, + sizeof(*c->table), GFP_KERNEL); + if (!c->table) + return -ENOMEM; + + base_table = c->reg_bases[REG_LUT_TABLE]; + + for (i = 0; i < LUT_MAX_ENTRIES; i++) { + data = readl_relaxed(base_table + (i * LUT_ROW_SIZE)); + freq = FIELD_GET(LUT_FREQ, data) * 1000; + + if (freq == prev_freq) + break; + + c->table[i].frequency = freq; + + dev_dbg(dev, "index=%d freq=%d\n", + i, c->table[i].frequency); + + prev_freq = freq; + } + + c->table[i].frequency = CPUFREQ_TABLE_END; + + return 0; +} + +static int mtk_get_related_cpus(int index, struct cpufreq_mtk *c) +{ + struct device_node *cpu_np; + struct of_phandle_args args; + int cpu, ret; + + for_each_possible_cpu(cpu) { + cpu_np = of_cpu_device_node_get(cpu); + if (!cpu_np) + continue; + + ret = of_parse_phandle_with_args(cpu_np, "mtk-freq-domain", + "#freq-domain-cells", 0, + &args); + of_node_put(cpu_np); + if (ret < 0) + continue; + + if (index == args.args[0]) { + cpumask_set_cpu(cpu, &c->related_cpus); + mtk_freq_domain_map[cpu] = c; + } + } + + return 0; +} + +static int mtk_cpu_resources_init(struct platform_device *pdev, + unsigned int cpu, int index, + const u16 *offsets) +{ + struct cpufreq_mtk *c; + struct device *dev = &pdev->dev; + int ret, i; + void __iomem *base; + + if (mtk_freq_domain_map[cpu]) + return 0; + + c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); + if (!c) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, index); + if (IS_ERR(base)) + return PTR_ERR(base); + + for (i = REG_LUT_TABLE; i < REG_ARRAY_SIZE; i++) + c->reg_bases[i] = base + offsets[i]; + + ret = mtk_get_related_cpus(index, c); + if (ret) { + dev_err(dev, "Domain-%d failed to get related CPUs\n", index); + return ret; + } + + ret = mtk_cpu_create_freq_table(pdev, c); + if (ret) { + dev_err(dev, "Domain-%d failed to create freq table\n", index); + return ret; + } + + return 0; +} + +static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev) +{ + struct device_node *cpu_np; + struct of_phandle_args args; + const u16 *offsets; + unsigned int cpu; + int ret; + + offsets = of_device_get_match_data(&pdev->dev); + if (!offsets) + return -EINVAL; + + for_each_possible_cpu(cpu) { + cpu_np = of_cpu_device_node_get(cpu); + if (!cpu_np) { + dev_err(&pdev->dev, "Failed to get cpu %d device\n", + cpu); + return -ENODEV; + } + + ret = of_parse_phandle_with_args(cpu_np, "mtk-freq-domain", + "#freq-domain-cells", 0, + &args); + if (ret < 0) + return ret; + + /* Get the bases of cpufreq for domains */ + ret = mtk_cpu_resources_init(pdev, cpu, args.args[0], offsets); + if (ret) { + dev_err(&pdev->dev, "CPUFreq resource init failed\n"); + return ret; + } + } + + ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver); + if (ret) { + dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); + return ret; + } + + return 0; +} + +static int mtk_cpufreq_hw_driver_remove(struct platform_device *pdev) +{ + return cpufreq_unregister_driver(&cpufreq_mtk_hw_driver); +} + +static const struct of_device_id mtk_cpufreq_hw_match[] = { + { .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets }, + {} +}; + +static struct platform_driver mtk_cpufreq_hw_driver = { + .probe = mtk_cpufreq_hw_driver_probe, + .remove = mtk_cpufreq_hw_driver_remove, + .driver = { + .name = "mtk-cpufreq-hw", + .of_match_table = mtk_cpufreq_hw_match, + }, +}; +module_platform_driver(mtk_cpufreq_hw_driver); + +MODULE_DESCRIPTION("Mediatek cpufreq-hw driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Oct 23 08:24:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 806CE1744 for ; Fri, 23 Oct 2020 08:35:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1831C21527 for ; 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Fri, 23 Oct 2020 16:24:55 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , "Viresh Kumar" , Maxime Ripard , "Santosh Shilimkar" , Amit Kucheria , Stephen Boyd , Ulf Hansson , "Dave Gerlach" , Florian Fainelli , "Robin Murphy" , Lorenzo Pieralisi , Subject: [PATCH v1 2/6] dt-bindings: arm: cpus: Document 'mtk, freq-domain' property Date: Fri, 23 Oct 2020 16:24:49 +0800 Message-ID: <1603441493-18554-3-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 53C7D773113909F92F9C837D2A74572C57D32B39C264274820D612D1E8E54F962000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_043507_527654_8AB634DA X-CRM114-Status: GOOD ( 11.06 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Add devicetree documentation for 'mtk,freq-domain' property specific to Mediatek CPUs. This property is used to reference the CPUFREQ node along with the domain id. Signed-off-by: Hector.Yuan --- Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 1222bf1..06a6f5b 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -255,6 +255,12 @@ properties: where voltage is in V, frequency is in MHz. + mtk-freq-domain: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + CPUs supporting freq-domain must set their "mtk-freq-domain" property + with phandle to a cpufreq_hw node followed by the domain id. + power-domains: $ref: '/schemas/types.yaml#/definitions/phandle-array' description: From patchwork Fri Oct 23 08:24:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852491 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CCBD6A2 for ; Fri, 23 Oct 2020 08:25:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03A6E20EDD for ; Fri, 23 Oct 2020 08:25:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="znFr9CIA"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Sw4Tz+3q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03A6E20EDD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DJahhPCiaxd6by67VgLvrCoidriPrSi5B3fMNjb/Qdw=; b=znFr9CIA6AAN4me1K/HgkwuKz p3HbnZIyD86lfb1N5i8QUK45RePA6a6DIApTJ0n/rI/fBr3eY1AZzUydZdj5EzRckth6d31ChjPya LyekOWnKWctmAdjV+6piTYmJx864Io2O43u3hwk3RHBrtq9SsKHk6Nv6g/cu7N3+Z7PPmq5v/wUvm aTtbOjGXouF5guy0k2hqVNOghIuYrIEbhaWwC59WJxk0EhBob4dV6QxL5IIsrQ0QMybu6ikmjBeDH YdxK+NymJOB1E5xxvW8T+F453Pnpa8mXZbud2J3Ox+YjDU5zCcXH9cY6TIhG7rhUMg7O7AMlXWRDs wRbGcjnzA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsO3-0008D6-T6; Fri, 23 Oct 2020 08:25:23 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsNx-00088G-Gp; Fri, 23 Oct 2020 08:25:18 +0000 X-UUID: 218c0534b1844cd8ba93062bd907d1bf-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0VcRiI/47uBH8qw621lJkqfCixACdBgrTLwaebngM9Y=; b=Sw4Tz+3qp6ESMw01rHba68g2NQX2Pc7ZtL6OgGqxTMcUwNCynSwbb6S3dLcb+5NUigSRegLl86xzk0c0d+RuCazda1WPoAvETCgV08n/AYk9x7M967mYnZKbJhSakO2aZ82KCtvGaL4ckxkHsoW541h9fLos4BCAQgYP0JFQL7s=; X-UUID: 218c0534b1844cd8ba93062bd907d1bf-20201023 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1646278130; Fri, 23 Oct 2020 00:25:05 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 01:25:03 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , "Lorenzo Pieralisi" , Subject: [PATCH v1 3/6] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Date: Fri, 23 Oct 2020 16:24:50 +0800 Message-ID: <1603441493-18554-4-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_042517_762601_39ECAFED X-CRM114-Status: GOOD ( 14.55 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..a99f44f --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + +required: + - compatible + - reg + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + }; + }; + + + + From patchwork Fri Oct 23 08:24:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6957261C for ; Fri, 23 Oct 2020 08:35:14 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7D5A21527 for ; Fri, 23 Oct 2020 08:35:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OEHbLjpS"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ZxR2oj8z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7D5A21527 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eG6fXK/h76yXSYtzWwt1eudhoJDDOAY+BJSHM53Rwm0=; b=OEHbLjpS8xcXTBODsQcqV2Hfe eg7AntP9zW3aqzutcTNobLmVSCPValyfI9UHP9wk5/xLa1/shoy8IPmSg7e1MvMOjOdfxSS8Y6+Gl PqWVFsKbvyEXeDhlRpTya/QWh4oSkZU0u9Vsq+B/ESjqb8Fdxh48k/8JtlEYQYTpdrgrN5tIxTxTt eRRv/KTWEOvUn1Fe7TCsfPgcxWEkmXB8MEaMvYwvWD21Ro9V0zSmIGKTq0R+rvvTGJGISTN5aeHvQ WAdsNIKrN3ody5EOUXtqxJTReQjyK8mCxGDwEvmeNnK7zrKBsDlA9h6Uhp10qsX+A5PmeZ35A3gB3 QENkywJkg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsXX-0001lj-S8; Fri, 23 Oct 2020 08:35:11 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVsXR-0001if-A4; Fri, 23 Oct 2020 08:35:06 +0000 X-UUID: c5731e94f0574299a646e78b04578e24-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=rCMbXAuODNB8y7MkCaQc2mt7ayxf9TpGQeinPyFrbEU=; b=ZxR2oj8zOX5nEMZ/vlqBLfka6izTXJCF/+gZ1n5VVRsvC7mkTUv+sPSftB5H3ByyVildlxl5/PnQAt/Bjyd97ojh6Tjxh57AwIiz7BqHC6xBBGP/APpMXUImeJDud7bTn/40002WsK0YUnVRJz+1U5duTHXuLv2GaGaqI67KoJk=; X-UUID: c5731e94f0574299a646e78b04578e24-20201023 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1082972577; Fri, 23 Oct 2020 00:35:02 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 01:25:00 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , "Viresh Kumar" , Maxime Ripard , "Santosh Shilimkar" , Amit Kucheria , Stephen Boyd , Ulf Hansson , "Dave Gerlach" , Florian Fainelli , "Robin Murphy" , Lorenzo Pieralisi , Subject: [PATCH v1 4/6] cpufreq: mediatek-hw: register EM power table Date: Fri, 23 Oct 2020 16:24:51 +0800 Message-ID: <1603441493-18554-5-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 1492DA2F4D89FE5D46D7253A3B77EFCEF5EC965C4A22111D57C163518DC29DF22000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_043505_543331_E0FC3602 X-CRM114-Status: GOOD ( 19.86 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Register energy model table for EAS and thermal cooling device usage Signed-off-by: Hector.Yuan --- drivers/cpufreq/mediatek-cpufreq-hw.c | 58 ++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c index 74449da..241d93f 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -17,9 +18,10 @@ #define LUT_ROW_SIZE 0x4 enum { - REG_LUT_TABLE, - REG_ENABLE, - REG_PERF_STATE, + REG_FREQ_LUT_TABLE, + REG_FREQ_ENABLE, + REG_FREQ_PERF_STATE, + REG_EM_POWER_TBL, REG_ARRAY_SIZE, }; @@ -27,23 +29,44 @@ enum { struct cpufreq_mtk { struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; + int nr_opp; cpumask_t related_cpus; }; static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = { - [REG_LUT_TABLE] = 0x0, - [REG_ENABLE] = 0x84, - [REG_PERF_STATE] = 0x88, + [REG_FREQ_LUT_TABLE] = 0x0, + [REG_FREQ_ENABLE] = 0x84, + [REG_FREQ_PERF_STATE] = 0x88, + [REG_EM_POWER_TBL] = 0x3D0, }; static struct cpufreq_mtk *mtk_freq_domain_map[NR_CPUS]; +static int mtk_cpufreq_get_cpu_power(unsigned long *mW, + unsigned long *KHz, struct device *cpu_dev) +{ + struct cpufreq_mtk *c = mtk_freq_domain_map[cpu_dev->id]; + int i; + + for (i = 0; i < c->nr_opp; i++) { + if (c->table[i].frequency < *KHz) + break; + } + i--; + + *KHz = c->table[i].frequency; + *mW = readl_relaxed(c->reg_bases[REG_EM_POWER_TBL] + + i * LUT_ROW_SIZE) / 1000; + + return 0; +} + static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { struct cpufreq_mtk *c = policy->driver_data; - writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); + writel_relaxed(index, c->reg_bases[REG_FREQ_PERF_STATE]); return 0; } @@ -55,7 +78,7 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) c = mtk_freq_domain_map[cpu]; - index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); + index = readl_relaxed(c->reg_bases[REG_FREQ_PERF_STATE]); index = min(index, LUT_MAX_ENTRIES - 1); return c->table[index].frequency; @@ -64,6 +87,14 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct cpufreq_mtk *c; + struct device *cpu_dev; + struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power); + + cpu_dev = get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("failed to get cpu%d device\n", policy->cpu); + return -ENODEV; + } c = mtk_freq_domain_map[policy->cpu]; if (!c) { @@ -77,7 +108,9 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) policy->driver_data = c; /* HW should be in enabled state to proceed now */ - writel_relaxed(0x1, c->reg_bases[REG_ENABLE]); + writel_relaxed(0x1, c->reg_bases[REG_FREQ_ENABLE]); + + em_dev_register_perf_domain(cpu_dev, c->nr_opp, &em_cb, policy->cpus); return 0; } @@ -93,7 +126,7 @@ static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) } /* HW should be in paused state now */ - writel_relaxed(0x0, c->reg_bases[REG_ENABLE]); + writel_relaxed(0x0, c->reg_bases[REG_FREQ_ENABLE]); return 0; } @@ -122,7 +155,7 @@ static int mtk_cpu_create_freq_table(struct platform_device *pdev, if (!c->table) return -ENOMEM; - base_table = c->reg_bases[REG_LUT_TABLE]; + base_table = c->reg_bases[REG_FREQ_LUT_TABLE]; for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base_table + (i * LUT_ROW_SIZE)); @@ -140,6 +173,7 @@ static int mtk_cpu_create_freq_table(struct platform_device *pdev, } c->table[i].frequency = CPUFREQ_TABLE_END; + c->nr_opp = i; return 0; } @@ -191,7 +225,7 @@ static int mtk_cpu_resources_init(struct platform_device *pdev, if (IS_ERR(base)) return PTR_ERR(base); - for (i = REG_LUT_TABLE; i < REG_ARRAY_SIZE; i++) + for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) c->reg_bases[i] = base + offsets[i]; ret = mtk_get_related_cpus(index, c); From patchwork Fri Oct 23 08:24:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852519 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEBAA61C for ; Fri, 23 Oct 2020 08:35:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8A8392168B for ; Fri, 23 Oct 2020 08:35:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="v8E6Rfo/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="cXdsTago" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8A8392168B Authentication-Results: mail.kernel.org; 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Fri, 23 Oct 2020 00:35:03 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 01:25:00 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , "Viresh Kumar" , Maxime Ripard , "Santosh Shilimkar" , Amit Kucheria , Stephen Boyd , Ulf Hansson , "Dave Gerlach" , Florian Fainelli , "Robin Murphy" , Lorenzo Pieralisi , Subject: [PATCH v1 5/6] cpufreq: mediatek-hw: Add SVS CPU initialization Date: Fri, 23 Oct 2020 16:24:52 +0800 Message-ID: <1603441493-18554-6-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_043507_887406_0F58A5F3 X-CRM114-Status: GOOD ( 17.59 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Use pm_qos to block cpu-idle state for SVS initializing. CPUs must be in power on state when doing SVS. Add polling ack while coufreq hw is ready.(SVS init done) Signed-off-by: Hector.Yuan --- drivers/cpufreq/mediatek-cpufreq-hw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c index 241d93f..15fba20 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -7,20 +7,27 @@ #include #include #include +#include #include #include #include #include +#include #include #define LUT_MAX_ENTRIES 32U #define LUT_FREQ GENMASK(11, 0) #define LUT_ROW_SIZE 0x4 +#define CPUFREQ_HW_STATUS BIT(0) +#define SVS_HW_STATUS BIT(1) +#define POLL_USEC 1000 +#define TIMEOUT_USEC 300000 enum { REG_FREQ_LUT_TABLE, REG_FREQ_ENABLE, REG_FREQ_PERF_STATE, + REG_FREQ_HW_STATE, REG_EM_POWER_TBL, REG_ARRAY_SIZE, @@ -37,6 +44,7 @@ struct cpufreq_mtk { [REG_FREQ_LUT_TABLE] = 0x0, [REG_FREQ_ENABLE] = 0x84, [REG_FREQ_PERF_STATE] = 0x88, + [REG_FREQ_HW_STATE] = 0x8c, [REG_EM_POWER_TBL] = 0x3D0, }; @@ -89,6 +97,12 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct cpufreq_mtk *c; struct device *cpu_dev; struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power); + struct pm_qos_request *qos_request; + int sig, pwr_hw = CPUFREQ_HW_STATUS | SVS_HW_STATUS; + + qos_request = kzalloc(sizeof(*qos_request), GFP_KERNEL); + if (!qos_request) + return -ENOMEM; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -107,11 +121,29 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) policy->freq_table = c->table; policy->driver_data = c; + /* Let CPUs leave idle-off state for SVS CPU initializing */ + cpu_latency_qos_add_request(qos_request, 0); + /* HW should be in enabled state to proceed now */ writel_relaxed(0x1, c->reg_bases[REG_FREQ_ENABLE]); + if (readl_poll_timeout(c->reg_bases[REG_FREQ_HW_STATE], sig, + (sig & pwr_hw) == pwr_hw, POLL_USEC, + TIMEOUT_USEC)) { + if (!(sig & CPUFREQ_HW_STATUS)) { + pr_info("cpufreq hardware of CPU%d is not enabled\n", + policy->cpu); + return -ENODEV; + } + + pr_info("SVS of CPU%d is not enabled\n", policy->cpu); + } + em_dev_register_perf_domain(cpu_dev, c->nr_opp, &em_cb, policy->cpus); + cpu_latency_qos_remove_request(qos_request); + kfree(qos_request); + return 0; } From patchwork Fri Oct 23 08:24:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852515 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 253C161C for ; Fri, 23 Oct 2020 08:35:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D271421527 for ; Fri, 23 Oct 2020 08:35:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="S/hlw6BM"; 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Fri, 23 Oct 2020 00:35:02 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 01:25:00 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , "Rob Herring" , "Rafael J. Wysocki" , "Viresh Kumar" , Maxime Ripard , "Santosh Shilimkar" , Amit Kucheria , Stephen Boyd , Ulf Hansson , "Dave Gerlach" , Florian Fainelli , "Robin Murphy" , Lorenzo Pieralisi , Subject: [PATCH v1 6/6] cpufreq: mediatek-hw: Add cooling dev flag Date: Fri, 23 Oct 2020 16:24:53 +0800 Message-ID: <1603441493-18554-7-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_043506_598551_9A5BF5ED X-CRM114-Status: GOOD ( 12.96 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hector.yuan@mediatek.com, linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "Hector.Yuan" Add cooling device flag for thermal throttle Signed-off-by: Hector.Yuan --- drivers/cpufreq/mediatek-cpufreq-hw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c index 15fba20..665f220f 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -165,7 +165,8 @@ static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) static struct cpufreq_driver cpufreq_mtk_hw_driver = { .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | - CPUFREQ_HAVE_GOVERNOR_PER_POLICY, + CPUFREQ_HAVE_GOVERNOR_PER_POLICY | + CPUFREQ_IS_COOLING_DEV, .verify = cpufreq_generic_frequency_table_verify, .target_index = mtk_cpufreq_hw_target_index, .get = mtk_cpufreq_hw_get,