From patchwork Fri Oct 23 10:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 11852691 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BAE98157C for ; Fri, 23 Oct 2020 10:18:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D65324631 for ; Fri, 23 Oct 2020 10:18:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nt9n7q1z"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="FXVNjYYN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D65324631 Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVu9N-0002YY-EF; Fri, 23 Oct 2020 10:18:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVu9K-0002XU-R9 for linux-riscv@lists.infradead.org; Fri, 23 Oct 2020 10:18:19 +0000 Received: from localhost.localdomain (unknown [42.120.72.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 708DE20936; Fri, 23 Oct 2020 10:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603448297; bh=BV1tH2U1Lsosw+Ugkhs7glTIjtqVDoAJop9TuiKHT44=; h=From:To:Cc:Subject:Date:From; b=FXVNjYYNeEGZSvIhl4SuHitDKUsn6hlGW8Wg42BMzw7N0bBGFCQQcXhfA83VUXfh9 PWbmy5NXe2PNDWiHSzBy2/Ktf60A1UV7UDxoKHO6LjuY2r1O41pscRE2LB20gp4Wkb MSAAeYE9mUg2sG/WR0ot+g2CIOxzKRiblzgHdqDM= From: guoren@kernel.org To: palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, greentime.hu@sifive.com, zong.li@sifive.com, atish.patra@wdc.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, wesley@sifive.com, yash.shah@sifive.com, hch@lst.de Subject: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base Date: Fri, 23 Oct 2020 10:17:23 +0000 Message-Id: <1603448245-79429-1-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_061819_022959_1302A770 X-CRM114-Status: GOOD ( 11.92 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, Guo Ren , guoren@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren ENABLE and CONTEXT registers contain M & S status for per-hart, so ref to the specification the correct definition is double to the current value. The value of hart_base and enable_base should be calculated by real physical hartid not software id. Sometimes the CPU node's from dts is not equal to the sequence index. Signed-off-by: Guo Ren --- drivers/irqchip/irq-sifive-plic.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index eaa3e9f..2e56576 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -44,16 +44,16 @@ * Each hart context has a vector of interrupt enable bits associated with it. * There's one bit for each interrupt source. */ -#define ENABLE_BASE 0x2000 -#define ENABLE_PER_HART 0x80 +#define ENABLE_BASE 0x2080 +#define ENABLE_PER_HART 0x100 /* * Each hart context has a set of control registers associated with it. Right * now there's only two: a source priority threshold over which the hart will * take an interrupt, and a register to claim interrupts. */ -#define CONTEXT_BASE 0x200000 -#define CONTEXT_PER_HART 0x1000 +#define CONTEXT_BASE 0x201000 +#define CONTEXT_PER_HART 0x2000 #define CONTEXT_THRESHOLD 0x00 #define CONTEXT_CLAIM 0x04 @@ -358,10 +358,10 @@ static int __init plic_init(struct device_node *node, cpumask_set_cpu(cpu, &priv->lmask); handler->present = true; handler->hart_base = - priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + priv->regs + CONTEXT_BASE + hartid * CONTEXT_PER_HART; raw_spin_lock_init(&handler->enable_lock); handler->enable_base = - priv->regs + ENABLE_BASE + i * ENABLE_PER_HART; + priv->regs + ENABLE_BASE + hartid * ENABLE_PER_HART; handler->priv = priv; done: for (hwirq = 1; hwirq <= nr_irqs; hwirq++) From patchwork Fri Oct 23 10:17:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 11852695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17BBF14B4 for ; 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Fri, 23 Oct 2020 10:18:29 +0000 Received: from localhost.localdomain (unknown [42.120.72.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5255E20936; Fri, 23 Oct 2020 10:18:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603448308; bh=Q2r2MpV4mhDq9ZPXIsBSWpTyiKSzFfZDPrP/d+7Waxw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o32LBurpluUVsOnJUTvVZM9MNs2/Yn9MJ9dd9LoErCOY4LYhqGMrav90SdRA1ftoo 3hvBWuzZ7SC0FiGceMW1gP/J/A6nPIV9ajR5ywAJf/rS/VH+j/caR0kVJ4M2lEBW3g ocpv9JC6gAt7ChMeauwUpsf81qXeKTp53BrBYpOw= From: guoren@kernel.org To: palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, greentime.hu@sifive.com, zong.li@sifive.com, atish.patra@wdc.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, wesley@sifive.com, yash.shah@sifive.com, hch@lst.de Subject: [PATCH 2/3] irqchip/irq-sifive-plic: Fixup couldn't broadcast to multi CPUs Date: Fri, 23 Oct 2020 10:17:24 +0000 Message-Id: <1603448245-79429-2-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603448245-79429-1-git-send-email-guoren@kernel.org> References: <1603448245-79429-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_061829_021637_5195CE58 X-CRM114-Status: GOOD ( 11.53 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, Guo Ren , guoren@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren If "echo 3 > /proc/irq/1/smp_affinity", we want irq 1 could be broadcast to CPU0 & CPU1 and one of them would pick up the irq handler. But current implementation couldn't let multi CPUs process the same IRQ concurrent. Signed-off-by: Guo Ren --- drivers/irqchip/irq-sifive-plic.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 2e56576..0003322 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -114,15 +114,12 @@ static inline void plic_irq_toggle(const struct cpumask *mask, static void plic_irq_unmask(struct irq_data *d) { struct cpumask amask; - unsigned int cpu; struct plic_priv *priv = irq_get_chip_data(d->irq); cpumask_and(&amask, &priv->lmask, cpu_online_mask); - cpu = cpumask_any_and(irq_data_get_affinity_mask(d), - &amask); - if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) - return; - plic_irq_toggle(cpumask_of(cpu), d, 1); + cpumask_and(&amask, &amask, irq_data_get_affinity_mask(d)); + + plic_irq_toggle(&amask, d, 1); } static void plic_irq_mask(struct irq_data *d) @@ -136,24 +133,16 @@ static void plic_irq_mask(struct irq_data *d) static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { - unsigned int cpu; struct cpumask amask; struct plic_priv *priv = irq_get_chip_data(d->irq); cpumask_and(&amask, &priv->lmask, mask_val); + cpumask_and(&amask, &amask, cpu_online_mask); - if (force) - cpu = cpumask_first(&amask); - else - cpu = cpumask_any_and(&amask, cpu_online_mask); - - if (cpu >= nr_cpu_ids) - return -EINVAL; + irq_data_update_effective_affinity(d, &amask); plic_irq_toggle(&priv->lmask, d, 0); - plic_irq_toggle(cpumask_of(cpu), d, 1); - - irq_data_update_effective_affinity(d, cpumask_of(cpu)); + plic_irq_toggle(&amask, d, 1); return IRQ_SET_MASK_OK_DONE; } From patchwork Fri Oct 23 10:17:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 11852699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 39B1F14B4 for ; Fri, 23 Oct 2020 10:18:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8ADD20936 for ; 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Fri, 23 Oct 2020 10:18:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603448314; bh=VQkOQqXVAMZZl0wG36+SPXHmfOpuP3DhOAi57iQd4xo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZtVp2hNnwKo2BHrStyM/agggm9GlwzSD0M0qp+eKjILGY/n6PR4CNYDEygQ2rcHL+ CtTu9EEFV7ziMODxvLTFw/3dG0Fs2WI3lHtpm8pc5OKbhvbdOLtzHgZSdEo27ovDBO tW/E3nHFIJGYlEwYcrVXK1B1FXD8e8HSv6pr/iRY= From: guoren@kernel.org To: palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, greentime.hu@sifive.com, zong.li@sifive.com, atish.patra@wdc.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, wesley@sifive.com, yash.shah@sifive.com, hch@lst.de Subject: [PATCH 3/3] irqchip/irq-sifive-plic: Fixup set_affinity enable irq unexpected Date: Fri, 23 Oct 2020 10:17:25 +0000 Message-Id: <1603448245-79429-3-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603448245-79429-1-git-send-email-guoren@kernel.org> References: <1603448245-79429-1-git-send-email-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_061835_748377_1CF8E3FB X-CRM114-Status: GOOD ( 15.64 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, Guo Ren , guoren@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren For PLIC, we only have enable registers to control per hart's irq affinity and irq_set_affinity would call plic_irq_toggle to enable the IRQ's routing. So we can't enable irq in irq_domain_map before request_irq, it'll let uninitialized devices' irq exception. The solution is to check the irq has been enabled, just like what irq-gic-v3 has done in gic_set_affinity. Signed-off-by: Guo Ren --- drivers/irqchip/irq-sifive-plic.c | 45 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 0003322..1a63859 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -130,6 +130,36 @@ static void plic_irq_mask(struct irq_data *d) } #ifdef CONFIG_SMP +static inline bool plic_toggle_is_enabled(struct plic_handler *handler, + int hwirq) +{ + u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); + u32 hwirq_mask = 1 << (hwirq % 32); + + if (readl(reg) & hwirq_mask) + return true; + else + return false; +} + +static inline bool plic_irq_is_enabled(const struct cpumask *mask, + struct irq_data *d) +{ + int cpu; + + for_each_cpu(cpu, mask) { + struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); + + if (!handler->present) + continue; + + if (plic_toggle_is_enabled(handler, d->hwirq)) + return true; + } + + return false; +} + static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { @@ -141,8 +171,10 @@ static int plic_set_affinity(struct irq_data *d, irq_data_update_effective_affinity(d, &amask); - plic_irq_toggle(&priv->lmask, d, 0); - plic_irq_toggle(&amask, d, 1); + if (plic_irq_is_enabled(&priv->lmask, d)) { + plic_irq_toggle(&priv->lmask, d, 0); + plic_irq_toggle(&amask, d, 1); + } return IRQ_SET_MASK_OK_DONE; } @@ -168,12 +200,19 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + unsigned int cpu; struct plic_priv *priv = d->host_data; irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); - irq_set_affinity(irq, &priv->lmask); + + cpu = cpumask_any_and(&priv->lmask, cpu_online_mask); + if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) + return -EINVAL; + + irq_set_affinity(irq, cpumask_of(cpu)); + return 0; }