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Fri, 23 Oct 2020 12:27:45 +0000 From: Sandeep Singh To: mathias.nyman@intel.com, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, sanket.goswami@amd.com, Nehal-bakulchandra.Shah@amd.com Cc: Shyam-sundar.S-k@amd.com, Sandeep Singh , Sanket Goswami Subject: [PATCH] usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC Date: Fri, 23 Oct 2020 17:57:13 +0530 Message-Id: <20201023122713.460551-1-Sandeep.Singh@amd.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [165.204.156.251] X-ClientProxiedBy: MA1PR01CA0142.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:35::36) To BY5PR12MB4098.namprd12.prod.outlook.com (2603:10b6:a03:205::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from jatayu.amd.com (165.204.156.251) by MA1PR01CA0142.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:35::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 23 Oct 2020 12:27:42 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 23a13bd4-d53e-4f74-37b6-08d8774f0b54 X-MS-TrafficTypeDiagnostic: BYAPR12MB3590: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; 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To fix this, need to disable a bit which is enable in sparse controller. Signed-off-by: Sanket Goswami Signed-off-by: Sandeep Singh --- drivers/usb/host/xhci-pci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index c26c06e5c88c..bf89172c43ca 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -23,6 +23,8 @@ #define SSIC_PORT_CFG2_OFFSET 0x30 #define PROG_DONE (1 << 30) #define SSIC_PORT_UNUSED (1 << 31) +#define SPARSE_DISABLE_BIT 17 +#define SPARSE_CNTL_ENABLE 0xC12C /* Device for a quirk */ #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 @@ -161,6 +163,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == 0x15e0 || pdev->device == 0x15e1)) xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; + if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) + xhci->quirks |= XHCI_DISABLE_SPARSE; + if (pdev->vendor == PCI_VENDOR_ID_AMD) xhci->quirks |= XHCI_TRUST_TX_LENGTH; @@ -498,6 +503,15 @@ static void xhci_pme_quirk(struct usb_hcd *hcd) readl(reg); } +static void xhci_sparse_control_quirk(struct usb_hcd *hcd) +{ + u32 reg; + + reg = readl(hcd->regs + SPARSE_CNTL_ENABLE); + reg &= ~BIT(SPARSE_DISABLE_BIT); + writel(reg, hcd->regs + SPARSE_CNTL_ENABLE); +} + static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) { struct xhci_hcd *xhci = hcd_to_xhci(hcd); @@ -517,6 +531,9 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) xhci_ssic_port_unused_quirk(hcd, true); + if (xhci->quirks & XHCI_DISABLE_SPARSE) + xhci_sparse_control_quirk(hcd); + ret = xhci_suspend(xhci, do_wakeup); if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) xhci_ssic_port_unused_quirk(hcd, false);