From patchwork Tue Oct 27 07:29:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859563 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0E8B6A2 for ; Tue, 27 Oct 2020 07:41:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74D2121D24 for ; Tue, 27 Oct 2020 07:41:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="QHWa/QCV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2507918AbgJ0HlY (ORCPT ); Tue, 27 Oct 2020 03:41:24 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:52062 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2507915AbgJ0HlY (ORCPT ); Tue, 27 Oct 2020 03:41:24 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IdWElrXDmpQFoaco0m0UMCnEmctd1bd4PoEePTk0JSNpk5yromOAxNldMu37CCK2ZIgpti9GpZPrJwdql2wY3gsmIwvD3x+LLhdrDl6pMi2vdpg9i4hxEsYg+gGXONxZyV4H4RdgjeUf7UWJcBXJ3o5d0Wn3K4vFpEDmTPvpBgKpbBLqaEufYHw6+PCK5DgaTlavXhj6fn3OT19NSuj2Ffn2ZcjnqUzrUhwZKsvYOI5yXr3ZLItJk4KN714/laINz0uLroQW4IEkc+svLyYeKp89pDhvzkV8B4xGnic7PR/hgZ86m2nDhaS9xTGYmGR0RfHD0MkuzS5vE4rrU6GlGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BNHXEGy2yAClFxnnxK27LPkHhQdirPb8SHOBfrSxyN8=; b=fA8cRL/HovhCNeAGajAdM9n6cJ7/OMoKT42812FJjvVVviQm4AaHQGBjsdqO3bNocYd/uWUxbAkPDdCnKHk/Qz91E/7qKrSQrFn5rWGAbpMq57aHAk9totudA+EKEeibENS4MHE0OiAJJn/6FoRMo0GRJD8CrWsy3vnyo6Utgn2JvBw6smADkBK6saBBdM/0FbzNRQZVnO/ipBQZ1dJwv+t5q7SCNK1zSXoSvrlcyEEX/OzMM3S96UuXY625lUgtE5YY5IcJ7H+n2ZpaspAg86iwt9CP20VXu1zm9R47K6ZohP5UJ7IJzikjUxmI4/H0FBSdKwR6rijAEhYrwNmhNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BNHXEGy2yAClFxnnxK27LPkHhQdirPb8SHOBfrSxyN8=; b=QHWa/QCV0mYQ9zNLIMiUkJwJAgXL+tlEkRsprF6vJUlYFDSbyDE3xqm1ZgN72IWWX69lzbnp0tpJ05AH/onXpCMXTONmTLdJKKLhO7OPmvIDWKYci+PpMM+j/XgVSNLQW5EsduuAjCv+ijqOKIL5uzGoVDUPm2iZOhWH1iwsfgk= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:40:31 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:40:31 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Date: Tue, 27 Oct 2020 15:29:55 +0800 Message-Id: <20201027073001.41808-2-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:30 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6eaf557c-4359-4ed3-5895-08d87a4b7340 X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1923; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SN55S+tQ5kvCT8+DOuLgOZfkACA+j/oS5WsPGJuocsFJVBqfVAQETxQZtkE3eje3vrjuk9IMEZsByol52xBpEFuHxoQpg6kCSVWa9bJrOjPWPNHlnMBKl7A3KzOXfO5smHbvp0xrJl4eT6Czgg1P+STPkC7QqQGucrtbZ36qmBPJk4FT+IVLztACU6nv7Apqt9ZwHKEFoIisppKqjksWLZYhaPPf82xHzm6ovQ4DnPuRpzyHNPaLfw77Io6gbhD64B3Q/4Gz4oDKH/pdlTaCZnHwjO8OwT75kqItfRZmyJhjGEb18EM78f9CsxpVCMFyPFEZIdcapcds63l8sYlOR764x+vPyoWQ3Z4yI5C8h/JRptTHxn8jpu26bWGjs8NLnI7iITf2D0KLndY0cspuIQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(366004)(396003)(136003)(376002)(346002)(1076003)(8676002)(5660300002)(86362001)(2906002)(186003)(8936002)(6666004)(4326008)(16526019)(6506007)(26005)(316002)(52116002)(2616005)(36756003)(956004)(69590400008)(6486002)(6512007)(478600001)(83380400001)(66556008)(66476007)(66946007)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: hcm7Ul3kfTUBEhXGfVzaVLi8l6i8ncnbD2Vt7ONS7uUPPQiQ7Snw7h3D9UZdWGPQUyXproUxjxhk94qc+wss0nuM3JzfPcmu16UlPDMoBPwYk4+r1UFdq/z4C8oxtBUTZeKUn1K5FJ28dk/QEvGOXQOWijEdmMRZ3cGG4ue9jrgMaSVsBNvvR1rIdoJzxGo8AeCLbSktCtGQpIpDefSjildnDQ3J6kSvgaDREy86l+9C0UDh++JLpfnylodpMUAm8uUSaF9nkWF3KhsSw6wrueVvVddxNkCZj1l+MgnVOtXVEDiWTd1K1azbq5xnHRKH9ptYma18XFbjPq9HkBDPIurVVhVgQqZwoQXQkf99uCCA89eP+n9NA9v1Nthmyxa52dxi7YCUCuv97FyTPbECuM+R3blreBYwMiUqeRbRXa/ADm8zFmR/Hk8BdrzKirVmFoGb4sHRf+rFpq7dXe6lfCiJ20NR+ipZlgQLk4YFg3t/AJYCKBMLJMKG1RT66zQUqPbhWwjGVPb+YlpOYboOyT8vBzs90/SDvUuLacA4GD6dQiWf1LHdWRyi+KiFHKghd5B0PpuD1z9q8H+QoRbn7pW9uH9thmYHRas0Qie7X/59HbGEwCkItVurbcILaIg9lXo23F4QspkmzOsAqr5Wxw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6eaf557c-4359-4ed3-5895-08d87a4b7340 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:35.1615 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AcmWZNwpZLAw2uXMSlnPGOh3RIzeEEp0K9BoJExg7cT92+/5qrWZhEwVWO3k3u72px87zm4SzSPQ+IIokCHNtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The dw_pci->ops may be a NULL, and fix it by adding one more check. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Acked-by: Gustavo Pimentel --- V2: - Rebased the patch against the latest code. drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c2dea8fc97c8..7a5024450c4d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -141,7 +141,7 @@ u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); ret = dw_pcie_read(pci->dbi_base + reg, size, &val); @@ -156,7 +156,7 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); return; } @@ -171,7 +171,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi2) { + if (pci->ops && pci->ops->write_dbi2) { pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); return; } @@ -186,7 +186,7 @@ static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); ret = dw_pcie_read(pci->atu_base + reg, 4, &val); @@ -200,7 +200,7 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); return; } @@ -271,7 +271,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, { u32 retries, val; - if (pci->ops->cpu_addr_fixup) + if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); if (pci->iatu_unroll_enabled) { @@ -479,7 +479,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) { u32 val; - if (pci->ops->link_up) + if (pci->ops && pci->ops->link_up) return pci->ops->link_up(pci); val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); From patchwork Tue Oct 27 07:29:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859565 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE247139F for ; Tue, 27 Oct 2020 07:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A7A5322281 for ; Tue, 27 Oct 2020 07:41:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="SzF82xoL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2507932AbgJ0Hlk (ORCPT ); Tue, 27 Oct 2020 03:41:40 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:52062 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2507917AbgJ0Hlj (ORCPT ); Tue, 27 Oct 2020 03:41:39 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i0NV9uj/TvpYJRlqa+oOiAxGVEXGuGo/DAw543SxmdxFz6qq42xTA4Zfz05/ZpJNN5qCtAM9rlsRJk+iKlQdYt48SqGQGNYHuHdO9MelU21iCMBC0YcH6OpoNytZqPeYjq9ixRIaEU7WBC5J59suhlUwtoiHgl4rf+zaQAHyg2GNma/pDEYA48hY0NcGmvKzdawukr4TEOipsNBBolrzh643nOXQGpE1RnV7Pg6p/FaM2Xg5ZM1AZK0w3rOBjQEEjVnd0o+JQpohTlUefSWkJp6Nk/8D+aEIhk0Uaf8GUtLFtjPpto0i7ghmhXg/5IbSARWNfVSA2iVy/u7AzNhxNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7HWFnbpm3lNxRVHZhaOrIDDULzGG9/ubtiVg+c3NDEE=; b=himzGNgcggoCCdwR2+TdNPAS2dAkepAZ5kVrqvFCMqIZGxHH+Wq2WJqs2wKt+h+eIIa2DJl3ifrLYLy0KKqsgCq35+JaThSgKbQimdKNSX+WkfyuA/dAMbXBg1B2Ws05PajemQSY9vrebm9nlLcq4C/sbpu8wPZGZqbRQlz+npgLdoMZ63ANAv0b5w17qgW9F1Jpd0cTc0lmSb+7VuKT5c3NuuT+LRVJ1JmzrbEE8I11Wo5RcSN2AFwr+sLl7giaCS7y6V8PJFd/6w9wBYALn6BEMf7g/oV2NGJswx6OgoaEgWbizcXFstVWg21E6DRyl7T5r0Gw39s4Oxd1OTeigQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7HWFnbpm3lNxRVHZhaOrIDDULzGG9/ubtiVg+c3NDEE=; b=SzF82xoLZZBdeQTJ8gvfhi6/njyS7sGtNBplIpbGxinpV+VEcI+OxVyNDo6VoulgrI62dTSEK80h4UFyTT9RzMBX5BPslsQCvYFJq95U2gaDbAY/1ueCyydV7XXsiZhIIMMIR61cN46WJBvueSoifk+f/wBuMjWWidEB9Rp0fak= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:40:45 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:40:45 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 2/7] PCI: layerscape: Change to use the DWC common link-up check function Date: Tue, 27 Oct 2020 15:29:56 +0800 Message-Id: <20201027073001.41808-3-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:35 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4ca8f199-4cd8-4a0d-3775-08d87a4b7645 X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: np507AMo7cQ4wHapQbBO6LckgHVj7bDJ+azryxnwFfQZMSkLCrPNyGVKCbMuG1SjuU3e9lfbC/Zq3KRRGiBqpaUU+qDek7C7OwaxTHej/XFY2kki/IHJ27CtKyEn8+q11wuGGhRv0RTsUZOd145VclEelVdsaD11oRHjW1Ep6Qv1XvLua4ev4eC0g4wzbcrxb4zvTNQJzdBA4b5ylqIYWrLU9SFxvbKpjMKpdnYbjvbHFikFCqkvD61kCEhxBDEfrpzaNf4myPLAfMnVn73BiKWu59PF5HSg1P4Ljb8I7u1+U0NFwUSHOwb9yCP72tNaMxeQbUDiOxq0F/hSW3iQY200Dd9PbTqhkU14WYy0zOZK41OVRwSCTZckJYKiea9ws+iSg+DALLe+0dxeybAvng== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(366004)(396003)(136003)(376002)(346002)(1076003)(8676002)(5660300002)(86362001)(2906002)(186003)(8936002)(6666004)(4326008)(16526019)(6506007)(26005)(316002)(52116002)(2616005)(36756003)(956004)(69590400008)(6486002)(6512007)(478600001)(83380400001)(66556008)(66476007)(66946007)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: WP4U8K6hQly6wYMspwox+imRTd6DciglRBHl9Rd6cRS8+5rW0k9lxXBwLnRmeNzGe778KgOFe9GIMAs9EHQ2UB0jsjzXABsZumtXnOny1erDdv3Gg1kUNO3nbvhJNzZRtGvYP5+AgMIspjhTTqk3olB6EtnXmH4wAy/BkScbV0lpke0sKYQ5F/hvZPbfkUuK3nymiCYSLnh6e/y8amm+qJGynpp9HgUeHAOJUoaaWGKVfL0OyvSCaqJtypemAMX5IcANc6e0nGH8+3Ksti6HDgKKpFhZTEBGb203xMXAnCvlkyni+z+O2mPeMTkgRxjQJqQVfmUQs/lAF0piH4Ej3xbQRBy6hVF2zsPfZ4qagAhpB5cI0IuVn1lP6F5z55GI3uUs/n8xLwM+96oQRjc0Ulu8/ExsWNTT3oU4Q5aK1WmwPf6iTYUIrSFduLkMKP2PCJno9mfkHtLru9aPTz75/+OpxODTqlipeDsnrXafc4yi2Lzn8axFeJVqxVnIVxd+KKV3y09BOSOIvfvfAaktw4+FjlXm97Zf5hj0KFXPfOGvVmYUhnQPVeKxXc8R/x+D7i400PisYezuc6XWwBwV7OmZ8KtcrkDMeLzFMXR0VZH3rtNQERtZ+uF8KKHwwB215GZ8NQiCuLoo90+URhrbUQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4ca8f199-4cd8-4a0d-3775-08d87a4b7645 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:40.3056 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gEr3RK6f6r8SrOEHPAijghGt02oFNjtAnS8T8PjDE5S4F39kkqGbbzpzphlFE3JDzv8LBwE4VeJVr79LAuLi5A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- V2: - No change. drivers/pci/controller/dwc/pci-layerscape.c | 141 ++------------------ 1 file changed, 10 insertions(+), 131 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index f24f79a70d9a..be404c16bcbe 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -22,12 +22,6 @@ #include "pcie-designware.h" -/* PEX1/2 Misc Ports Status Register */ -#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) -#define LTSSM_STATE_SHIFT 20 -#define LTSSM_STATE_MASK 0x3f -#define LTSSM_PCIE_L0 0x11 /* L0 state */ - /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ @@ -36,19 +30,12 @@ #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { - u32 lut_offset; - u32 ltssm_shift; - u32 lut_dbg; const struct dw_pcie_host_ops *ops; - const struct dw_pcie_ops *dw_pcie_ops; }; struct ls_pcie { struct dw_pcie *pci; - void __iomem *lut; - struct regmap *scfg; const struct ls_pcie_drvdata *drvdata; - int index; }; #define to_ls_pcie(x) dev_get_drvdata((x)->dev) @@ -91,38 +78,6 @@ static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); } -static int ls1021_pcie_link_up(struct dw_pcie *pci) -{ - u32 state; - struct ls_pcie *pcie = to_ls_pcie(pci); - - if (!pcie->scfg) - return 0; - - regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); - state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; - - return 1; -} - -static int ls_pcie_link_up(struct dw_pcie *pci) -{ - struct ls_pcie *pcie = to_ls_pcie(pci); - u32 state; - - state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> - pcie->drvdata->ltssm_shift) & - LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; - - return 1; -} - /* Forward error response of outbound non-posted requests */ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) { @@ -155,33 +110,6 @@ static int ls_pcie_host_init(struct pcie_port *pp) return 0; } -static int ls1021_pcie_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct ls_pcie *pcie = to_ls_pcie(pci); - struct device *dev = pci->dev; - u32 index[2]; - int ret; - - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - ret = PTR_ERR(pcie->scfg); - dev_err(dev, "No syscfg phandle specified\n"); - pcie->scfg = NULL; - return ret; - } - - if (of_property_read_u32_array(dev->of_node, - "fsl,pcie-scfg", index, 2)) { - pcie->scfg = NULL; - return -EINVAL; - } - pcie->index = index[1]; - - return ls_pcie_host_init(pp); -} - static int ls_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -205,71 +133,25 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp) return 0; } -static const struct dw_pcie_host_ops ls1021_pcie_host_ops = { - .host_init = ls1021_pcie_host_init, - .msi_host_init = ls_pcie_msi_host_init, -}; - static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .msi_host_init = ls_pcie_msi_host_init, }; -static const struct dw_pcie_ops dw_ls1021_pcie_ops = { - .link_up = ls1021_pcie_link_up, -}; - -static const struct dw_pcie_ops dw_ls_pcie_ops = { - .link_up = ls_pcie_link_up, -}; - -static const struct ls_pcie_drvdata ls1021_drvdata = { - .ops = &ls1021_pcie_host_ops, - .dw_pcie_ops = &dw_ls1021_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls1043_drvdata = { - .lut_offset = 0x10000, - .ltssm_shift = 24, - .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls1046_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 24, - .lut_dbg = 0x407fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls2080_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, - .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls2088_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, - .lut_dbg = 0x407fc, +static const struct ls_pcie_drvdata layerscape_drvdata = { .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, }; static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, - { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata }, - { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata }, + { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1021a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata }, { }, }; @@ -310,7 +192,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->ops = pcie->drvdata->dw_pcie_ops; pcie->pci = pci; @@ -319,8 +200,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset; - if (!ls_pcie_is_bridge(pcie)) return -ENODEV; From patchwork Tue Oct 27 07:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859569 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 198BC139F for ; Tue, 27 Oct 2020 07:42:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E42072071A for ; Tue, 27 Oct 2020 07:42:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="aVmHU+Fd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2507943AbgJ0HmU (ORCPT ); Tue, 27 Oct 2020 03:42:20 -0400 Received: from mail-vi1eur05on2086.outbound.protection.outlook.com ([40.107.21.86]:50144 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2507940AbgJ0HmU (ORCPT ); Tue, 27 Oct 2020 03:42:20 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZVgUyI+WT3haZBT/jQkJEhW1KW4Ad1vmRqGWu98voOd1cHA/StCcXNoQWJr7OZHZAkfShP8fqbvCXj1OLK3btJZerqxbh+iMp9FLmRqUzASmFiplKD8KPW6g8jkWAFTcZdaCNNNFY52nhb0NLnn6zv2CwgQ7l7R2vn1xLV8L5ClR9ceGjvWYeadgB+ikNmNVEO2TtA70YH2Ss9BfE2C9W5KhGgHyzuNIhgAGWI3CK5kQlMgBtNOBtPQoTYEVn5es0NinOinpsGDKCePQmDdP/OUpOGM+XscggeRH3qkUIvcT8xqO4h3xlr17rXrXwkLLsmjHS2h0jAgbC/riKdQ6Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kgmGd58G/NWc3kA6pQs1GSF1desYjmaoDKf5hDKPHEA=; b=nQq3JUdqjaZnr7t4LXRqKwF5+qgJBKv4VyF5x1c/xkElz+vMB5nX2Lk4ku27Kj2oviEftt1Gn4Qz/j5wnAR6Xg+gJ4esz6zWhC8n2wEKJ0Ad3VjoHZnlGd7MP2UJeShPRCVdlV3eZmymjfnFWTJogpFxe8VtiA8vQWmUuc6ZQZNhzPo7K37X0APBwIGcVFESjYWV8xsTbW2iM5nqBlNF4UQMFWqCpxTDLP6QX61C/fOBm8rFHWR4qVh7n4LuSc6SmPfjds9oei73YOvgye3Z+dglrcVJ1kGyzTFWH+/5az3GGyIc5XgMnNFBrNVlYD7o500Z6pDQNT3JvorYhY0Lyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kgmGd58G/NWc3kA6pQs1GSF1desYjmaoDKf5hDKPHEA=; b=aVmHU+FdsuGXc60xjuVctxQCKEPc9D4QszEQ5GYhm0y+X0/tuJ1x42bxVVC2oF+5o/gGR2q/GrMTQeFdv1kXdYqrRoBHPfDHv0j9ZJ+gJp/aPiqwDSScR5etm1W0NR1fUykZ8bg9NhyRG2cyjHp9gBCbh/k/XISEKh5WaDmC09M= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:41:21 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:41:21 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Date: Tue, 27 Oct 2020 15:29:57 +0800 Message-Id: <20201027073001.41808-4-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:40 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 27949b19-062f-4f32-4eb5-08d87a4b794b X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: b+zUsVMYCrMDIycO9L80HzaoOb6tlm40D46ycCIt6xhNw8mk67mEMi8IoTFr/YPB4jAV1O8lAMKU9TJcRSGVTdR+1XpqUkRyoAPcphK5nQTO/0zZqp/bDvCUy7NPG4hhACYgEa79GTGJfgPw9ahcvBrXAbuBa1sbyQpqP3MwSwTVAC5KQAa/KqqyOWr3HvRKq1QpOZz8X4GGpq4+on1J6cOgqCKE9NEo4v4ve2dlu4TfFoF/vzgO+xscJ8WVhumiF/N0DUenTjR2Pk8qaABIIGnnEkoPHRKk2EbxcguDhG4950f2WR67jYp/5GZRf5ZrtWU9v5ftQBG41GxV1+VO3o7LSx3VHLBjNnuSmjxFXoVCmcPFG+6u/3kSO7REZ0cDyIm3Srf3a1JOh7EMZqc1NQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(366004)(396003)(136003)(376002)(346002)(1076003)(8676002)(5660300002)(86362001)(2906002)(186003)(8936002)(6666004)(4326008)(16526019)(6506007)(26005)(316002)(52116002)(2616005)(36756003)(956004)(69590400008)(6486002)(6512007)(478600001)(83380400001)(66556008)(66476007)(66946007)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: N80xbcbm7u6SY617svPAUNgoLxBlzFOZOLmMc2VnKwjZUwpUW4zKU5y9OuMBeK0FJVteuG4lONw2MYMPH6C5H7sJAnp7HhHpPpWPsEo5evgZeydxfirHek6sLwuU0bfC8eT+SHPvsfETaONKXER/5fBoTuCuClJHr35tOxXE3oRRdN7ASkoqWkRAKlJcpCbodGwVQMEoyZh+kICgqSDPslJjwwmaOUfaFg0Tp5Y6FkLV5ehm7Q08ntlzUF9nhKRhcJqAuvu2dREYYtGCxIToAdSCC0al6EuOZVjG2oh/sauUVJ37dVZRZqy/ToFp+51EJ8WZVNDV8igzpDZGzu28u04KX8sHwPwKxxJs6v5lM/DNGZQG4bEci7jLe/5kK57D+cAM5kEhkiOQL2DC11TZMLfIMl62jXXWWO3zF2OhrF8nKGF7dt1q7MLlYzFnXp4htR1D4OCLMuE3teecmEEMsBKT52Ri5XKJsFh0JAn0XapGTdrFzOTE0fm1Hogcu3gT0cBZQOwjH5i0qmiR4sfM/puqKpHwaOnk9HABCXJAP1X0rM69KRU2jOMA/HRqkuQw8Hxap+7tV5/xPW52/HB29SOHPMTrKQhjeRRFOS1FyXmPsjUmDD2Ett1hCi1UWFc8RtU1sBIEyXigrRFCR5zabQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27949b19-062f-4f32-4eb5-08d87a4b794b X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:45.3177 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2UZVWCqxduxQLLnGxSKJIU1EP+IlzWO1Rd/6vpF2cIvya4tKrQJ9jrUjQyaEjjf0+U/3iZsTMprjrazih4l+OA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..0033c898976e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -39,6 +39,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { From patchwork Tue Oct 27 07:29:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859577 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84FF26A2 for ; Tue, 27 Oct 2020 07:43:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58EFC21D24 for ; Tue, 27 Oct 2020 07:43:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="ZJ3XkFpB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729229AbgJ0HnW (ORCPT ); Tue, 27 Oct 2020 03:43:22 -0400 Received: from mail-vi1eur05on2073.outbound.protection.outlook.com ([40.107.21.73]:45137 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2507972AbgJ0HnV (ORCPT ); Tue, 27 Oct 2020 03:43:21 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=T022JTdVZC/09QfXPgX3pFjVgvd3T9JUKtzLWFsMth329TwdLp6Qyd8IpWJo4li0q2xWq7WBIAKtlBDOLjaEcSP8lg0PBele0xovqptlHeXmHQet69oW3eBOyz3SMKQkWuq60M6Q7aDHqETAK+C8+gzFj/Y5qDD3c8TKvZkkLyunrCYg4nxTMO9vvbCgC0kVd+PPoFEOa3rHUGrjXjXQyQHDl9OHx6OSjYKFXn3Q7T5kSxuMiNPJiFQuWPWwXeQHUiA4VA0W0qPGsuIH5SjFEzDM5xTEYErRl/p7ylKTBBoYK2qcvfTwLgAQCAswY5hJ9WeCoKRw2IZZjVUUdhQT4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uzF1q97Q6m4XmQWrzKHzORKpyrNgqKqqz4LG63VzAEs=; b=dEnYo7HWypmiZi9Oj01Hs69VGHRskqvn21sKXClSTvAVhDJbceDdiCPVn1tXnb05BeOrhOuX6im3K1f2rb5VD2eKuckpvoOb7G6cf9AZvAnNMwNqE6UYnirqxwqMv1uLvoc1IJnAj2rqvbn2kq43e6kpbD3lIfftmxjkYf3NabP8OPlqcPvl/zh9ARU3xS+QMUMjagDpYGkHZs30gb0XHamzHq0E+XmVwFsi9OOpPTQtR/NF66ijW52WxrYOpuqmdEwXvjpkfvsYWixeBporENrO7qLU+2lESspUo27HUWWOgXETD13hVY8cd5W/95QNIFlZmnb5+WCcqlNcSvIAhw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uzF1q97Q6m4XmQWrzKHzORKpyrNgqKqqz4LG63VzAEs=; b=ZJ3XkFpBGz16IaHtF5EBpRdzy9zGgAlVfMFRQqpICuBgzWwxqoiHgX6MdoSHVz6pUYvi8mSHv8IXyDToIPdyWvMPuX7oc9SbxgprpREFqtMkqPLF7e+HEregiovlzkXVHpadczn1MsBcv3o0SAkdvnLYSIb52GoHGlxHhAmCtvU= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:42:17 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:42:17 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Date: Tue, 27 Oct 2020 15:29:58 +0800 Message-Id: <20201027073001.41808-5-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:45 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 70162701-d6c0-4fe2-13fc-08d87a4b7cc4 X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2449; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3NWbvToTS6rdgeFmOuwXBWExdAenb//jhFm8L/Z9oBh8UeprgXuQDtdEogPbTN7oDm90MGVD6Mh6nTZv2CqAR1E17QJgan9OynTo3nPFYIf+ExvhRo/lfjGmwDH0uTvLbgdDJN678U8kU85d+2jeDadlw8BVf3FRZP6q31ZldXodSP4uW9trR3+xsFn0NYPOj+j6vRtNKSr8I29W4/DoRGqN3G5rHTHGTOnYYvvHJ80r3o5i2fGU61eZ4aky1raPYDz8JnAKnv0wI1w00KsN19q6ZwyR5IKaIauMn6NQPG6klUxr7pFT07+RUoyYAQ1w2BUwVOCINO76hVkbDYwNG8ghKy+YdZMy40RGF/9l+Ai3biBhRZDeUZajvxZw4YUrFJFJSOQms67jG2C8mAu8oQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(366004)(396003)(136003)(376002)(346002)(1076003)(8676002)(5660300002)(86362001)(2906002)(186003)(8936002)(6666004)(4326008)(16526019)(6506007)(26005)(316002)(52116002)(2616005)(36756003)(956004)(69590400008)(6486002)(6512007)(478600001)(83380400001)(66556008)(66476007)(66946007)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: sBpgyDbWs4TtWPygTFY6S7hB/MGjihfWw2e0EoITcctY5dNUPp4d3D//H9H6yNKtN84vTDAlFqilv/FQjNc9SosfL6mKeZJkEyaC8TBz/wUyiK1lN6VGd9eYEnFg1ML8t2/ODGdOaGIoUkjAi58XboTilCGxwUHfRueUDUZf3ER5HZ0jdyocj5hXdwRFfMpU8nGsWAwMBzVDhYtraEN126KJZgFdms0GZqzvHbgKFFn+VtYLPQM7lc1sA4r2/kEH7KFx4at0JrxPHsliKABPEEMBnQamiKgaytkWlJGr9LAlLA3ZfYXGCgodkok5Xg15qCC0eGKhMzZcbGnThrJkTbOVBWS29jOSOWXxQ3uhRFZV83MKV2ADXJuG8i0ijFLfQ1IJWFObMepofDlRZWkdqs9XFOp28QIlaNPe999qUGjaifdclRlFFOogVI6FdhmWayx3MH35cL9La5blSnfu9XZIk9AQtskE4kRVT93T9m/25lER2mN8KaFow+9Fbu2LvzPSh2VcckRms3eZ7oGfAggmATvMQmuWsBH4BNZuz4pUcxoadppZdJ1QofD5PiUZ5ZRXpk4MFQCnp2pjrmoKnHiRAC3tODhMWG2l6HzVYKkdDEYwbCoLzlAo+BBj2XcHjPOxSjgNXX1mLkOlqJU5YQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 70162701-d6c0-4fe2-13fc-08d87a4b7cc4 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:51.1093 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hAJHtBXuVo9AMks46rGmzolLobeRY4i2AXwifK4Chu6paJ70ZA+xpUan4O0Z9M4tjEMRJlnXSppvbZiGu7/Ckg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Add the big-endian property for LS1012A, LS1043A and LS1046A PCIe devicetree nodes. Signed-off-by: Hou Zhiqiang --- V2: - No change. arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ 3 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 6a2c09199047..0f63aea30477 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -512,6 +512,7 @@ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 0464b8aa4bc4..d33a64ae8b0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -837,6 +837,7 @@ <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + big-endian; status = "disabled"; }; @@ -863,6 +864,7 @@ <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + big-endian; status = "disabled"; }; @@ -889,6 +891,7 @@ <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + big-endian; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 1fa39bacff4b..b01fb93f7d19 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -741,6 +741,7 @@ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; @@ -777,6 +778,7 @@ <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; @@ -813,6 +815,7 @@ <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; From patchwork Tue Oct 27 07:29:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859581 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D514139F for ; Tue, 27 Oct 2020 07:44:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 765C12225E for ; Tue, 27 Oct 2020 07:44:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="kiPaHc0Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2507995AbgJ0HoS (ORCPT ); Tue, 27 Oct 2020 03:44:18 -0400 Received: from mail-vi1eur05on2056.outbound.protection.outlook.com ([40.107.21.56]:29377 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2507990AbgJ0HoS (ORCPT ); Tue, 27 Oct 2020 03:44:18 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dZ1YfqR8TW39YwcG+69sVRco4amvm/XxS5JG+Y+FumAdnpYxMZ7ABNTJ+ZJTJb5blsRmo4LXLS5PTwnzNVmhXZZuqYUw5qRGzPSW93vMuXjrw9YhvZFWEHcKJnbvBAm39SGtnbBtRlRzZ8ngQKIvMaYIe1uuoEIywoyYoKdxucSnYPmcpF3VAE2rdxdi5rRaFMQsAKr1TB2PJCkekAMm0JWH2XpwK0tpVpioNRhK2VqTvgcc9nAvAux7SYLaAX1o+Sw4Iw2kUbHmOttMr+WyTYgadZc0yPVINxHadtyh3bRvcPKOvXljoDPz9j8eNpYul/mVrSw+HOIXTgjxkNsi3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jam39fFqyA/nzkn24XXLMaYiMtAQRjPcA+ORlQbXaG0=; b=jZfule+PVJEy91PEqWZxOzSnq9BOh8kzW/V3tk9Vfa2XqFfZiCLE6mDsrte3cbzP9B7OwCgKYxlt9SK73Vk/a8YChZTKtVdEeuw54DvDbZYSpS145k0COaeVY5wsISgpMQlD2F55GwGUGlhUUUdtzNiDBGD0hPwIAEINQZl50uo6c0AoIzrBTzgQl8XDCqLeLYo9Pys7xcUt3SnEp7CYAP2pmYZvAZwI8gqIXWbS3cEDo7RQwSAFJzgqdVCRK7U9YKRaXmYA0OeeSAb9J0KUkKxeazOMi48gV9uXL//z3a/7pRF+pjTXWCXJAtK6sDoBX1DjEJEzd8qXg5T3q7n5eg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jam39fFqyA/nzkn24XXLMaYiMtAQRjPcA+ORlQbXaG0=; b=kiPaHc0Z06WZraevFDvLz+CR380P/VqzKURQ3/5mI0SdKoYIa7w/rHu2gEwk7pbqQarz98vlPVWKGeUUFr41om50FvCRPfg0HjEFGIVse0vDjwS6C4xECRUnLQptjPUq5p91hUkCMNje5+3mYakmeRSlptD4MUOSY94xtftuxww= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:43:14 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:43:14 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Date: Tue, 27 Oct 2020 15:29:59 +0800 Message-Id: <20201027073001.41808-6-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:51 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5d3337f5-7036-4408-ff11-08d87a4b7fd4 X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QnrwP/RW2sQG5QMQ1KrPgq+fP9BOQzeApsn+n01bBC/IXx15IgVo55kKH+0ULcAtoOlQDHy0yHdaodIJP27Ct1fX7Hvu/d65ZrRPCg/+RKCoZQ0CSBjdgsi/XVb1obKLOr5i3pFlrxQISxgQ9eJP4rXb+052i9keO+1uXh4+u6inW3LYORK+QzasV7g2rwZlZlhYJ20q+KanNhJHZnebTlmcF28l17JfxXg+doqK2FzuNW+m1/+S9kh2qC06P80ORAfBB0OXi+n+KVuhsd3RJdd18ODEo6ic/6Ngcvx6m25Y+aIj+u/M0ydt3zM8hIPuq+Uj8bmXeX87NxfAxLdBAidGR695IZ1omWS+11fU+yJ6LHkWyW1ckrNz+5dovg66pj3MBKlaLSenmGOwIEq10w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(376002)(346002)(396003)(366004)(136003)(39860400002)(6486002)(6512007)(478600001)(83380400001)(36756003)(956004)(2616005)(69590400008)(66946007)(66556008)(66476007)(186003)(2906002)(8936002)(1076003)(8676002)(15650500001)(86362001)(5660300002)(6506007)(26005)(52116002)(316002)(16526019)(4326008)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: XuUH0p0QHO/y9cjkmoubmAcWJX2emGl1w/IgwDYOdW7u2Se3CjEWepFQ4+kRUHC0F9R2Rs5Hco6ljS8GU8s4cEG5Vw0ztIPpN6uvmqopa3wpH2MHDRdC8Vyt0BHalXFqKSzF2juVuGv1WIq+iCvyH4jBccn6JEIbvmdjr2YDvvkYV18u93mFAjOwumB7WERdqzym7LupVuMcnsOHTZNnl0zA1fK9vY2eyMZrTRNEr294ppFOvaVoN30RWcG9ozVpuUc5t9gW5AJ0kI3BMPXh0Kj5kJq78mdnTN7PED2PKRS8zVNyCPQeFr96JL1nXAndfFKO5iwY6BEDFv36Ubm8iIIdI6IA5pbxL9ZCVqs3G3jG5+LZ5e5pZbtdD/IGbCCFdGcnjn9kMA0Jgc1/waMz8PUBkJq3Hx09sgou6ibgVm4PpIS0I/zP0BM5Gp0yjiRADbE/NRwkoG8J8XWB33BQ06zUiVBUu/A/mdPeacNW+2r9CpB1Mgn/0cNG49ELk8U1lXjmLyfXfnruKM4yVoiXn8OwqaegFHqDLu5b/PQkxvddAl/KuoPbRvPZWT00ncovGNyICrpCOJv3twAqUAroB8qfadJilTk4rAkobLHZdcNXTF+zzS+HYo4zAmm55MuJjm6VhfK3wTNcIalY/Itg/w== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d3337f5-7036-4408-ff11-08d87a4b7fd4 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:56.3263 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KgbGZb71KK/+MYfxw23FW947II88IW5Xe5a4DIjTeW3eZAAewT3VRvugpJJM1iQqMJiIwPShWfQnJnQzy15L5w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 0033c898976e..4228562be505 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -33,7 +33,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software From patchwork Tue Oct 27 07:30:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859585 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0033E139F for ; Tue, 27 Oct 2020 07:45:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D020B2224E for ; Tue, 27 Oct 2020 07:45:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="qO/NjPu6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2508041AbgJ0Hpz (ORCPT ); Tue, 27 Oct 2020 03:45:55 -0400 Received: from mail-db8eur05on2067.outbound.protection.outlook.com ([40.107.20.67]:55521 "EHLO EUR05-DB8-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2508036AbgJ0Hpz (ORCPT ); Tue, 27 Oct 2020 03:45:55 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z7qgEeUgY7B4+0+oVrzv/Ofz1eDpyFV8TuNQr852p4bWx43Tz1TsFmmkZ38cn5QAyLoe0ZwtKRtf9D3Y5xc7Tz3CAvWhBcqy32Q8xsIBwhKecdvkQ2XeLHeS0i/tUJbpGBVYrwruPQHwdMaU+7xlM9piDPaoBjmAsXDlouMx9sAPRAPvUnu9/OLa2OseowuIHgO7ofaCowu+4FEo646pTx0O2UuCbQwdRD6CPOgRVUc0EvvTket9sclpSb5chBSsWSt/dt/oLCiKtqNrZsOxhcUgPk9pCR62YQF5F+RFHOQhnhBKJEc2uVTgul3nfiRK8V0iO/mXoJuRpYeAKdL++A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ze/uanjvDGeOjyHQEzfhjx0dBZ/4oWSUNg+9UOaFCtk=; b=SLNRAiPJfI8VhT1OttiJhm9v0H0OGFdxSg1cYXOzbgCD1SCpJawkgD8khD5wRMQLCP8DrSHbJkV8BS5WPfeROGIKP7PNooT1kd0Fk64yuUO7mk+SNpayqAcCsMEOwIu3SieFA/bSjUu+PwwUG2NDEtXb8XjuANHwqisYLR2KZchcRt6dauCjludCLgh/DdVvAictcJPXPC8TuS83dQoaDqU8NJG/UZ1u1fKi7tDSrLx3T7U+Hnjj7Q9G6dnYThOIlyf9d64EWSgILFJK/mSLEiB0ePr61eg/fo2ZIgbQp356lG+A4YTw5/OcaHeVVwK4Gxnzb4mfgJ99Xng7BEe+iA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ze/uanjvDGeOjyHQEzfhjx0dBZ/4oWSUNg+9UOaFCtk=; b=qO/NjPu64XIWOXhhOF7rMGPi9hjjVi5o3fSlfUPA/cZ8x49YEG24F+HY/XC7O6JUD7f6wTPwpOFjILr5RLjDUiyUbShu6uXBadAd7BheB2jYA41HBjLcV/ID6CDMP1iX4kFgkg1pI+4SdH4ij8f1gpkGycNRAnJb5+sW7ymK8/I= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:44:14 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:44:14 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 6/7] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Date: Tue, 27 Oct 2020 15:30:00 +0800 Message-Id: <20201027073001.41808-7-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:39:56 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cbce7ed5-476e-4a53-93b4-08d87a4b82e0 X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3173; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Dm5Bi235PWHEKvvNAqF0Ay2Jmg2/Hw5ZCznAbodrXsfyKXQuXldjC/37kS8C+uf/d5eMm8jTz/UtoIBKZ2cxbUYdJBQ98ZyIMPcybgadl1acJ0IpEbzcJIHM6SuSoOrztQXD3SgBgGOOA0NthfHALgRfPnmJed9Sd/pNdbsuYNI6P/6S2lxM2YHeENWYAEc1+Q6N7xB1B3HEACdN0Z0wN/kO1cXNi7ZkSopzoVWW780yXGFJt+ywvLrbgTF09sP97zvqOzgt3ZD/X1HURszHB4tzoqnimSFHWdGOCUCayb10RciO9jgkNj8/gnRsAHSUwwkUhdb6oKOchEKafc6GjuSu3X3JQQ9Vf1+VEzqVE3RSASzW5anfXt3E7iipI/wU0hHCSX1wL46k1OgeQ+gggg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(376002)(346002)(396003)(366004)(136003)(39860400002)(6486002)(6512007)(478600001)(83380400001)(36756003)(956004)(2616005)(69590400008)(66946007)(66556008)(66476007)(186003)(2906002)(8936002)(6666004)(1076003)(8676002)(86362001)(5660300002)(6506007)(26005)(52116002)(316002)(16526019)(4326008)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: JlRnMlKrqrzRfsKX/tWBDO1Iq/cbYOzdkxmqT/mv98tzp5HtZzUYqTTgSx+Z3gpAUuLa6k2xRLyTFh6iN4GWxYvFK7FxEAbPxqY48L2DZno1eEQwnoI52+lM6uu5iixG72a6guWKK72k2JV4UvemEEtgfisk51VOD9Tw01bOXcGQHH3RZ9EzGl6MyijSXEhbay+OtBa7DleYpHLXWjjl/eQw9MyEMl+RBCbdnMaGZXtGycr4Q9GvIAudVJ7Etbh/PGEbJPVkCJ34tM0AgxPOp5riFVr8JxgQSdIy/B4mVUiFLM7GKu9mXL5TZlhK6L5l0ysQj15dLth7bITZLKYf5JJyWBLidZJXBaYnTog7BefoNxq+jiC80kDVWbRId3jgBegcQu1yucfBA3q7XHnqT3Y4Yg1hdCxeyGhTF7mfk/2q0j6yt9AQc4qRqMR673cRmiZmG2vfBlL/OVq4DzinclDMwdfSbu6q44rhYHHbjp92FlrMSF0cqlwbJuyqQM7rLJKLBd8PfavJLvhaYvyBjGB+3hV+2aPjU50BxrtCaUolTGWc+goIrchDy+EhGbqoyDlkXNmnB5UyiWFFQX1NhXyXgfjE4++kPmN9uZd7Ntkd+70jEmj8YHeehU1zEJ0dHpDorDXQUnlrnhy3yaHSZQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cbce7ed5-476e-4a53-93b4-08d87a4b82e0 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:40:01.4804 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 39xx/b/plkCV1K99f7Zxt2dLpqFBC831FWJYl0UxivOYFPaaBPnzYfzVW1WuL9MDcSsiZC3uLQzPG/Yu9J1U5Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller DT node. Signed-off-by: Hou Zhiqiang --- V2: - Correct the order of the subject prefixes. arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d33a64ae8b0f..23bf3796d98f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -822,6 +822,7 @@ interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -849,6 +850,7 @@ interrupts = <0 128 0x4>, <0 127 0x4>; interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -876,6 +878,7 @@ interrupts = <0 162 0x4>, <0 161 0x4>; interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 2>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From patchwork Tue Oct 27 07:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Z.Q. Hou" X-Patchwork-Id: 11859595 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 739BD139F for ; Tue, 27 Oct 2020 07:48:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 402982224E for ; Tue, 27 Oct 2020 07:48:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="Sp5tzWv6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2508078AbgJ0HsQ (ORCPT ); Tue, 27 Oct 2020 03:48:16 -0400 Received: from mail-vi1eur05on2089.outbound.protection.outlook.com ([40.107.21.89]:24353 "EHLO EUR05-VI1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2508076AbgJ0HsP (ORCPT ); Tue, 27 Oct 2020 03:48:15 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UkLlySo1i+qmpLrSASmzsZJha3Pv5Khu99EwyuHyE8F0qAEZegX4gyHSkceHJF7Xc1mEgGkc2RpvJuz6NvZcsk46Qre/yDjR++s4PewFLNthEqfvWgJ4bYk5A3IFpV7sINWyZU1zxFrnNUHYuCqN59BahuKkhWX2c0HwB2w48NE9TcPFDPs8E4OD0vS4CczFpxE+8bAhtNrRTa2WwMy2B62+iiahxIuvRQyBTbiV8YArpeDkoWfEjw4sEMxv93m86uRKz5Sae/hLgGApejRt0MvZkABPwY3VYJyTDsDPNjXFacuKpePmCnnVjkGfz2jbGvs33l2XkYAsB0ee4uSMWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tZKspeFQ9V5shkamVUXryg9ecJNvzeTWGvhhshwUyYk=; b=DyYVDiN+AvutUwghOlK+ZfNk26DIkdSgpksH+SrpF8y3KmrfjI0WdoFHL322T6PfWiRLQ1O/rfIrzNP5F6n1806l6IJ/LwUKEuSp0ShEOx03xjEWMrOknO4S7WlwRXNiaZ3HhQ92s78JklMQUxeQk0wFoIWMCL+EgSXLD3hXq/kJPPIArbCRBJj27KFMmCJQrI03uqIU9ictBScJGYOR7mOH3uZMM+av5DP/JE2WXYg11qDgthiXaXzi/qusr5BzsqeA8xm2a0ukdo0bggEfz8ODfkOXGt2K5nw6Lkt2HayhaSAhS7uejKB5Igh06hfYfcA9bVadNqdw6KvKsxsalw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tZKspeFQ9V5shkamVUXryg9ecJNvzeTWGvhhshwUyYk=; b=Sp5tzWv6KqURJtdzKScuBbMvhN3cmBGavt/2qRN+A2m5hgQbQLPNwHZCh5zEeXmgm1g8bTPum9qFQFq3KXXt0c96DLtPjgxHfcivq5Rb0fOXK8r03VsPAC6tlnkO4zdrl+4Yb1ODAboJg7fFeK0xkG7AJRusKxUkrbBxr/TtSQE= Authentication-Results: vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:45:51 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:45:51 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 7/7] PCI: layerscape: Add power management support Date: Tue, 27 Oct 2020 15:30:01 +0800 Message-Id: <20201027073001.41808-8-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 27 Oct 2020 07:40:01 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 312aff0c-5a83-4616-4159-08d87a4b85fb X-MS-TrafficTypeDiagnostic: HE1PR0402MB3371: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1850; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 75oiWCKDbTvCCOSTLT3nL12aw4jgOzWgbEWGCQf8KvxRBQiNzpK+sP9yt0ZDSML6dQdOvsCflls4B228oJeGE4UDwxCuHoQREn9Ulum52wm6tTF5AEUvORiksM0K2uEAiXuYQpslFdVjRqvYg/j81dduGfRWS8kdyl87K7eQ5aDwpfKC9s1jlYZEldqsEk1xptQjJGFvFJsXsqb4i8i3Omql9T+n/ZIJg4r8fcw0W7KdR8tDwRXYc/hmVy0ZS0OP7cqtJEWttU4PLZtoIgZnVnlseeUynshrlnkIMtZ3LeKm3UllyX5+WLPPkWUnfEohsJLUrU23QKRHCAmvyfTvCsnKOM9AX9Np2Y1RrnpUeyzrbvOSlymApn0q+eNP3rvsSZZTzdITgyzBhjG5rpZ69w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:HE1PR0402MB3371.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(376002)(346002)(396003)(366004)(136003)(39860400002)(6486002)(6512007)(478600001)(83380400001)(36756003)(956004)(2616005)(69590400008)(66946007)(66556008)(66476007)(186003)(30864003)(2906002)(8936002)(1076003)(8676002)(86362001)(5660300002)(6506007)(26005)(52116002)(316002)(16526019)(4326008)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: hfVyaj588kjOpp3igr0Jc69ZURLEf7e+FyokDsLwuO7ITXuWpwRp4SYVYGLv9nrPHWhK2YRZGXOnNbTqM6uT3usJATwDPmvC+8kRBZuwwfllUogUhpfJ6ubWIkfSc7NcOPrKJFcg8XVULDALB08sZWX500jqPIEez1almijyXTF4JAEJwV8vQ96IVB4US7BkUbV5TyWiu4WKzoV1PuD5lhYWkyjDn9QFLhkkNLbA4RPx1DrUDZlhtRihM00BaGgd6Jm4tPMFc/yK7VO6blXFiGObjBAFIP13u04zWctrEa52LpZfBmHjIhhse005sFf8HsiujqM75U+qiyBr/fBe9mpXdu17NRjOQtSfLBlpOLqocLUFHbkWuoSZNgsNAWLnKy8GP6ou+qb4mw8YlC8TNLt460JmhLkAhFUVibdJDBCT8REk9OHn1OxkV9PLSxRA0cvfedd/E9tE1fy4YCasrhd+Ol8hG9ZKErED9rjeXdLo07Z4IxpJ9dRnPX0RRNbpTeIuuBh6aBLtGbuU7PshSDMTVHbKeADcoS9XcXGiEyHUqi9KJ7os1f6u09uiE/GEkCON+AbnP7LLT8rdg8m66NmcNK98jm0CkTVHgk+IJA0KRAsY9u2bKKAYFbNg5J8E2tJwULFnnxDJQ9lUMBY8Kw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 312aff0c-5a83-4616-4159-08d87a4b85fb X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:40:06.6524 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3GvC8NRqYBroi2ZWoweI1YkiuvYeyRO/Nj/Qd1Umu9G+kO2IwYmP9IXeCJWeWvakS5SIi5PgP210q7X5HtsPRQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally put the PCIe controller into D3 state after the L2/L3 ready state transition process completion. Signed-off-by: Hou Zhiqiang --- V2: - Change to use the common defines to access the RC configuration registers. drivers/pci/controller/dwc/pci-layerscape.c | 380 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 379 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index be404c16bcbe..9886eaead593 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -3,13 +3,16 @@ * PCIe host controller driver for Freescale Layerscape SoCs * * Copyright (C) 2014 Freescale Semiconductor. + * Copyright 2020 NXP * * Author: Minghuan Lian */ +#include #include #include #include +#include #include #include #include @@ -27,17 +30,60 @@ #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ +/* PF Message Command Register */ +#define LS_PCIE_PF_MCR 0x2c +#define PF_MCR_PTOMR BIT(0) +#define PF_MCR_EXL2S BIT(1) + +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 +#define LS_PCIE_IS_L2(v) \ + (((v) & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L2) + +struct ls_pcie; + +struct ls_pcie_host_pm_ops { + int (*pm_init)(struct ls_pcie *pcie); + void (*send_turn_off_message)(struct ls_pcie *pcie); + void (*exit_from_l2)(struct ls_pcie *pcie); +}; + struct ls_pcie_drvdata { + const u32 pf_off; + const u32 lut_off; const struct dw_pcie_host_ops *ops; + const struct ls_pcie_host_pm_ops *pm_ops; }; struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; + void __iomem *pf_base; + void __iomem *lut_base; + bool big_endian; + bool ep_presence; + bool pm_support; + struct regmap *scfg; + int index; }; +#define ls_pcie_lut_readl_addr(addr) ls_pcie_lut_readl(pcie, addr) +#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -86,6 +132,210 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->lut_base + off); + + return ioread32(pcie->lut_base + off); +} + +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + return iowrite32be(val, pcie->lut_base + off); + + return iowrite32(val, pcie->lut_base + off); + +} + +static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->pf_base + off); + + return ioread32(pcie->pf_base + off); +} + +static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + return iowrite32be(val, pcie->pf_base + off); + + return iowrite32(val, pcie->pf_base + off); + +} + +static void ls_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_PTOMR; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_PTOMR), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll turn off message timeout\n"); +} + +static void ls1021a_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val |= PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); + + mdelay(10); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val &= ~PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); +} + +static void ls1043a_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val |= PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); + + mdelay(10); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val &= ~PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); +} + +static void ls_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_EXL2S; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_EXL2S), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll exit L2 state timeout\n"); +} + +static void ls_pcie_retrain_link(struct ls_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL); + val |= PCI_EXP_LNKCTL_RL; + dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCTL, val); +} + +static void ls1021a_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val |= PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val &= ~PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + mdelay(1); + + ls_pcie_retrain_link(pcie); +} +static void ls1043a_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + mdelay(1); + + ls_pcie_retrain_link(pcie); +} + +static int ls1021a_pcie_pm_init(struct ls_pcie *pcie) +{ + struct device *dev = pcie->pci->dev; + u32 index[2]; + int ret; + + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + ret = PTR_ERR(pcie->scfg); + dev_err(dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return ret; + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", + index, 2); + if (ret) { + pcie->scfg = NULL; + return ret; + } + + pcie->index = index[1]; + + return 0; +} + +static int ls_pcie_pm_init(struct ls_pcie *pcie) +{ + return 0; +} + +static void ls_pcie_set_dstate(struct ls_pcie *pcie, u32 dstate) +{ + struct dw_pcie *pci = pcie->pci; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM); + u32 val; + + val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL); + val &= ~PCI_PM_CTRL_STATE_MASK; + val |= dstate; + dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val); +} + static int ls_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -133,20 +383,52 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp) return 0; } +static struct ls_pcie_host_pm_ops ls1021a_pcie_host_pm_ops = { + .pm_init = &ls1021a_pcie_pm_init, + .send_turn_off_message = &ls1021a_pcie_send_turnoff_msg, + .exit_from_l2 = &ls1021a_pcie_exit_from_l2, +}; + +static struct ls_pcie_host_pm_ops ls1043a_pcie_host_pm_ops = { + .pm_init = &ls1021a_pcie_pm_init, + .send_turn_off_message = &ls1043a_pcie_send_turnoff_msg, + .exit_from_l2 = &ls1043a_pcie_exit_from_l2, +}; + +static struct ls_pcie_host_pm_ops ls_pcie_host_pm_ops = { + .pm_init = &ls_pcie_pm_init, + .send_turn_off_message = &ls_pcie_send_turnoff_msg, + .exit_from_l2 = &ls_pcie_exit_from_l2, +}; + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .msi_host_init = ls_pcie_msi_host_init, }; +static const struct ls_pcie_drvdata ls1021a_drvdata = { + .ops = &ls_pcie_host_ops, + .pm_ops = &ls1021a_pcie_host_pm_ops, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .ops = &ls_pcie_host_ops, + .lut_off = 0x10000, + .pm_ops = &ls1043a_pcie_host_pm_ops, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .ops = &ls_pcie_host_ops, + .lut_off = 0x80000, + .pf_off = 0xc0000, + .pm_ops = &ls_pcie_host_pm_ops, }; static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, @@ -170,6 +452,15 @@ static int __init ls_add_pcie_port(struct ls_pcie *pcie) return ret; } + if (dw_pcie_link_up(pci)) { + dev_dbg(pci->dev, "Endpoint is present\n"); + pcie->ep_presence = true; + } + + if (pcie->drvdata->pm_ops && pcie->drvdata->pm_ops->pm_init && + !pcie->drvdata->pm_ops->pm_init(pcie)) + pcie->pm_support = true; + return 0; } @@ -200,6 +491,14 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); + + if (pcie->drvdata->lut_off) + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; + + if (pcie->drvdata->pf_off) + pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; @@ -212,11 +511,88 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } +static bool ls_pcie_pm_check(struct ls_pcie *pcie) +{ + if (!pcie->ep_presence) { + dev_dbg(pcie->pci->dev, "Endpoint isn't present\n"); + return false; + } + + if (!pcie->pm_support) + return false; + + return true; +} + +#ifdef CONFIG_PM_SLEEP +static int ls_pcie_suspend_noirq(struct device *dev) +{ + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + u32 val; + int ret; + + if (!ls_pcie_pm_check(pcie)) + return 0; + + pcie->drvdata->pm_ops->send_turn_off_message(pcie); + + /* 10ms timeout to check L2 ready */ + ret = readl_poll_timeout(pci->dbi_base + PCIE_PORT_DEBUG0, + val, LS_PCIE_IS_L2(val), 100, 10000); + if (ret) { + dev_err(dev, "PCIe link enter L2 timeout! ltssm = 0x%x\n", val); + return ret; + } + + ls_pcie_set_dstate(pcie, 0x3); + + return 0; +} + +static int ls_pcie_resume_noirq(struct device *dev) +{ + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + int ret; + + if (!ls_pcie_pm_check(pcie)) + return 0; + + ls_pcie_set_dstate(pcie, 0x0); + + pcie->drvdata->pm_ops->exit_from_l2(pcie); + + /* delay 10ms to access EP */ + mdelay(10); + + ret = ls_pcie_host_init(&pci->pp); + if (ret) { + dev_err(dev, "ls_pcie_host_init failed! ret = 0x%x\n", ret); + return ret; + } + + ret = dw_pcie_wait_for_link(pci); + if (ret) { + dev_err(dev, "wait link up timeout! ret = 0x%x\n", ret); + return ret; + } + + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +static const struct dev_pm_ops ls_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq, + ls_pcie_resume_noirq) +}; + static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie", .of_match_table = ls_pcie_of_match, .suppress_bind_attrs = true, + .pm = &ls_pcie_pm_ops, }, }; builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9d2f511f13fa..0d863f525057 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -54,6 +54,7 @@ #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +#define PORT_LOGIC_LTSSM_STATE_L2 0x15 #define PCIE_PORT_DEBUG1 0x72C #define PCIE_PORT_DEBUG1_LINK_UP BIT(4) #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)