From patchwork Tue Oct 27 20:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C38C4363A for ; Tue, 27 Oct 2020 20:40:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55D5120725 for ; Tue, 27 Oct 2020 20:40:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55D5120725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C45096EC43; Tue, 27 Oct 2020 20:40:03 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 485106EC44 for ; Tue, 27 Oct 2020 20:40:01 +0000 (UTC) IronPort-SDR: s2F8atFYjK0ygE4tMu+NLEN32/WwY3g0KSo0cp5Nx5pUMTBmWNLQDwKn8pkSEajUB/HJbkwAl1 60s9Fz3dR3xQ== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="165569938" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="165569938" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:01 -0700 IronPort-SDR: JCVbxwTlMxFLYsTsulhTWoaCijsWbV/EnFaOgdxYnrRmjsT8/CXTb6M/YkrR278AMc3nc/qQjQ bF4imXA201Qw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="424526066" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 27 Oct 2020 13:39:59 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:39:58 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:48 +0200 Message-Id: <20201027203955.28032-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Extract intel_crtc_ddb_weight() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä skl_ddb_get_pipe_allocation_limits() doesn't care how the weights for distributing the ddb are caclculated for each pipe. Put that calculation into a separate function so that such mundane details are hidden from view. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 46 ++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0ef01a01ef8d..d14cdedc4ac3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4084,6 +4084,25 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, return slice_mask; } +static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int hdisplay, vdisplay; + + if (!crtc_state->hw.active) + return 0; + + /* + * Watermark/ddb requirement highly depends upon width of the + * framebuffer, So instead of allocating DDB equally among pipes + * distribute DDB based on resolution/width of the display. + */ + drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay); + + return hdisplay; +} + static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, u8 active_pipes); @@ -4098,7 +4117,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct drm_crtc *for_crtc = crtc_state->uapi.crtc; const struct intel_crtc *crtc; - u32 pipe_width = 0, total_width_in_range = 0, width_before_pipe_in_range = 0; + unsigned int pipe_weight = 0, total_weight = 0, weight_before_pipe = 0; enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe; struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(intel_state); @@ -4167,18 +4186,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, */ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size; - /* - * Watermark/ddb requirement highly depends upon width of the - * framebuffer, So instead of allocating DDB equally among pipes - * distribute DDB based on resolution/width of the display. - */ total_slice_mask = dbuf_slice_mask; for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; enum pipe pipe = crtc->pipe; - int hdisplay, vdisplay; - u32 pipe_dbuf_slice_mask; + unsigned int weight; + u8 pipe_dbuf_slice_mask; if (!crtc_state->hw.active) continue; @@ -4205,14 +4217,13 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, if (dbuf_slice_mask != pipe_dbuf_slice_mask) continue; - drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay); - - total_width_in_range += hdisplay; + weight = intel_crtc_ddb_weight(crtc_state); + total_weight += weight; if (pipe < for_pipe) - width_before_pipe_in_range += hdisplay; + weight_before_pipe += weight; else if (pipe == for_pipe) - pipe_width = hdisplay; + pipe_weight = weight; } /* @@ -4227,9 +4238,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return ret; } - start = ddb_range_size * width_before_pipe_in_range / total_width_in_range; - end = ddb_range_size * - (width_before_pipe_in_range + pipe_width) / total_width_in_range; + start = ddb_range_size * weight_before_pipe / total_weight; + end = ddb_range_size * (weight_before_pipe + pipe_weight) / total_weight; alloc->start = offset + start; alloc->end = offset + end; From patchwork Tue Oct 27 20:39:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1328FC4363A for ; Tue, 27 Oct 2020 20:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7716E20725 for ; Tue, 27 Oct 2020 20:40:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7716E20725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECEEF6EC44; Tue, 27 Oct 2020 20:40:06 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CF826EC45 for ; Tue, 27 Oct 2020 20:40:04 +0000 (UTC) IronPort-SDR: UeB6fl1hLOu+BI4PfTc3iFlAoQM4MesmCREy76Eu4VLB4r5mQ/bfNvwSvAl5ys9iphhiFZuVv0 xXwCzTLt74hA== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="252859366" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="252859366" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:04 -0700 IronPort-SDR: nvJVi0jbW+XWxoiW/xURRhfxqrGa/FBTI1KmEmVTqbzHsTwT1rwPhVLsJRoOuiX/zsrIuOv105 Xu2N8x8gAYTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="303883347" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga008.fm.intel.com with SMTP; 27 Oct 2020 13:40:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:01 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:49 +0200 Message-Id: <20201027203955.28032-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/8] drm/i915: Pass the crtc to skl_compute_dbuf_slices() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä skl_compute_dbuf_slices() has no use for the crtc state, so just pass the crtc itself. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d14cdedc4ac3..260d3cf24db3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4103,7 +4103,7 @@ static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_st return hdisplay; } -static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, +static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes); static int @@ -4115,10 +4115,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, { struct drm_atomic_state *state = crtc_state->uapi.state; struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - struct drm_crtc *for_crtc = crtc_state->uapi.crtc; - const struct intel_crtc *crtc; + struct intel_crtc *for_crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc *crtc; unsigned int pipe_weight = 0, total_weight = 0, weight_before_pipe = 0; - enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe; + enum pipe for_pipe = for_crtc->pipe; struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(intel_state); const struct intel_dbuf_state *old_dbuf_state = @@ -4162,14 +4162,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, * * FIXME get rid of this mess */ - *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; + *alloc = to_intel_crtc_state(for_crtc->base.state)->wm.skl.ddb; return 0; } /* * Get allowed DBuf slices for correspondent pipe and platform. */ - dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes); + dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); /* * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2 @@ -4195,8 +4195,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, if (!crtc_state->hw.active) continue; - pipe_dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, - active_pipes); + pipe_dbuf_slice_mask = + skl_compute_dbuf_slices(crtc, active_pipes); /* * According to BSpec pipe can share one dbuf slice with another @@ -4246,7 +4246,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", - for_crtc->base.id, for_crtc->name, + for_crtc->base.base.id, for_crtc->base.name, dbuf_slice_mask, alloc->start, alloc->end, active_pipes); return 0; @@ -4649,10 +4649,8 @@ static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs); } -static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, - u8 active_pipes) +static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; From patchwork Tue Oct 27 20:39:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49ABAC388F9 for ; Tue, 27 Oct 2020 20:40:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E805520725 for ; Tue, 27 Oct 2020 20:40:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E805520725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 663426EC45; Tue, 27 Oct 2020 20:40:11 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id DB4AE6EC45 for ; Tue, 27 Oct 2020 20:40:07 +0000 (UTC) IronPort-SDR: B+8+Ty6fPoG57IT1VIi6n4S++eNhl5QrWr1ldP4iH4UOCDZkxi8djalXWDrfXDAtlaDp9VCxXm TeSSkA7jwhnw== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="185909478" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="185909478" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:07 -0700 IronPort-SDR: XB/iT6NI/HyCniA4QEpbRPK2pS3+6oZlXavI4pfM7+aahkSxx2GxuUpmQMgQKL+1P6uSJoTvUA YEsRmjIlLPlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="323085270" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga006.jf.intel.com with SMTP; 27 Oct 2020 13:40:04 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:04 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:50 +0200 Message-Id: <20201027203955.28032-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/8] drm/i915: Introduce intel_dbuf_slice_size() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Put the code into a function with a descriptive name. Also relocate the code a bit help future work. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 36 +++++++++++++++++++-------------- drivers/gpu/drm/i915/intel_pm.h | 1 - 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 260d3cf24db3..8083785237ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4024,6 +4024,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) return 0; } +static int intel_dbuf_size(struct drm_i915_private *dev_priv) +{ + int ddb_size = INTEL_INFO(dev_priv)->ddb_size; + + drm_WARN_ON(&dev_priv->drm, ddb_size == 0); + + if (INTEL_GEN(dev_priv) < 11) + return ddb_size - 4; /* 4 blocks for bypass path allocation */ + + return ddb_size; +} + +static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) +{ + return intel_dbuf_size(dev_priv) / + INTEL_INFO(dev_priv)->num_supported_dbuf_slices; +} + /* * Calculate initial DBuf slice offset, based on slice size * and mask(i.e if slice size is 1024 and second slice is enabled @@ -4045,22 +4063,11 @@ icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask, return offset; } -u16 intel_get_ddb_size(struct drm_i915_private *dev_priv) -{ - u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size; - drm_WARN_ON(&dev_priv->drm, ddb_size == 0); - - if (INTEL_GEN(dev_priv) < 11) - return ddb_size - 4; /* 4 blocks for bypass path allocation */ - - return ddb_size; -} - u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry) { u32 slice_mask = 0; - u16 ddb_size = intel_get_ddb_size(dev_priv); + u16 ddb_size = intel_dbuf_size(dev_priv); u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; u16 slice_size = ddb_size / num_supported_slices; u16 start_slice; @@ -4142,9 +4149,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return 0; } - ddb_size = intel_get_ddb_size(dev_priv); - - slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + ddb_size = intel_dbuf_size(dev_priv); + slice_size = intel_dbuf_slice_size(dev_priv); /* * If the state doesn't change the active CRTC's or there is no diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index eab83e251dd5..00910bc01407 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -40,7 +40,6 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_uv); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv); -u16 intel_get_ddb_size(struct drm_i915_private *dev_priv); u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry); void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, From patchwork Tue Oct 27 20:39:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A08D4C388F9 for ; Tue, 27 Oct 2020 20:40:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FAEA20725 for ; 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27 Oct 2020 13:40:10 -0700 IronPort-SDR: y7jyczNxn8OG0JHAogjFh1MUkKY8ERPO/H8q2LF90onYuaZygz8EjuwEM55ungV/iGpobX5hlf 4OhVvsQHFr0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="360889220" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 27 Oct 2020 13:40:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:07 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:51 +0200 Message-Id: <20201027203955.28032-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/8] drm/i915: Introduce skl_ddb_entry_for_slices() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Generalize icl_get_first_dbuf_slice_offset() into something that just gives us the start+end of the dbuf chunk covered by the specified slices as a standard ddb entry. Initial idea was to use it during readout as well, but we shall see. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++---------------------- 1 file changed, 18 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8083785237ba..e4917454ec07 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4042,25 +4042,23 @@ static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) INTEL_INFO(dev_priv)->num_supported_dbuf_slices; } -/* - * Calculate initial DBuf slice offset, based on slice size - * and mask(i.e if slice size is 1024 and second slice is enabled - * offset would be 1024) - */ -static unsigned int -icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask, - u32 slice_size, - u32 ddb_size) +static void +skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask, + struct skl_ddb_entry *ddb) { - unsigned int offset = 0; + int slice_size = intel_dbuf_slice_size(dev_priv); - if (!dbuf_slice_mask) - return 0; + if (!slice_mask) { + ddb->start = 0; + ddb->end = 0; + return; + } - offset = (ffs(dbuf_slice_mask) - 1) * slice_size; + ddb->start = (ffs(slice_mask) - 1) * slice_size; + ddb->end = fls(slice_mask) * slice_size; - WARN_ON(offset >= ddb_size); - return offset; + WARN_ON(ddb->start >= ddb->end); + WARN_ON(ddb->end > intel_dbuf_size(dev_priv)); } u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, @@ -4131,12 +4129,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, const struct intel_dbuf_state *old_dbuf_state = intel_atomic_get_old_dbuf_state(intel_state); u8 active_pipes = new_dbuf_state->active_pipes; - u16 ddb_size; + struct skl_ddb_entry ddb_slices; u32 ddb_range_size; u32 i; u32 dbuf_slice_mask; - u32 offset; - u32 slice_size; u32 total_slice_mask; u32 start, end; int ret; @@ -4149,9 +4145,6 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return 0; } - ddb_size = intel_dbuf_size(dev_priv); - slice_size = intel_dbuf_slice_size(dev_priv); - /* * If the state doesn't change the active CRTC's or there is no * modeset request, then there's no need to recalculate; @@ -4177,20 +4170,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, */ dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); - /* - * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2 - * and slice size is 1024, the offset would be 1024 - */ - offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask, - slice_size, ddb_size); - - /* - * Figure out total size of allowed DBuf slices, which is basically - * a number of allowed slices for that pipe multiplied by slice size. - * Inside of this - * range ddb entries are still allocated in proportion to display width. - */ - ddb_range_size = hweight8(dbuf_slice_mask) * slice_size; + skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); + ddb_range_size = skl_ddb_entry_size(&ddb_slices); total_slice_mask = dbuf_slice_mask; for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { @@ -4247,8 +4228,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, start = ddb_range_size * weight_before_pipe / total_weight; end = ddb_range_size * (weight_before_pipe + pipe_weight) / total_weight; - alloc->start = offset + start; - alloc->end = offset + end; + alloc->start = ddb_slices.start + start; + alloc->end = ddb_slices.start + end; drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", From patchwork Tue Oct 27 20:39:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36613C388F9 for ; Tue, 27 Oct 2020 20:40:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD22720878 for ; Tue, 27 Oct 2020 20:40:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD22720878 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 465116EC46; Tue, 27 Oct 2020 20:40:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBDF36EC46 for ; Tue, 27 Oct 2020 20:40:13 +0000 (UTC) IronPort-SDR: n/LzyEbqsfthvTUuFDaGS66RJRouRVkU114WnMDdaKvOkkXSzlX6j/amYZirr3Q50iBpKgn6l9 /DrNXfDJ5OMQ== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="155938039" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="155938039" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:13 -0700 IronPort-SDR: tc2MMfe8mnNuu6RcHOHk/bdhlUdmC8Ia4231eAOXL18q++3i+QANokrn+ruT93g8BWBGXti/Nr 4bFINEn/QaYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="361527772" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 27 Oct 2020 13:40:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:52 +0200 Message-Id: <20201027203955.28032-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Move pipe ddb entries into the dbuf state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by moving the actual per-pipe ddb entries there. v2: Rebase Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++------- .../drm/i915/display/intel_display_types.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 16 ++++++-------- drivers/gpu/drm/i915/intel_pm.h | 4 ++++ 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f41b6f8b5618..cb2f06fc1123 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15673,6 +15673,10 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state) static void skl_commit_modeset_enables(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; @@ -15687,7 +15691,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* ignore allocations for crtc's that have been turned off. */ if (!needs_modeset(new_crtc_state)) { - entries[pipe] = old_crtc_state->wm.skl.ddb; + entries[pipe] = old_dbuf_state->ddb[pipe]; update_pipes |= BIT(pipe); } else { modeset_pipes |= BIT(pipe); @@ -15711,11 +15715,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + if (skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], entries, I915_MAX_PIPES, pipe)) continue; - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); @@ -15726,8 +15730,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) * then we need to wait for a vblank to pass for the * new ddb allocation to take effect. */ - if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, - &old_crtc_state->wm.skl.ddb) && + if (!skl_ddb_entry_equal(&new_dbuf_state->ddb[pipe], + &old_dbuf_state->ddb[pipe]) && (update_pipes | modeset_pipes)) intel_wait_for_vblank(dev_priv, pipe); } @@ -15778,10 +15782,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, I915_MAX_PIPES, pipe)); + drm_WARN_ON(&dev_priv->drm, + skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], + entries, I915_MAX_PIPES, pipe)); - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f6f0626649e0..a4b5c06a1181 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -757,7 +757,6 @@ struct intel_crtc_wm_state { struct { /* gen9+ only needs 1-step wm programming */ struct skl_pipe_wm optimal; - struct skl_ddb_entry ddb; struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; } skl; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e4917454ec07..2ec48d9522e8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4154,16 +4154,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, * grab _all_ crtc locks, including the one we currently hold. */ if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) { - /* - * alloc may be cleared by clear_intel_crtc_state, - * copy from old state to be sure - * - * FIXME get rid of this mess - */ - *alloc = to_intel_crtc_state(for_crtc->base.state)->wm.skl.ddb; + !dev_priv->wm.distrust_bios_wm) return 0; - } /* * Get allowed DBuf slices for correspondent pipe and platform. @@ -4790,7 +4782,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + struct intel_dbuf_state *dbuf_state = + intel_atomic_get_new_dbuf_state(state); + struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; u16 alloc_size, start = 0; u16 total[I915_MAX_PLANES] = {}; u16 uv_total[I915_MAX_PLANES] = {}; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 00910bc01407..724204bb8442 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -9,8 +9,10 @@ #include #include "display/intel_bw.h" +#include "display/intel_display.h" #include "display/intel_global_state.h" +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -68,6 +70,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); struct intel_dbuf_state { struct intel_global_state base; + struct skl_ddb_entry ddb[I915_MAX_PIPES]; + u8 enabled_slices; u8 active_pipes; }; From patchwork Tue Oct 27 20:39:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F0E1C55178 for ; Tue, 27 Oct 2020 20:40:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C3A520725 for ; Tue, 27 Oct 2020 20:40:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9C3A520725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BF9F6EC49; Tue, 27 Oct 2020 20:40:19 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D8A296EC46 for ; Tue, 27 Oct 2020 20:40:16 +0000 (UTC) IronPort-SDR: p4hLYBI6NxIL9fy90udESbMzAjJksXLRR5IGmpzgGwwWEZjWHEuDM+9XQVDkHW65qNG3LwAhCP /kjSpt+Ydi2Q== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="168288451" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="168288451" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:16 -0700 IronPort-SDR: LXNxA4uXVG1D81LZhVnv9OtULmw+j7MMFvjVUJ7dP9+e4UJEXZ20EMizxFkUfQdBKFzbfE52rI lKDnuo2JcLiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="334520337" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 27 Oct 2020 13:40:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:13 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:53 +0200 Message-Id: <20201027203955.28032-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/8] drm/i915: Extract intel_crtc_dbuf_weights() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the code to calculate the weights used to chunk up the dbuf between pipes. There's still extra stuff in there that shouldn't be there and must be moved out, but that requires a bit more state to be tracked in the dbuf state. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 145 ++++++++++++++++++++------------ 1 file changed, 89 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2ec48d9522e8..bc4d7ce5fd7c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4111,62 +4111,35 @@ static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_st static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes); -static int -skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state, - const u64 total_data_rate, - struct skl_ddb_entry *alloc, /* out */ - int *num_active /* out */) +static int intel_crtc_dbuf_weights(struct intel_atomic_state *state, + struct intel_crtc *for_crtc, + unsigned int *weight_start, + unsigned int *weight_end, + unsigned int *weight_total) { - struct drm_atomic_state *state = crtc_state->uapi.state; - struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - struct intel_crtc *for_crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_crtc *crtc; - unsigned int pipe_weight = 0, total_weight = 0, weight_before_pipe = 0; + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + u8 active_pipes = new_dbuf_state->active_pipes; enum pipe for_pipe = for_crtc->pipe; - struct intel_dbuf_state *new_dbuf_state = - intel_atomic_get_new_dbuf_state(intel_state); - const struct intel_dbuf_state *old_dbuf_state = - intel_atomic_get_old_dbuf_state(intel_state); - u8 active_pipes = new_dbuf_state->active_pipes; - struct skl_ddb_entry ddb_slices; - u32 ddb_range_size; - u32 i; - u32 dbuf_slice_mask; - u32 total_slice_mask; - u32 start, end; - int ret; - - *num_active = hweight8(active_pipes); - - if (!crtc_state->hw.active) { - alloc->start = 0; - alloc->end = 0; - return 0; - } - - /* - * If the state doesn't change the active CRTC's or there is no - * modeset request, then there's no need to recalculate; - * the existing pipe allocation limits should remain unchanged. - * Note that we're safe from racing commits since any racing commit - * that changes the active CRTC list or do modeset would need to - * grab _all_ crtc locks, including the one we currently hold. - */ - if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) - return 0; + const struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + u8 dbuf_slice_mask; + u8 total_slice_mask; + int i, ret; /* * Get allowed DBuf slices for correspondent pipe and platform. */ dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); - - skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); - ddb_range_size = skl_ddb_entry_size(&ddb_slices); - total_slice_mask = dbuf_slice_mask; - for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { + + *weight_start = 0; + *weight_end = 0; + *weight_total = 0; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { enum pipe pipe = crtc->pipe; unsigned int weight; u8 pipe_dbuf_slice_mask; @@ -4197,12 +4170,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, continue; weight = intel_crtc_ddb_weight(crtc_state); - total_weight += weight; + *weight_total += weight; - if (pipe < for_pipe) - weight_before_pipe += weight; - else if (pipe == for_pipe) - pipe_weight = weight; + if (pipe < for_pipe) { + *weight_start += weight; + *weight_end += weight; + } else if (pipe == for_pipe) { + *weight_end += weight; + } } /* @@ -4217,15 +4192,73 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return ret; } - start = ddb_range_size * weight_before_pipe / total_weight; - end = ddb_range_size * (weight_before_pipe + pipe_weight) / total_weight; + return 0; +} + +static int +skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, + const struct intel_crtc_state *crtc_state, + const u64 total_data_rate, + struct skl_ddb_entry *alloc, /* out */ + int *num_active /* out */) +{ + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + unsigned int weight_start, weight_end, weight_total; + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + u8 active_pipes = new_dbuf_state->active_pipes; + struct skl_ddb_entry ddb_slices; + u32 ddb_range_size; + u32 dbuf_slice_mask; + u32 start, end; + int ret; + + *num_active = hweight8(active_pipes); + + if (!crtc_state->hw.active) { + alloc->start = 0; + alloc->end = 0; + return 0; + } + + /* + * If the state doesn't change the active CRTC's or there is no + * modeset request, then there's no need to recalculate; + * the existing pipe allocation limits should remain unchanged. + * Note that we're safe from racing commits since any racing commit + * that changes the active CRTC list or do modeset would need to + * grab _all_ crtc locks, including the one we currently hold. + */ + if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && + !dev_priv->wm.distrust_bios_wm) + return 0; + + /* + * Get allowed DBuf slices for correspondent pipe and platform. + */ + dbuf_slice_mask = skl_compute_dbuf_slices(crtc, active_pipes); + + skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); + ddb_range_size = skl_ddb_entry_size(&ddb_slices); + + ret = intel_crtc_dbuf_weights(state, crtc, + &weight_start, &weight_end, &weight_total); + if (ret) + return ret; + + start = ddb_range_size * weight_start / weight_total; + end = ddb_range_size * weight_end / weight_total; alloc->start = ddb_slices.start + start; alloc->end = ddb_slices.start + end; drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", - for_crtc->base.base.id, for_crtc->base.name, + crtc->base.base.id, crtc->base.name, dbuf_slice_mask, alloc->start, alloc->end, active_pipes); return 0; From patchwork Tue Oct 27 20:39:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE19EC4363A for ; Tue, 27 Oct 2020 20:40:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 760D320725 for ; Tue, 27 Oct 2020 20:40:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 760D320725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C72C6EC4A; Tue, 27 Oct 2020 20:40:22 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65AE66EC4A for ; Tue, 27 Oct 2020 20:40:20 +0000 (UTC) IronPort-SDR: jzw4N79dwN6GwotmAGkHATu0qXPG8tCQq9O7glXTEKXSIe6V/ybQnAyWLwAOKhT7oYyq4h3KMs AQkiru6Koc8w== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="232343819" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="232343819" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:19 -0700 IronPort-SDR: zSW0am3Cx5bhi9zfc5zFXqxSyZgJaPFJAMtF71zYvz87Ltk/zm4p/1neVYQ/XOzONxYl83O2IS W9bf+4SC0Q1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="304017834" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 27 Oct 2020 13:40:17 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:16 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:54 +0200 Message-Id: <20201027203955.28032-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Encapsulate dbuf state handling harder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to make the dbuf state computation less fragile let's make it stand on its own feet by now requiring someone to peek into a crystall ball ahead of time to figure out which pipes need to be added to the state under which potential future conditions. Instead we compute each piece of the state as we go along, and if any fallout occurs that affects more than the current set of pipes we add the affected pipes to the state naturally. That requires that we track a few extra thigns in the global dbuf state: dbuf slices for each pipe, and the weight each pipe has when distributing the same set of slice(s) between multiple pipes. Easy enough. We do need to follow a somewhat careful sequence of computations though as there are several steps involved in cooking up the dbuf state. Thoguh we could avoid some of that by computing more things on demand instead of relying on earlier step of the algorithm to have filled it out. I think the end result is still reasonable as the entire sequence is pretty much consolidated into a single function instead of being spread around all over. The rough sequence is this: 1. calculate active_pipes 2. calculate dbuf slices for every pipe 3. calculate total enabled slices 4. calculate new dbuf weights for any crtc in the state 5. calculate new ddb entry for every pipe based on the sets of slices and weights, and add any affected crtc to the state 6. calculate new plane ddb entries for all crtcs in the state, and add any affected plane to the state so that we'll perform the requisite hw reprogramming And as a nice bonus we get to throw dev_priv->wm.distrust_bios_wm out the window. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 15 - .../drm/i915/display/intel_display_debugfs.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 9 - drivers/gpu/drm/i915/intel_pm.c | 379 +++++++----------- drivers/gpu/drm/i915/intel_pm.h | 2 + 5 files changed, 138 insertions(+), 268 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cb2f06fc1123..48d79caa7a54 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15308,20 +15308,6 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - /* - * distrust_bios_wm will force a full dbuf recomputation - * but the hardware state will only get updated accordingly - * if state->modeset==true. Hence distrust_bios_wm==true && - * state->modeset==false is an invalid combination which - * would cause the hardware and software dbuf state to get - * out of sync. We must prevent that. - * - * FIXME clean up this mess and introduce better - * state tracking for dbuf. - */ - if (dev_priv->wm.distrust_bios_wm) - any_ms = true; - intel_fbc_choose_crtc(dev_priv, state); ret = calc_watermark_data(state); if (ret) @@ -16160,7 +16146,6 @@ static int intel_atomic_commit(struct drm_device *dev, intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); return ret; } - dev_priv->wm.distrust_bios_wm = false; intel_shared_dpll_swap_state(state); intel_atomic_track_fbs(state); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index cfb4c1474982..71ecd32a9df9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1008,7 +1008,6 @@ static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, if (!dev_priv->ipc_enabled && enable) drm_info(&dev_priv->drm, "Enabling IPC: WM will be proper only after next commit\n"); - dev_priv->wm.distrust_bios_wm = true; dev_priv->ipc_enabled = enable; intel_enable_ipc(dev_priv); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bcd8650603d8..ca5fd600cffd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1126,15 +1126,6 @@ struct drm_i915_private { * crtc_state->wm.need_postvbl_update. */ struct mutex wm_mutex; - - /* - * Set during HW readout of watermarks/DDB. Some platforms - * need to know when we're still using BIOS-provided values - * (which we don't fully trust). - * - * FIXME get rid of this. - */ - bool distrust_bios_wm; } wm; struct dram_info { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bc4d7ce5fd7c..9a199eb2d013 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4108,56 +4108,22 @@ static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_st return hdisplay; } -static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, - u8 active_pipes); - -static int intel_crtc_dbuf_weights(struct intel_atomic_state *state, - struct intel_crtc *for_crtc, - unsigned int *weight_start, - unsigned int *weight_end, - unsigned int *weight_total) +static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state, + enum pipe for_pipe, + unsigned int *weight_start, + unsigned int *weight_end, + unsigned int *weight_total) { - const struct intel_dbuf_state *old_dbuf_state = - intel_atomic_get_old_dbuf_state(state); - struct intel_dbuf_state *new_dbuf_state = - intel_atomic_get_new_dbuf_state(state); - u8 active_pipes = new_dbuf_state->active_pipes; - enum pipe for_pipe = for_crtc->pipe; - const struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - u8 dbuf_slice_mask; - u8 total_slice_mask; - int i, ret; - - /* - * Get allowed DBuf slices for correspondent pipe and platform. - */ - dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); - total_slice_mask = dbuf_slice_mask; + struct drm_i915_private *dev_priv = + to_i915(dbuf_state->base.state->base.dev); + enum pipe pipe; *weight_start = 0; *weight_end = 0; *weight_total = 0; - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - enum pipe pipe = crtc->pipe; - unsigned int weight; - u8 pipe_dbuf_slice_mask; - - if (!crtc_state->hw.active) - continue; - - pipe_dbuf_slice_mask = - skl_compute_dbuf_slices(crtc, active_pipes); - - /* - * According to BSpec pipe can share one dbuf slice with another - * pipes or pipe can use multiple dbufs, in both cases we - * account for other pipes only if they have exactly same mask. - * However we need to account how many slices we should enable - * in total. - */ - total_slice_mask |= pipe_dbuf_slice_mask; + for_each_pipe(dev_priv, pipe) { + int weight = dbuf_state->weight[pipe]; /* * Do not account pipes using other slice sets @@ -4166,12 +4132,10 @@ static int intel_crtc_dbuf_weights(struct intel_atomic_state *state, * i.e no partial intersection), so it is enough to check for * equality for now. */ - if (dbuf_slice_mask != pipe_dbuf_slice_mask) + if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) continue; - weight = intel_crtc_ddb_weight(crtc_state); *weight_total += weight; - if (pipe < for_pipe) { *weight_start += weight; *weight_end += weight; @@ -4179,87 +4143,65 @@ static int intel_crtc_dbuf_weights(struct intel_atomic_state *state, *weight_end += weight; } } - - /* - * FIXME: For now we always enable slice S1 as per - * the Bspec display initialization sequence. - */ - new_dbuf_state->enabled_slices = total_slice_mask | BIT(DBUF_S1); - - if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) { - ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); - if (ret) - return ret; - } - - return 0; } static int -skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state, - const u64 total_data_rate, - struct skl_ddb_entry *alloc, /* out */ - int *num_active /* out */) +skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->uapi.state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - unsigned int weight_start, weight_end, weight_total; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + unsigned int weight_total, weight_start, weight_end; const struct intel_dbuf_state *old_dbuf_state = intel_atomic_get_old_dbuf_state(state); struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(state); - u8 active_pipes = new_dbuf_state->active_pipes; + struct intel_crtc_state *crtc_state; struct skl_ddb_entry ddb_slices; + enum pipe pipe = crtc->pipe; u32 ddb_range_size; u32 dbuf_slice_mask; u32 start, end; int ret; - *num_active = hweight8(active_pipes); - - if (!crtc_state->hw.active) { - alloc->start = 0; - alloc->end = 0; - return 0; + if (new_dbuf_state->weight[pipe] == 0) { + new_dbuf_state->ddb[pipe].start = 0; + new_dbuf_state->ddb[pipe].end = 0; + goto out; } - /* - * If the state doesn't change the active CRTC's or there is no - * modeset request, then there's no need to recalculate; - * the existing pipe allocation limits should remain unchanged. - * Note that we're safe from racing commits since any racing commit - * that changes the active CRTC list or do modeset would need to - * grab _all_ crtc locks, including the one we currently hold. - */ - if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) - return 0; - - /* - * Get allowed DBuf slices for correspondent pipe and platform. - */ - dbuf_slice_mask = skl_compute_dbuf_slices(crtc, active_pipes); + dbuf_slice_mask = new_dbuf_state->slices[pipe]; skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); ddb_range_size = skl_ddb_entry_size(&ddb_slices); - ret = intel_crtc_dbuf_weights(state, crtc, - &weight_start, &weight_end, &weight_total); - if (ret) - return ret; + intel_crtc_dbuf_weights(new_dbuf_state, pipe, + &weight_start, &weight_end, &weight_total); start = ddb_range_size * weight_start / weight_total; end = ddb_range_size * weight_end / weight_total; - alloc->start = ddb_slices.start + start; - alloc->end = ddb_slices.start + end; + new_dbuf_state->ddb[pipe].start = ddb_slices.start + start; + new_dbuf_state->ddb[pipe].end = ddb_slices.start + end; + +out: + if (skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], + &new_dbuf_state->ddb[pipe])) + return 0; + + ret = intel_atomic_lock_global_state(&new_dbuf_state->base); + if (ret) + return ret; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); drm_dbg_kms(&dev_priv->drm, - "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", + "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", crtc->base.base.id, crtc->base.name, - dbuf_slice_mask, alloc->start, alloc->end, active_pipes); + old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], + old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, + new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, + old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); return 0; } @@ -4811,59 +4753,32 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state, } static int -skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) +skl_allocate_plane_ddb(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->uapi.state); - struct intel_dbuf_state *dbuf_state = + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_dbuf_state *dbuf_state = intel_atomic_get_new_dbuf_state(state); - struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; + const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; + int num_active = hweight8(dbuf_state->active_pipes); u16 alloc_size, start = 0; u16 total[I915_MAX_PLANES] = {}; u16 uv_total[I915_MAX_PLANES] = {}; u64 total_data_rate; enum plane_id plane_id; - int num_active; u64 plane_data_rate[I915_MAX_PLANES] = {}; u64 uv_plane_data_rate[I915_MAX_PLANES] = {}; u32 blocks; int level; - int ret; /* Clear the partitioning for disabled planes. */ memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); - if (!crtc_state->hw.active) { - struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->uapi.state); - struct intel_dbuf_state *new_dbuf_state = - intel_atomic_get_new_dbuf_state(state); - const struct intel_dbuf_state *old_dbuf_state = - intel_atomic_get_old_dbuf_state(state); - - /* - * FIXME hack to make sure we compute this sensibly when - * turning off all the pipes. Otherwise we leave it at - * whatever we had previously, and then runtime PM will - * mess it up by turning off all but S1. Remove this - * once the dbuf state computation flow becomes sane. - */ - if (new_dbuf_state->active_pipes == 0) { - new_dbuf_state->enabled_slices = BIT(DBUF_S1); - - if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) { - ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); - if (ret) - return ret; - } - } - - alloc->start = alloc->end = 0; + if (!crtc_state->hw.active) return 0; - } if (INTEL_GEN(dev_priv) >= 11) total_data_rate = @@ -4875,12 +4790,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) plane_data_rate, uv_plane_data_rate); - ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, - total_data_rate, - alloc, &num_active); - if (ret) - return ret; - alloc_size = skl_ddb_entry_size(alloc); if (alloc_size == 0) return 0; @@ -5805,39 +5714,114 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, return 0; } +static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state) +{ + struct drm_i915_private *dev_priv = to_i915(dbuf_state->base.state->base.dev); + u8 enabled_slices; + enum pipe pipe; + + /* + * FIXME: For now we always enable slice S1 as per + * the Bspec display initialization sequence. + */ + enabled_slices = BIT(DBUF_S1); + + for_each_pipe(dev_priv, pipe) + enabled_slices |= dbuf_state->slices[pipe]; + + return enabled_slices; +} + static int skl_compute_ddb(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_dbuf_state *old_dbuf_state; - const struct intel_dbuf_state *new_dbuf_state; + struct intel_dbuf_state *new_dbuf_state = NULL; const struct intel_crtc_state *old_crtc_state; struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int ret, i; - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { - ret = skl_allocate_pipe_ddb(new_crtc_state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + new_dbuf_state = intel_atomic_get_dbuf_state(state); + if (IS_ERR(new_dbuf_state)) + return PTR_ERR(new_dbuf_state); + + old_dbuf_state = intel_atomic_get_old_dbuf_state(state); + break; + } + + if (!new_dbuf_state) + return 0; + + new_dbuf_state->active_pipes = + intel_calc_active_pipes(state, old_dbuf_state->active_pipes); + + if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { + ret = intel_atomic_lock_global_state(&new_dbuf_state->base); if (ret) return ret; + } - ret = skl_ddb_add_affected_planes(old_crtc_state, - new_crtc_state); + for_each_intel_crtc(&dev_priv->drm, crtc) { + enum pipe pipe = crtc->pipe; + + new_dbuf_state->slices[pipe] = + skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes); + + if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) + continue; + + ret = intel_atomic_lock_global_state(&new_dbuf_state->base); if (ret) return ret; } - old_dbuf_state = intel_atomic_get_old_dbuf_state(state); - new_dbuf_state = intel_atomic_get_new_dbuf_state(state); + new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); + + if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) { + ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); + if (ret) + return ret; - if (new_dbuf_state && - new_dbuf_state->enabled_slices != old_dbuf_state->enabled_slices) drm_dbg_kms(&dev_priv->drm, "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", old_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices, INTEL_INFO(dev_priv)->num_supported_dbuf_slices); + } + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + enum pipe pipe = crtc->pipe; + + new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); + + if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) + continue; + + ret = intel_atomic_lock_global_state(&new_dbuf_state->base); + if (ret) + return ret; + } + + for_each_intel_crtc(&dev_priv->drm, crtc) { + ret = skl_crtc_allocate_ddb(state, crtc); + if (ret) + return ret; + } + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + ret = skl_allocate_plane_ddb(state, crtc); + if (ret) + return ret; + + ret = skl_ddb_add_affected_planes(old_crtc_state, + new_crtc_state); + if (ret) + return ret; + } return 0; } @@ -5974,83 +5958,6 @@ skl_print_wm_changes(struct intel_atomic_state *state) } } -static int intel_add_affected_pipes(struct intel_atomic_state *state, - u8 pipe_mask) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc *crtc; - - for_each_intel_crtc(&dev_priv->drm, crtc) { - struct intel_crtc_state *crtc_state; - - if ((pipe_mask & BIT(crtc->pipe)) == 0) - continue; - - crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); - } - - return 0; -} - -static int -skl_ddb_add_affected_pipes(struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - int i, ret; - - if (dev_priv->wm.distrust_bios_wm) { - /* - * skl_ddb_get_pipe_allocation_limits() currently requires - * all active pipes to be included in the state so that - * it can redistribute the dbuf among them, and it really - * wants to recompute things when distrust_bios_wm is set - * so we add all the pipes to the state. - */ - ret = intel_add_affected_pipes(state, ~0); - if (ret) - return ret; - } - - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_dbuf_state *new_dbuf_state; - const struct intel_dbuf_state *old_dbuf_state; - - new_dbuf_state = intel_atomic_get_dbuf_state(state); - if (IS_ERR(new_dbuf_state)) - return PTR_ERR(new_dbuf_state); - - old_dbuf_state = intel_atomic_get_old_dbuf_state(state); - - new_dbuf_state->active_pipes = - intel_calc_active_pipes(state, old_dbuf_state->active_pipes); - - if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes) - break; - - ret = intel_atomic_lock_global_state(&new_dbuf_state->base); - if (ret) - return ret; - - /* - * skl_ddb_get_pipe_allocation_limits() currently requires - * all active pipes to be included in the state so that - * it can redistribute the dbuf among them. - */ - ret = intel_add_affected_pipes(state, - new_dbuf_state->active_pipes); - if (ret) - return ret; - - break; - } - - return 0; -} - /* * To make sure the cursor watermark registers are always consistent * with our computed state the following scenario needs special @@ -6119,15 +6026,6 @@ skl_compute_wm(struct intel_atomic_state *state) struct intel_crtc_state *old_crtc_state; int ret, i; - ret = skl_ddb_add_affected_pipes(state); - if (ret) - return ret; - - /* - * Calculate WM's for all pipes that are part of this transaction. - * Note that skl_ddb_add_affected_pipes may have added more CRTC's that - * weren't otherwise being modified if pipe allocations had to change. - */ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { ret = skl_build_pipe_wm(new_crtc_state); @@ -6296,11 +6194,6 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); } - - if (dev_priv->active_pipes) { - /* Fully recompute DDB on first atomic commit */ - dev_priv->wm.distrust_bios_wm = true; - } } static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 724204bb8442..97550cf0b6df 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -71,6 +71,8 @@ struct intel_dbuf_state { struct intel_global_state base; struct skl_ddb_entry ddb[I915_MAX_PIPES]; + unsigned int weight[I915_MAX_PIPES]; + u8 slices[I915_MAX_PIPES]; u8 enabled_slices; u8 active_pipes; From patchwork Tue Oct 27 20:39:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 11861859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD1BC55178 for ; Tue, 27 Oct 2020 20:40:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9894520725 for ; Tue, 27 Oct 2020 20:40:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9894520725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 306136EC4C; Tue, 27 Oct 2020 20:40:25 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 92F9D6EC4D for ; Tue, 27 Oct 2020 20:40:23 +0000 (UTC) IronPort-SDR: B+PvzksoNvqM18cFz1usIZuabdaFpm3GsXAh3BvYwAyhimPZj85swYD6ejxcZIZlOs6BnRt8GC oCj51VO2Utew== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="155128647" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="155128647" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:22 -0700 IronPort-SDR: /SFMOKKvG5jeWHiZ+2QviUAw0ynmQzUUA6UtAEmJLk2YpasmxZH8g/o5laydFPVtEeajIGhrIS nLYJAQ03hFrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="355677949" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 27 Oct 2020 13:40:20 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:19 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:55 +0200 Message-Id: <20201027203955.28032-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 8/8] drm/i915: Do a bit more initial readout for dbuf X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Readout the dbuf related stuff during driver init/resume and stick it into our dbuf state. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 -- drivers/gpu/drm/i915/intel_pm.c | 48 +++++++++++++++++++- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 48d79caa7a54..63057f966a4c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17883,14 +17883,10 @@ void intel_modeset_init_hw(struct drm_i915_private *i915) { struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); - struct intel_dbuf_state *dbuf_state = - to_intel_dbuf_state(i915->dbuf.obj.state); intel_update_cdclk(i915); intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; - - dbuf_state->enabled_slices = i915->dbuf.enabled_slices; } static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9a199eb2d013..e079043ad3e8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5670,6 +5670,18 @@ static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, return a->start < b->end && b->start < a->end; } +static void skl_ddb_entry_union(struct skl_ddb_entry *a, + const struct skl_ddb_entry *b) +{ + if (a->end && b->end) { + a->start = min(a->start, b->start); + a->end = max(a->end, b->end); + } else if (b->end) { + a->start = b->start; + a->end = b->end; + } +} + bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, const struct skl_ddb_entry *entries, int num_entries, int ignore_idx) @@ -6186,14 +6198,46 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) { + struct intel_dbuf_state *dbuf_state = + to_intel_dbuf_state(dev_priv->dbuf.obj.state); struct intel_crtc *crtc; - struct intel_crtc_state *crtc_state; for_each_intel_crtc(&dev_priv->drm, crtc) { - crtc_state = to_intel_crtc_state(crtc->base.state); + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + enum pipe pipe = crtc->pipe; + enum plane_id plane_id; skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); + + memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); + + for_each_plane_id_on_crtc(crtc, plane_id) { + struct skl_ddb_entry *ddb_y = + &crtc_state->wm.skl.plane_ddb_y[plane_id]; + struct skl_ddb_entry *ddb_uv = + &crtc_state->wm.skl.plane_ddb_uv[plane_id]; + + skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe, + plane_id, ddb_y, ddb_uv); + + skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); + skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv); + } + + dbuf_state->slices[pipe] = + skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes); + + dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); + + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", + crtc->base.base.id, crtc->base.name, + dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, + dbuf_state->ddb[pipe].end, dbuf_state->active_pipes); } + + dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices; } static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)