From patchwork Tue Oct 27 21:51:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D37C388F9 for ; Tue, 27 Oct 2020 21:52:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB0E42222C for ; Tue, 27 Oct 2020 21:52:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pIEXrqKG"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="wfeRS9GZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB0E42222C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5LTx+iLtdGXMmpSEhZtCF+tYNbCiBLJFO+P2IMhOQ2U=; b=pIEXrqKGpOQTzZpG6kFtjLSfi MvWD/VVfF6flb+eKoEYyAqFVAZmgMFL7x4LpeR9kbWN13xvzf+6LcliV+jjMZIKCr5gXVGs0vYuLr GH/9ZeYzR1ESh2Vcjn3zvQDZ7mtVRoNr7BLb7runmxLm4T5+JoUbc2eo2Uy7Bc4rQV0XKuAq0xSSv z+3A/kUnHeZJOh9FFlrbk+lFDvjToR9VZU/Auq7oRoazwUgBjwo1c6pXkWPqX3icNqFt8TpPFR0Ph wGvZzXZmIW7idhQLpULKfE1Eca9vwVhA+jQCpuyNHrIXZXF03mvPHZQlVky57O/kNBRwLD/Q5eJeN 2L5CT7M5Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsS-0002PC-5C; Tue, 27 Oct 2020 21:51:36 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsJ-0002MC-Eu for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 21:51:28 +0000 Received: from localhost.localdomain (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BC0782222C; Tue, 27 Oct 2020 21:51:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835486; bh=Esg3EpfECFhTL7iOJ/NxBoUqAj8LX4q6jNym7Nfr4Mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wfeRS9GZUSTaVPY8xaTFMD+96LQjW11D886hCcuB950L8h1O6rLEFyxbmF3qmBMDH fY5AkV1PLoGFmxSL0vYvc/koVgyRjyQ+5H9cKcnW0fMncOmrrFadiXejDkpvPIOMsP ZDHgILA2q3Xn13YJeeBvUV0Nm57BXbl1oyKU12uw= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/6] KVM: arm64: Handle Asymmetric AArch32 systems Date: Tue, 27 Oct 2020 21:51:13 +0000 Message-Id: <20201027215118.27003-2-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175127_604129_0844357E X-CRM114-Status: GOOD ( 19.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , James Morse , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Qais Yousef On a system without uniform support for AArch32 at EL0, it is possible for the guest to force run AArch32 at EL0 and potentially cause an illegal exception if running on a core without AArch32. Add an extra check so that if we catch the guest doing that, then we prevent it from running again by resetting vcpu->arch.target and return ARM_EXCEPTION_IL. We try to catch this misbehaviour as early as possible and not rely on an illegal exception occuring to signal the problem. Attempting to run a 32bit app in the guest will produce an error from QEMU if the guest exits while running in AArch32 EL0. Tested on Juno by instrumenting the host to fake asym aarch32 and instrumenting KVM to make the asymmetry visible to the guest. Cc: James Morse Cc: Marc Zyngier Signed-off-by: Qais Yousef [will: Incorporated feedback from Marc] Link: https://lore.kernel.org/r/20201021104611.2744565-2-qais.yousef@arm.com Signed-off-by: Will Deacon --- arch/arm64/kvm/arm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index f56122eedffc..a3b32df1afb0 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -808,6 +808,25 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) preempt_enable(); + /* + * The ARMv8 architecture doesn't give the hypervisor + * a mechanism to prevent a guest from dropping to AArch32 EL0 + * if implemented by the CPU. If we spot the guest in such + * state and that we decided it wasn't supposed to do so (like + * with the asymmetric AArch32 case), return to userspace with + * a fatal error. + */ + if (!system_supports_32bit_el0() && vcpu_mode_is_32bit(vcpu)) { + /* + * As we have caught the guest red-handed, decide that + * it isn't fit for purpose anymore by making the vcpu + * invalid. The VMM can try and fix it by issuing a + * KVM_ARM_VCPU_INIT if it really wants to. + */ + vcpu->arch.target = -1; + ret = ARM_EXCEPTION_IL; + } + ret = handle_exit(vcpu, ret); } From patchwork Tue Oct 27 21:51:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A117C4363A for ; Tue, 27 Oct 2020 21:53:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF49920759 for ; Tue, 27 Oct 2020 21:53:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="IVsuz29V"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="0mMOxqkq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF49920759 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=N35Y0rteVYILjK4/Q2PGfMuyxXX2Dfr09sPOzaLrkfg=; b=IVsuz29VRFryNLzkkau0nvv/h 88lhmUfXX0TXLOh/xBy+Zo+kvKAJ0AvIU0WjvKSwkV39subOsJ9vRHHM2C0QSBNmhdFqUAQMeD1Qv bLxzmOCwWw42sEg17yqrsQVnHYPcJAsjnL+crA4zWDXydwMWltl4QRy+tFCMSuMQ6JysDmB75rQFt y/a+kyWI5bUClNBYcH4XitRz9fr+k49ub++/n3n/+A0ACn1/WftJBMOxqwUqXZg+LSi+2FCYeLHtV 1oaoJQ7RV9dkNRnKZJMrVNkZ7uCo+ir6lUqD/h8MyQdTw/me5t5N75OE3ajRna/S069tLJnPB9Ybm gjDxUbO0A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsX-0002QQ-72; Tue, 27 Oct 2020 21:51:41 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsL-0002N7-Uv for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 21:51:31 +0000 Received: from localhost.localdomain (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4C6512223C; Tue, 27 Oct 2020 21:51:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835489; bh=GAUTwFhizKAw0Z9lmj6Hxux2DjN4LfuQzDBctcI63WI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0mMOxqkq/GUDbYIwo0xjmXYRUaxpVGR9HvrBC+6y58kagcN3uPDfrh0WpegeVNStj AMPFd4AwowY2CUbeu33+hYtnS0Utv1gdyjaYS1xRmNgFeKJpWCETAm2HIjOgozQ48F /lOaSIpsTdUK/kAMY0WJzHH6dOct60Qc31iCFoyY= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Date: Tue, 27 Oct 2020 21:51:14 +0000 Message-Id: <20201027215118.27003-3-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175130_204940_07B49A13 X-CRM114-Status: GOOD ( 21.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When confronted with a mixture of CPUs, some of which support 32-bit applications and others which don't, we quite sensibly treat the system as 64-bit only for userspace and prevent execve() of 32-bit binaries. Unfortunately, some crazy folks have decided to build systems like this with the intention of running 32-bit applications, so relax our sanitisation logic to continue to advertise 32-bit support to userspace on these systems and track the real 32-bit capable cores in a cpumask instead. For now, the default behaviour remains but will be tied to a command-line option in a later patch. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cpufeature.h | 3 ++ arch/arm64/kernel/cpufeature.c | 54 +++++++++++++++++++++++++++-- 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f7e7144af174..aeab42cb917e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -582,6 +582,9 @@ static inline bool cpu_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); } +const struct cpumask *system_32bit_el0_cpumask(void); +bool system_has_mismatched_32bit_el0(void); + static inline bool system_supports_32bit_el0(void) { return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index dcc165b3fc04..2e2219cbd54c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -104,6 +104,10 @@ DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); bool arm64_use_ng_mappings = false; EXPORT_SYMBOL(arm64_use_ng_mappings); +static bool __read_mostly __allow_mismatched_32bit_el0; +/* Mask of CPUs supporting 32-bit EL0. Only valid if we allow a mismatch */ +static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; + /* * Flag to indicate if we have computed the system wide * capabilities based on the boot time active CPUs. This @@ -942,8 +946,11 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, * as the register values may be UNKNOWN and we're not going to be * using them for anything. */ - if (!id_aa64pfr0_32bit_el0(pfr0)) - return taint; + if (!id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) + return 0; + + if (__allow_mismatched_32bit_el0) + cpumask_set_cpu(cpu, cpu_32bit_el0_mask); /* * If we don't have AArch32 at EL1, then relax the strictness of @@ -1193,6 +1200,47 @@ has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) return feature_matches(val, entry); } +static int __init init_32bit_el0_mask(void) +{ + if (!__allow_mismatched_32bit_el0) + return 0; + + if (!alloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) + return -ENOMEM; + + if (id_aa64pfr0_32bit_el0(per_cpu(cpu_data, 0).reg_id_aa64pfr0)) + cpumask_set_cpu(0, cpu_32bit_el0_mask); + + return 0; +} +early_initcall(init_32bit_el0_mask); + +const struct cpumask *system_32bit_el0_cpumask(void) +{ + if (__allow_mismatched_32bit_el0) + return cpu_32bit_el0_mask; + + return system_supports_32bit_el0() ? cpu_present_mask : cpu_none_mask; +} + +bool system_has_mismatched_32bit_el0(void) +{ + u64 reg; + unsigned int fld; + + if (!__allow_mismatched_32bit_el0) + return false; + + reg = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64PFR0_EL0_SHIFT); + return fld == ID_AA64PFR0_EL0_64BIT_ONLY; +} + +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) +{ + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; +} + static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) { bool has_sre; @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, .type = ARM64_CPUCAP_SYSTEM_FEATURE, - .matches = has_cpuid_feature, + .matches = has_32bit_el0, .sys_reg = SYS_ID_AA64PFR0_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64PFR0_EL0_SHIFT, From patchwork Tue Oct 27 21:51:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD72C4363A for ; Tue, 27 Oct 2020 21:52:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFAAF207E8 for ; Tue, 27 Oct 2020 21:52:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="NiuDCZq5"; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsa-0002Rp-QE; Tue, 27 Oct 2020 21:51:44 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXWsO-0002Np-6s for linux-arm-kernel@lists.infradead.org; Tue, 27 Oct 2020 21:51:33 +0000 Received: from localhost.localdomain (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B28282222C; Tue, 27 Oct 2020 21:51:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835491; bh=c7zF3MN4y4ZK0euObvy+1HVIOy0osdnoCeXghTN/qeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cs8xjkwYMhG1Qbc9ORqEL9fFj8Ar5rtdS8yziDGSJb6k7+xWOrU4yAdHabSoVSg88 Ivjkq0sCRYqfRctT1ZOtPpLbMj1+y4QtdOAwA/jEAdmeEGinzwTVmv7dhfziUya4eP g3LyBdRM3zWiFk75vMwFzAUQjydR58S4pkIVqmEw= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/6] KVM: arm64: Kill 32-bit vCPUs on systems with mismatched EL0 support Date: Tue, 27 Oct 2020 21:51:15 +0000 Message-Id: <20201027215118.27003-4-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175132_386365_87FBF613 X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If a vCPU tries to run 32-bit code on a system with mismatched support at EL0, then we should kill it. Signed-off-by: Will Deacon --- arch/arm64/kvm/arm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index a3b32df1afb0..7150dd996e1d 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -633,6 +633,14 @@ static void check_vcpu_requests(struct kvm_vcpu *vcpu) } } +static bool vcpu_mode_is_bad_32bit(struct kvm_vcpu *vcpu) +{ + if (likely(!vcpu_mode_is_32bit(vcpu))) + return false; + + return !system_supports_32bit_el0() || system_has_mismatched_32bit_el0(); +} + /** * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code * @vcpu: The VCPU pointer @@ -816,7 +824,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) * with the asymmetric AArch32 case), return to userspace with * a fatal error. */ - if (!system_supports_32bit_el0() && vcpu_mode_is_32bit(vcpu)) { + if (vcpu_mode_is_bad_32bit(vcpu)) { /* * As we have caught the guest red-handed, decide that * it isn't fit for purpose anymore by making the vcpu From patchwork Tue Oct 27 21:51:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B74DEC4363A for ; Tue, 27 Oct 2020 21:52:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F70620725 for ; Tue, 27 Oct 2020 21:52:25 +0000 (UTC) Authentication-Results: mail.kernel.org; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835493; bh=nU3hgM26iNL5yzEFEmr4JyXLx49XcFjrIm2/XNRCwTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h1p/YiTfKA4I1zPlc/xkUOdmqbPbFdOBKAKnCXJRvdNzzI4QZnt3w8WKPMks6DGE1 VYdSfzmRB+n1HaAn8L6ThtVPP4NCyCciXCgHmCz/MMQq0jTVRLdkMyXuXhs1m3hMfc 2o713+d9YtU3ETrrCJWaR5RxubBBoX0yULA/6eRU= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] arm64: Kill 32-bit applications scheduled on 64-bit-only CPUs Date: Tue, 27 Oct 2020 21:51:16 +0000 Message-Id: <20201027215118.27003-5-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175134_866014_2B59A621 X-CRM114-Status: GOOD ( 19.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Scheduling a 32-bit application on a 64-bit-only CPU is a bad idea. Ensure that 32-bit applications always take the slow-path when returning to userspace on a system with mismatched support at EL0, so that we can avoid trying to run on a 64-bit-only CPU and force a SIGKILL instead. Signed-off-by: Will Deacon --- arch/arm64/kernel/process.c | 21 ++++++++++++++++++++- arch/arm64/kernel/signal.c | 26 ++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 4784011cecac..c45b5f9dd66b 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -542,6 +542,17 @@ static void erratum_1418040_thread_switch(struct task_struct *prev, write_sysreg(val, cntkctl_el1); } +static void compat_thread_switch(struct task_struct *next) +{ + if (!is_compat_thread(task_thread_info(next))) + return; + + if (!system_has_mismatched_32bit_el0()) + return; + + set_tsk_thread_flag(next, TIF_NOTIFY_RESUME); +} + /* * Thread switching. */ @@ -558,6 +569,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, uao_thread_switch(next); ssbs_thread_switch(next); erratum_1418040_thread_switch(prev, next); + compat_thread_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case @@ -620,8 +632,15 @@ unsigned long arch_align_stack(unsigned long sp) */ void arch_setup_new_exec(void) { - current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0; + unsigned long mmflags = 0; + + if (is_compat_task()) { + mmflags = MMCF_AARCH32; + if (system_has_mismatched_32bit_el0()) + set_tsk_thread_flag(current, TIF_NOTIFY_RESUME); + } + current->mm->context.flags = mmflags; ptrauth_thread_init_user(current); if (task_spec_ssb_noexec(current)) { diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index a8184cad8890..bcb6ca2d9a7c 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -911,6 +911,19 @@ static void do_signal(struct pt_regs *regs) restore_saved_sigmask(); } +static bool cpu_affinity_invalid(struct pt_regs *regs) +{ + if (!compat_user_mode(regs)) + return false; + + /* + * We're preemptible, but a reschedule will cause us to check the + * affinity again. + */ + return !cpumask_test_cpu(raw_smp_processor_id(), + system_32bit_el0_cpumask()); +} + asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned long thread_flags) { @@ -948,6 +961,19 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, if (thread_flags & _TIF_NOTIFY_RESUME) { tracehook_notify_resume(regs); rseq_handle_notify_resume(NULL, regs); + + /* + * If we reschedule after checking the affinity + * then we must ensure that TIF_NOTIFY_RESUME + * is set so that we check the affinity again. + * Since tracehook_notify_resume() clears the + * flag, ensure that the compiler doesn't move + * it after the affinity check. + */ + barrier(); + + if (cpu_affinity_invalid(regs)) + force_sig(SIGKILL); } if (thread_flags & _TIF_FOREIGN_FPSTATE) From patchwork Tue Oct 27 21:51:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E26D4C388F9 for ; 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Tue, 27 Oct 2020 21:51:38 +0000 Received: from localhost.localdomain (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5CC1B20829; Tue, 27 Oct 2020 21:51:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835496; bh=7xtHpE+jN4KpE9aM9q3M6jMkm03ttdE7SBSV+UdhCUQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l/U0lij0fRys470mF3hwkMMbzObDJHRKi2dF5fW3IA/jbYB9alNaVzhhx/g/7o6cg bqIbnBe1A7JAGpgFfiIj6b5z/Kv+dMaHVEN4zTs8fceQxp4LBtoXHGGSPMr5p3qD9D f2ECqbFgp1/9T4F9tzZUUfDvDhUzvbLGLBgZ5fTY= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/6] arm64: Advertise CPUs capable of running 32-bit applcations in sysfs Date: Tue, 27 Oct 2020 21:51:17 +0000 Message-Id: <20201027215118.27003-6-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175137_384376_059431C1 X-CRM114-Status: GOOD ( 16.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since 32-bit applications will be killed if they are caught trying to execute on a 64-bit-only CPU in a mismatched system, advertise the set of 32-bit capable CPUs to userspace in sysfs. Signed-off-by: Will Deacon --- .../ABI/testing/sysfs-devices-system-cpu | 8 ++++++++ arch/arm64/kernel/cpufeature.c | 19 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index b555df825447..19893fb8e870 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -472,6 +472,14 @@ Description: AArch64 CPU registers 'identification' directory exposes the CPU ID registers for identifying model and revision of the CPU. +What: /sys/devices/system/cpu/aarch32_el0 +Date: October 2020 +Contact: Linux ARM Kernel Mailing list +Description: Identifies the subset of CPUs in the system that can execute + AArch32 (32-bit ARM) applications. If absent, then all or none + of the CPUs can execute AArch32 applications and execve() will + behave accordingly. + What: /sys/devices/system/cpu/cpu#/cpu_capacity Date: December 2016 Contact: Linux kernel mailing list diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2e2219cbd54c..9f29d4d1ef7e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -67,6 +67,7 @@ #include #include #include +#include #include #include #include @@ -1236,6 +1237,24 @@ bool system_has_mismatched_32bit_el0(void) return fld == ID_AA64PFR0_EL0_64BIT_ONLY; } +static ssize_t aarch32_el0_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct cpumask *mask = system_32bit_el0_cpumask(); + return sprintf(buf, "%*pbl\n", cpumask_pr_args(mask)); +} +static const struct kobj_attribute aarch32_el0_attr = __ATTR_RO(aarch32_el0); + +static int __init aarch32_el0_sysfs_init(void) +{ + if (!__allow_mismatched_32bit_el0) + return 0; + + return sysfs_create_file(&cpu_subsys.dev_root->kobj, + &aarch32_el0_attr.attr); +} +device_initcall(aarch32_el0_sysfs_init); + static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) { return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; From patchwork Tue Oct 27 21:51:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 11861955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D26C388F9 for ; Tue, 27 Oct 2020 21:52:35 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E0F820756 for ; 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Tue, 27 Oct 2020 21:51:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603835498; bh=Ka4lRA9eCqvV0mOQOAKOwdP3JXDO0/rJj+vKpZ1rCUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cYFhzVnjg1EqcT7oLaMbsjThTi5jopeWooHM/SUSykJR7E/YAYGHKyk+lfPzBCkxB cCP/K9H5xhPonZa32Z4HOPjfWmCtNOoqaT7tLkkUsUF0WYUWjxPu+8RXw68R4JepEW Jd5kaSBSGx0jz4Sp7CbGuy99h2b4hktL2xGYDmXA= From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/6] arm64: Hook up cmdline parameter to allow mismatched 32-bit EL0 Date: Tue, 27 Oct 2020 21:51:18 +0000 Message-Id: <20201027215118.27003-7-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201027215118.27003-1-will@kernel.org> References: <20201027215118.27003-1-will@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_175139_710656_B651D0F4 X-CRM114-Status: GOOD ( 13.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Peter Zijlstra , Catalin Marinas , Qais Yousef , Suren Baghdasaryan , Greg Kroah-Hartman , Will Deacon , Morten Rasmussen Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow systems with mismatched 32-bit support at EL0 to run 32-bit applications based on a new kernel parameter. Signed-off-by: Will Deacon --- Documentation/admin-guide/kernel-parameters.txt | 7 +++++++ arch/arm64/kernel/cpufeature.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 526d65d8573a..1d9021db4d9f 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -289,6 +289,13 @@ do not want to use tracing_snapshot_alloc() as it needs to be done where GFP_KERNEL allocations are allowed. + allow_mismatched_32bit_el0 [ARM64] + Allow execve() of 32-bit applications and setting of the + PER_LINUX32 personality on systems where not all of the + CPUs support 32-bit EL0. When this parameter is present, + the set of CPUs supporting 32-bit EL0 is indicated by + /sys/devices/system/cpu/aarch32_el0. + amd_iommu= [HW,X86-64] Pass parameters to the AMD IOMMU driver in the system. Possible values are: diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9f29d4d1ef7e..ccc08da443ec 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1237,6 +1237,13 @@ bool system_has_mismatched_32bit_el0(void) return fld == ID_AA64PFR0_EL0_64BIT_ONLY; } +static int __init parse_32bit_el0_param(char *str) +{ + __allow_mismatched_32bit_el0 = true; + return 0; +} +early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); + static ssize_t aarch32_el0_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) {