From patchwork Wed Oct 28 19:17:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11862995 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0FF74697 for ; Wed, 28 Oct 2020 19:18:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8801224813 for ; Wed, 28 Oct 2020 19:18:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="D8i9GMqn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8801224813 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kXqy9-0006FI-Dq for patchwork-qemu-devel@patchwork.kernel.org; Wed, 28 Oct 2020 15:18:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kXqwm-0004iJ-UG for qemu-devel@nongnu.org; Wed, 28 Oct 2020 15:17:25 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:53477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kXqwi-0007a0-1l for qemu-devel@nongnu.org; Wed, 28 Oct 2020 15:17:24 -0400 Received: by mail-wm1-x342.google.com with SMTP id t3so343084wmi.3 for ; Wed, 28 Oct 2020 12:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t9TzEw+5lSfoYMnb9djte7cKvh5seLsAJB+iLYPKOyU=; b=D8i9GMqnKB3nl+KwjctvK3niE9NTEDkSCqoj8cZygsHAXXnGv07iTv+v6ce4gT/4WS U0l0ge3oLggS3ck1sOdFclGf5TxKevH7a62Fprwr/YQ4NkFQeHGWtZiWs+hwCJiS8vgd jfFPwGxZzM3ftPbf4DduuO+4hDtj285yTLBshk2UDPFzuqKue96rH577qh+XBLdRJQ2u 3ahnuz//tgWpV/NtcReiVnzinq4ycqjjBot79jMdBpV3U7PoLeKY673cp8jEV+F4TeEp J7Z6FAChvfLfqufTCCrYOoCEGYgGnSR0eSLxOCbbqDM0B3guGRGm8OVkoKwvQuTTK5O1 7AHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t9TzEw+5lSfoYMnb9djte7cKvh5seLsAJB+iLYPKOyU=; b=P9X/X6QDZcZrygIURqH6OKAHj5V00ou7Y4ofqijVfvfM7fNXETEMcSlLg6uoo0A1P9 LVmwfVVekcXBn4DkUFsKtZN0DgK1toRhjhP/YE6v4sCGtPv76bMDyyvH0CEiIa2kcoL8 B54f8dB0aRTUTjjeygM5HR8EYPYXCqlbkaFSot+DpUoMxzaT+FePET/A4tVpktPY8bxL UXPBpVm1nQ3iDkqBmRjNp/G8dR/TsSqBxOGfVKULFQrGQv9XwOzXb8kJVqyKzcTNVA7T EXAzX61j9by5q1jEzVdn1ukLAxWA2CWOzj0M2A0/KLsgppOBJ6yR8kJhK4uM0Abipwuy uiAQ== X-Gm-Message-State: AOAM531bq3kP9B4o5g9xNMP7ddGOVn0fnKWhucSBiGwtV89zcsXrWdbZ 4Q3Cb6Xgsld6DxLmMSi4t3WH2w== X-Google-Smtp-Source: ABdhPJwC53uZKvaNgozpthKdgc/Yk8dYmpNIK8XcZiAr73P2qa2kBzxTeBKwyxma4XvEpCTM8lhUFQ== X-Received: by 2002:a1c:7d49:: with SMTP id y70mr302920wmc.103.1603912636259; Wed, 28 Oct 2020 12:17:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l16sm743953wrx.5.2020.10.28.12.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2020 12:17:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Fix float16 pairwise Neon ops on big-endian hosts Date: Wed, 28 Oct 2020 19:17:11 +0000 Message-Id: <20201028191712.4910-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201028191712.4910-1-peter.maydell@linaro.org> References: <20201028191712.4910-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error meant we were using the H4() address swizzler macro rather than the H2() which is required for 2-byte data. This had no effect on little-endian hosts but meant we put the result data into the destination Dreg in the wrong order on big-endian hosts. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/arm/vec_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index a973454e4f4..30d76d05beb 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1858,10 +1858,10 @@ DO_ABA(gvec_uaba_d, uint64_t) r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \ r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \ \ - d[H4(0)] = r0; \ - d[H4(1)] = r1; \ - d[H4(2)] = r2; \ - d[H4(3)] = r3; \ + d[H2(0)] = r0; \ + d[H2(1)] = r1; \ + d[H2(2)] = r2; \ + d[H2(3)] = r3; \ } DO_NEON_PAIRWISE(neon_padd, add) From patchwork Wed Oct 28 19:17:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11862997 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 714A314C0 for ; Wed, 28 Oct 2020 19:18:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1DCB124813 for ; Wed, 28 Oct 2020 19:18:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="e5Wv2uGm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1DCB124813 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kXqy9-0006Ib-RT for patchwork-qemu-devel@patchwork.kernel.org; Wed, 28 Oct 2020 15:18:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kXqwo-0004id-FY for qemu-devel@nongnu.org; Wed, 28 Oct 2020 15:17:27 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44591) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kXqwi-0007aH-1S for qemu-devel@nongnu.org; Wed, 28 Oct 2020 15:17:26 -0400 Received: by mail-wr1-x444.google.com with SMTP id t9so245914wrq.11 for ; Wed, 28 Oct 2020 12:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U8T+0Mhujpk/WaABXyjdAKtr18CEtiJsfJ83860ndlw=; b=e5Wv2uGmUQoaPNakhRk+lH2Cndq0TGY1ZNc2JfsHuR9bCyrh/u5UhZms9GZpnhBrrC f0B9EK3ToMmKqQjGYX84NcOUJG+FN2NtUA4iH9+CE/chQEOpwPSRcTrbmpNYXgiSRS2Z A+AnhqzxGFFlfh2yurriIzhFKF+9O+M2KbnKldNOgPWN/OW0y1EiMCcs+06+wE7PwFaB Mqmm1f/mbuG8r6OgNd/LFPx7xf66YC72crcKMs8XHqFMZVSrgX4RAY6ntu1ydZGjUSYs rJyMzSeR8vmJSJi7pXv4QppPKl1SV5rGd2vgvXgPPEHK8Ccl2W+Ht5h/HdDNuxPHqJpM 3YsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U8T+0Mhujpk/WaABXyjdAKtr18CEtiJsfJ83860ndlw=; b=oCANLtrN+UxWnuD5cyN114SXlqi1qMIv+Gl19R9B+75L1JiplA4CmzALpCZ3MHbdqB /8DzUnAVU9BsOCI6ng9BdfQZXGB2LQGiLW4sgnSXqyhJNvNwnEKOeCWkpTH85QiTyJaP k7c8rf4SB73uxdxcl/QQjP5wXu6h8AlS3vGE8S6hdsVamv3de4/oe3nbi5BxMeCFBrBg OMWHzw57V6xQ8wh8k6IytJBGsojtgtIMfNwwFf7hdM1zuwWAdyApOwHvPGLuqKTfoQX1 s/XQWNcyiIKUj+x1LVMMBCwB3Vg3BzOT4ctRVwWjQ7JlLllV0u2o2PVtjHZATIrUqNZV 0nJw== X-Gm-Message-State: AOAM533obG/lOdjfFwdg3veTMLh5whA3vodGFELaMUJaauJkbfjn6mLM R7EYtwWik8NEXHuLbrbd6FZDdUnE9zIgCQ== X-Google-Smtp-Source: ABdhPJz/5GHCh+7rQCfI91dSLSrxJfjyLApSHMcoPEIC1Fq7svZiPB3xgJSRQXmO1ji+S1fck1Zw6Q== X-Received: by 2002:a05:6000:1051:: with SMTP id c17mr931493wrx.290.1603912637519; Wed, 28 Oct 2020 12:17:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l16sm743953wrx.5.2020.10.28.12.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2020 12:17:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts Date: Wed, 28 Oct 2020 19:17:12 +0000 Message-Id: <20201028191712.4910-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201028191712.4910-1-peter.maydell@linaro.org> References: <20201028191712.4910-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The helper functions for performing the udot/sdot operations against a scalar were not using an address-swizzling macro when converting the index of the scalar element into a pointer into the vm array. This had no effect on little-endian hosts but meant we generated incorrect results on big-endian hosts. For these insns, the index is indexing over group of 4 8-bit values, so 32 bits per indexed entity, and H4() is therefore what we want. (For Neon the only possible input indexes are 0 and 1.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- I believe that gvec_udot_idx_h and gvec_sdot_idx_h are OK because the index there is over groups of 4*16-bit values, which are 64 bits each. --- target/arm/vec_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 30d76d05beb..0f33127c4c4 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -293,7 +293,7 @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) intptr_t index = simd_data(desc); uint32_t *d = vd; int8_t *n = vn; - int8_t *m_indexed = (int8_t *)vm + index * 4; + int8_t *m_indexed = (int8_t *)vm + H4(index) * 4; /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. * Otherwise opr_sz is a multiple of 16. @@ -324,7 +324,7 @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) intptr_t index = simd_data(desc); uint32_t *d = vd; uint8_t *n = vn; - uint8_t *m_indexed = (uint8_t *)vm + index * 4; + uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4; /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. * Otherwise opr_sz is a multiple of 16.