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Thu, 01 Nov 2018 05:54:12 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id s20sm1914177lfb.51.2018.11.01.05.54.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Nov 2018 05:54:10 -0700 (PDT) From: Linus Walleij To: Russell King , Sudeep Holla , Lorenzo Pieralisi Subject: [PATCH] RFC: ARM: do not handle Spectre V2 on Vexpress CA9 Date: Thu, 1 Nov 2018 13:54:06 +0100 Message-Id: <20181101125406.8874-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181101_055427_738272_C7E9D5D3 X-CRM114-Status: GOOD ( 17.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Since the introduction of the Spectre V2 fixes for ARMv7, especially the BPIALL workaround, the Versatile Express CA9 with its fragile CA9 core tile simply doesn't boot for me anymore. If I turn on low level debugging the boot log stops short at: smp: Bringing up secondary CPUs ... GIC: PPI13 is secure or misconfigured CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 CPU1: Spectre v2: using BPIALL workaround GIC: PPI13 is secure or misconfigured CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 CPU1: Spectre v2: using BPIALL workaround This is pretty much consistent behaviour, I think it managed to boot at one point but these fixes are definately rubbing this CPU the wrong way. This (not elegant) workaround tries to work around it by simply not applying any Spectre v2 fixes on the ARM Vexpress CA9. My other A9 platforms seem to work fine with the fixes, so this appears to be related to the fragility of the core tile on this one reference design, so maybe it would be acceptable to mitigate it like this. I don't know how much this could be related to my particular specimen, it would be great if others with this machine could verify the problem. Signed-off-by: Linus Walleij --- arch/arm/mm/proc-v7-bugs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index 5544b82a2e7a..10b9eedc3b37 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -42,6 +43,11 @@ static void cpu_v7_spectre_init(void) const char *spectre_v2_method = NULL; int cpu = smp_processor_id(); + if (of_machine_is_compatible("arm,vexpress,v2p-ca9")) { + pr_err("CPU%u: Spectre v2: can't handle mitigations, CPU is vulnerable\n", cpu); + return; + } + if (per_cpu(harden_branch_predictor_fn, cpu)) return;