From patchwork Fri Oct 30 21:28:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Levinsky X-Patchwork-Id: 11870859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF5A661C for ; Fri, 30 Oct 2020 21:29:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F55B2224D for ; Fri, 30 Oct 2020 21:29:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="U4sqVR9j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727866AbgJ3V2o (ORCPT ); Fri, 30 Oct 2020 17:28:44 -0400 Received: from mail-dm6nam12on2053.outbound.protection.outlook.com ([40.107.243.53]:32864 "EHLO NAM12-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727853AbgJ3V2o (ORCPT ); Fri, 30 Oct 2020 17:28:44 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=b+YkWtIBAEBRcs+QWeulSKiBR5KHQFEMwco7J+wp0CHMJdxnFcVs57tTtyMoQM0DMyMIq66penglg6R5Ybf9ESjg7bV6S/snWH44zO/k3LinlJW3cT7AjDhjqUlH7Qg2I8s3nG7Jzom7ouT12j0IIoHH/g/U1IjXSLcxeq2c0HUJaopqvHqd0JgbnOLnqbSFNpFIwIVTzdC9w9v21rSGyVQh9eK24oJ5hx6yT+4TlNQIBg1FlTcASa2iWW5Al6aIv1c7tZjaoO/xKL+KzBxOQLlbeoC8B66NS0V4dieZelAA0bvOifTGak66VNjfbET84aoJ1yZIYT/ql42dGEquoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2Vpc2qALYKsniXcacH+wUXo0p8OO7wRYBSl9foF8LDU=; b=hhf/2w8T7EkwykUm8pscKr4nqla5A0yZkt6y/9IcPvLcReu69HZb1VZuCFFZoWwxblA61/dmTJIC1SaneKpSK3/djsRWppSttUY7hFnQ4ZpEmhkUkpkBbq9/vmFJGFS0CfiTkRSbW46AGpO6/efdeDqk7kq0B8tZBndEY/OScYF3w+BqUPX9lKsmEkCANOr2CsfUqzX0az0UGeN6a5TEYQBHINNVLbc+7od2csr7gmAyJ6Pn38FXZaKZ9q0jkJxnE15rqyuC1kdwZYiW6Qm2C6eKV+t2dRvL/FcHT56jkbLIXvsbA7ARRBid21+eHJ7/tdltVXK+bp1bzajPA49p7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2Vpc2qALYKsniXcacH+wUXo0p8OO7wRYBSl9foF8LDU=; b=U4sqVR9jg/5911g17qtFDxLAz//DCZlAVEpVzIHTy8wb96KbiILoM64IzhcVYfidf5jqYN2lZpe/EumDEtGAucQ1PP5qe92pSi5dDZtbHyWagTAVbZ93fSoiA6+SxYO200005t/iSCC98JSCWizgHqRl5IkRBC2AGEIFeOATph4= Received: from DM5PR16CA0014.namprd16.prod.outlook.com (2603:10b6:3:c0::24) by SN6PR02MB5311.namprd02.prod.outlook.com (2603:10b6:805:6a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19; Fri, 30 Oct 2020 21:28:39 +0000 Received: from CY1NAM02FT015.eop-nam02.prod.protection.outlook.com (2603:10b6:3:c0:cafe::9f) by DM5PR16CA0014.outlook.office365.com (2603:10b6:3:c0::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19 via Frontend Transport; Fri, 30 Oct 2020 21:28:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT015.mail.protection.outlook.com (10.152.75.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3520.15 via Frontend Transport; Fri, 30 Oct 2020 21:28:39 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 30 Oct 2020 14:28:34 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 30 Oct 2020 14:28:34 -0700 Envelope-to: stefanos@xilinx.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.2.206] (port=56470 helo=xsjblevinsk50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kYbwo-0003JM-Dc; Fri, 30 Oct 2020 14:28:34 -0700 From: Ben Levinsky To: , CC: , , , , Subject: [PATCH v20 1/5] firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. Date: Fri, 30 Oct 2020 14:28:30 -0700 Message-ID: <20201030212834.18270-2-ben.levinsky@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201030212834.18270-1-ben.levinsky@xilinx.com> References: <20201030212834.18270-1-ben.levinsky@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d2bc0a27-f01c-4d08-a069-08d87d1ac495 X-MS-TrafficTypeDiagnostic: SN6PR02MB5311: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:525; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AQMg5CcBoPe75soAqQpvHdJxdNo9M3G88VtalbWGWE5TpCM+0HI7bjvXLMtVfIq+UB3UFatZL/eJaXTWv6DGeKK9YVoBWYEcNebTsnvqMhDwvQNkuPdSYUzbslpa7idFXA60swLtRTlFvAUy3kokcximeVvwsdXAc6uI7gfo9yzrdo0oFAheafbOdFo0cw6pmlLx2v1hVUjNiPt9/v1VlU81o8w48k4srH6MpYopnH3z8Rn1te4gVLNp92OanyzVm3EtfOUpng10n8mfOBv1TI1cYJ3o0bQwMNyz910qkE/1utqQawbsToQgiB/cwjJKwP+rCuN0lIu2CatAJBKokE1IbxI4FPYTu6kJ7PjGvwx6XPVZA+SK+oRgEt6q2BYYth4HUNNPPsoDYqeRLvRHAlB8c0qBtjVmjxWJ/Gcs7dY= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(39860400002)(376002)(396003)(136003)(346002)(46966005)(186003)(83380400001)(7696005)(8936002)(26005)(54906003)(336012)(7636003)(47076004)(36906005)(356005)(478600001)(8676002)(110136005)(316002)(36756003)(4326008)(2906002)(9786002)(2616005)(426003)(1076003)(82740400003)(70586007)(70206006)(5660300002)(6666004)(44832011)(82310400003)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 21:28:39.2927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2bc0a27-f01c-4d08-a069-08d87d1ac495 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5311 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add ZynqMP firmware ioctl enums for RPU configuration. Signed-off-by: Ben Levinsky --- include/linux/firmware/xlnx-zynqmp.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 5968df82b991..bb347dfe4ba4 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -104,6 +104,10 @@ enum pm_ret_status { }; enum pm_ioctl_id { + IOCTL_GET_RPU_OPER_MODE = 0, + IOCTL_SET_RPU_OPER_MODE = 1, + IOCTL_RPU_BOOT_ADDR_CONFIG = 2, + IOCTL_TCM_COMB_CONFIG = 3, IOCTL_SD_DLL_RESET = 6, IOCTL_SET_SD_TAPDELAY, IOCTL_SET_PLL_FRAC_MODE, @@ -129,6 +133,21 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR, }; +enum rpu_oper_mode { + PM_RPU_MODE_LOCKSTEP = 0, + PM_RPU_MODE_SPLIT = 1, +}; + +enum rpu_boot_mem { + PM_RPU_BOOTMEM_LOVEC = 0, + PM_RPU_BOOTMEM_HIVEC = 1, +}; + +enum rpu_tcm_comb { + PM_RPU_TCM_SPLIT = 0, + PM_RPU_TCM_COMB = 1, +}; + enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE, PM_RESET_ACTION_ASSERT, From patchwork Fri Oct 30 21:28:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Levinsky X-Patchwork-Id: 11870857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DF8292C for ; Fri, 30 Oct 2020 21:28:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 069E42222F for ; Fri, 30 Oct 2020 21:28:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="KzvlPM5r" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727848AbgJ3V2m (ORCPT ); Fri, 30 Oct 2020 17:28:42 -0400 Received: from mail-bn7nam10on2051.outbound.protection.outlook.com ([40.107.92.51]:17569 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727553AbgJ3V2k (ORCPT ); Fri, 30 Oct 2020 17:28:40 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R3WaUd7G0ucjoay8XbYWB/v/dao8c2KSwxXacgs2srSdXGwiXjwnyFJBuH8ZJSS3M1JJmVBu1iVdxLRl/fDPSaTTTaT4TtH6heptstis/du0ukU6KZuVY2c86TVKOJDLWUDAJDOocXgeEeCzg93HkNwWxlQDEsHOBidvnCzVkQJwHuJOxBlC8EsCvJCbm+0SG6OaFRgK3Zim7ofxnPr0wb6D0lBNqtMflBaLud3xW/23/AtwGX1QNlYz1IMyVLrYYtP4i6p3RW7jijuk3yH/GjR1Sen8T1hJtA5IoeIG80Zv2PYwdjUSOpWJmxjYpbSUSyIV69VjJ7dUFf83uClKAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yvj/lkr1NeFpW96h7I8rBBF1Fco7AUaEqsAkifx19DA=; b=HVo0WSZcCHbgO2PGEKWUr7Ehg9nOh5CTzjXlFx8mCbMduOsfQ55e5j7RieYP5ixliQRLIpTuYPZ3cNE2jnwUc3qqb52YWIADCbZG4Bwm/65my2mFRRVqcyPj2fL7vejtdnj6Jd+4XlPNSXgwxIZv7YD3rB19Ai2/9kGBlsJoNMLRWfddZh/mriENJXZDXagtXFmsY1Gt0gyZVW6xkSHkn43oJLRZEzayhx/TYTvFY+juK2qqisdvqXTppROyvCFOXCw8Q9XyLbe4NyTnBYNcZItz3oIsvy7IEXBak42OGI3jZc2uFT8Xg45EAKA9UtG91RQnfXlzhALSPcWje8VoNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yvj/lkr1NeFpW96h7I8rBBF1Fco7AUaEqsAkifx19DA=; b=KzvlPM5riiGmPRR8xFFiPTu4r7oULVGLyCOV0yLMKXwPYM27+ErMS1mn90sa083qN4wAZV7qZW6S32T4KJaDcOlGDZLeXODRNh6zSDe7GkfLUOfiDTUwDTS5n+wanJo7pWdz6yz/C6yOX0T/OJZPUe0TVKPiu/pXcAmKji5IvAU= Received: from SN4PR0701CA0032.namprd07.prod.outlook.com (2603:10b6:803:2d::12) by BL0PR02MB4915.namprd02.prod.outlook.com (2603:10b6:208:5a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18; Fri, 30 Oct 2020 21:28:37 +0000 Received: from SN1NAM02FT064.eop-nam02.prod.protection.outlook.com (2603:10b6:803:2d:cafe::28) by SN4PR0701CA0032.outlook.office365.com (2603:10b6:803:2d::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 21:28:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by SN1NAM02FT064.mail.protection.outlook.com (10.152.72.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3499.20 via Frontend Transport; Fri, 30 Oct 2020 21:28:36 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 30 Oct 2020 14:28:34 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 30 Oct 2020 14:28:34 -0700 Envelope-to: stefanos@xilinx.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.2.206] (port=56470 helo=xsjblevinsk50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kYbwo-0003JM-E3; Fri, 30 Oct 2020 14:28:34 -0700 From: Ben Levinsky To: , CC: , , , , Subject: [PATCH v20 2/5] firmware: xilinx: Add shutdown/wakeup APIs Date: Fri, 30 Oct 2020 14:28:31 -0700 Message-ID: <20201030212834.18270-3-ben.levinsky@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201030212834.18270-1-ben.levinsky@xilinx.com> References: <20201030212834.18270-1-ben.levinsky@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98818510-79e9-4011-4986-08d87d1ac302 X-MS-TrafficTypeDiagnostic: BL0PR02MB4915: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8AdSURafcmMQLV/ROdqJKA9P3BQ1fPmBuaXCshQiBAsD49R+groru2TDGu+RFTKtPBg6gHERIqEITeOwWXo3JAQ85xTVL1Sazyy7aagebGLeuevcZa4j+XRnr13Ro48SapH1fKJGSN7xw8/2xjkkHCr7GlMcgX5/PvDDj2na9QqxZ42pSHSyHrShDb32oaTAsx2JiXy85KaCSTmtLXXHVGKH6D8WS1JQYivGVH37NGPSPlCZoyyE8rId7cKfz3kAe8GkpKinL87X8wmS1YgOdXlI/SJvrKXq3FHE2QGuF5JpZz2baKSfCdcvKGro1J73dZ2RZhnZLc2f4qAOWrFXllihOid2gLREg12rUMmG6jkVuh/beG0gNtchDXPcsoBpz/A/HniGAV0DXPXlcOiJj66r98iXvK5iQWaFIZ3hvrg= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(396003)(346002)(136003)(376002)(39860400002)(46966005)(110136005)(44832011)(336012)(426003)(478600001)(8936002)(7636003)(36906005)(186003)(82310400003)(47076004)(83380400001)(70206006)(70586007)(36756003)(2906002)(356005)(2616005)(54906003)(9786002)(1076003)(7696005)(82740400003)(316002)(4326008)(8676002)(5660300002)(26005)(6666004)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 21:28:36.6454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98818510-79e9-4011-4986-08d87d1ac302 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT064.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB4915 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add shutdown/wakeup a resource eemi operations to shutdown or bringup a resource. Note alignment of args matches convention of other fn's in this file. The reason being that the long fn name results in aligned args that otherwise go over 80 chars so shift right to avoid this Signed-off-by: Ben Levinsky --- drivers/firmware/xilinx/zynqmp.c | 35 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 23 ++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 8d1ff2454e2e..a966ee956573 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -846,6 +846,41 @@ int zynqmp_pm_release_node(const u32 node) } EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); +/** + * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to + * be powered down forcefully + * @node: Node ID of the targeted PU or subsystem + * @ack: Flag to specify whether acknowledge is requested + * + * Return: status, either success or error+reason + */ +int zynqmp_pm_force_pwrdwn(const u32 node, + const enum zynqmp_pm_request_ack ack) +{ + return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, node, ack, 0, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_force_pwrdwn); + +/** + * zynqmp_pm_request_wake - PM call to wake up selected master or subsystem + * @node: Node ID of the master or subsystem + * @set_addr: Specifies whether the address argument is relevant + * @address: Address from which to resume when woken up + * @ack: Flag to specify whether acknowledge requested + * + * Return: status, either success or error+reason + */ +int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack) +{ + /* set_addr flag is encoded into 1st bit of address */ + return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr, + address >> 32, ack, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake); + /** * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves * @node: Node ID of the slave diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index bb347dfe4ba4..6241c5ac51b3 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -12,6 +12,7 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 @@ -64,6 +65,8 @@ enum pm_api_id { PM_GET_API_VERSION = 1, + PM_FORCE_POWERDOWN = 8, + PM_REQUEST_WAKEUP = 10, PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE, @@ -376,6 +379,12 @@ int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); +int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -526,6 +535,20 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; } + +static inline int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Fri Oct 30 21:28:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Levinsky X-Patchwork-Id: 11870861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57F2F61C for ; Fri, 30 Oct 2020 21:29:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 238E42222F for ; Fri, 30 Oct 2020 21:29:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="FGtJMagT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727844AbgJ3V2l (ORCPT ); Fri, 30 Oct 2020 17:28:41 -0400 Received: from mail-eopbgr770044.outbound.protection.outlook.com ([40.107.77.44]:59286 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727727AbgJ3V2k (ORCPT ); Fri, 30 Oct 2020 17:28:40 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XVczcBkR36sfjQOSqcdVYGgA3K8JJJAkaz5KTHE7IUGPByGiJHrqO8K7+gTKKR35XWBbD7ee7zuA9ufcA0z2f1uJjWxLLKIa2+78eCPrpBPzJQl9Zp+5zm7ZLJREp1v4yvs6NRk2BVFvFdecydOHDwIZaQ8I7fTGeNOv7VVH1V4/t7iOsLfQLxL9HEWEyemhmpecK9KUJbPTb7HjhOWcQv5Of/y0lyST2WKBym/NC0lr2iwLZgSgOsgPjvYCXLlhqAUYyA91yJFmMkRWREPoaKXVHf+yns7bR+UbKWexb2vz/kaRk8IaSW+il33k96Egj6FDmVnXO3LJsuYZ9UZrSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r2Do4r27cWJECnVSSikp85Ccuyf/oXixg8hF0D9rUCE=; b=BNGLYK97GyoblgfkRSJNoyeEILvn6t6JzatH89M69WRD2kzvqS3yCcXIHUjDZ6RzH0AxwR0VwOZE5jzFGUNhzsFxWR5lupUtJucjNK2/PqP+xYlmpDFGGb7vb65lGDOyXDbDK7GT1kWZNVqZeppBIKv+UqtqsTp2hZbxvzcV0wqBo8xTF8h9OjvEiJ/0KwcgCkCxF9ZBrIr7Q7/UaUT/HUCzKAlXCW1kou0Xih2daWdaafnm3zx/ooHdLiZVAikovXoi88E09BaJTbfpX7PvJgw8RjguGrHs+0V6ldH6PjviHoDBiinA/Ftwl8qS6wBFpID5m29H6ibne+bjJzds0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=r2Do4r27cWJECnVSSikp85Ccuyf/oXixg8hF0D9rUCE=; b=FGtJMagTkjGkO/nDekg0HKr24fqU5EtYX2dl82j7w7Xb5ByppHZ91Eq/WCrEKpTGEWe/rBQhJyFkX2AfAZf+hICvOH4LKMyBIYlJ9HXU6Mdt5qFJTpxChFpAaT5PAAps3g42f2u43hJKykGidlXTsQcIgYmP9U1u7CJR6bz9SGQ= Received: from SN4PR0701CA0045.namprd07.prod.outlook.com (2603:10b6:803:2d::21) by BYAPR02MB5064.namprd02.prod.outlook.com (2603:10b6:a03:71::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.28; Fri, 30 Oct 2020 21:28:37 +0000 Received: from SN1NAM02FT064.eop-nam02.prod.protection.outlook.com (2603:10b6:803:2d:cafe::35) by SN4PR0701CA0045.outlook.office365.com (2603:10b6:803:2d::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 21:28:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by SN1NAM02FT064.mail.protection.outlook.com (10.152.72.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3499.20 via Frontend Transport; Fri, 30 Oct 2020 21:28:37 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 30 Oct 2020 14:28:34 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 30 Oct 2020 14:28:34 -0700 Envelope-to: stefanos@xilinx.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.2.206] (port=56470 helo=xsjblevinsk50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kYbwo-0003JM-EY; Fri, 30 Oct 2020 14:28:34 -0700 From: Ben Levinsky To: , CC: , , , , Subject: [PATCH v20 3/5] firmware: xilinx: Add RPU configuration APIs Date: Fri, 30 Oct 2020 14:28:32 -0700 Message-ID: <20201030212834.18270-4-ben.levinsky@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201030212834.18270-1-ben.levinsky@xilinx.com> References: <20201030212834.18270-1-ben.levinsky@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f62b2ae4-4349-4342-aff6-08d87d1ac38d X-MS-TrafficTypeDiagnostic: BYAPR02MB5064: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:820; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Mhf3U6zSrjgw/sFN5cmeCGCEkwBkDzcb5EBYn/pib2mChZix9muhYsFnr0WQOcSvkK28wM9yb3+nw68ijxgthu2bMIasajx6oOFzucmo6PFubK361zCeBvIHEoWdFDuE9x+zFgRpiFuOv9G30fyWtMiq0TnGAtt9fETpjzKHYuUHKA7oC5tyUffdbv/y7r3sYGwRSc/dPCP90476kvQQdpjuAAfEkYSZPGJrZjZwzkIiUCHSVegVcVb0D8EFv4hK690QqLf9LDAMOjU4LtIhyULKafkn5OAMDNDen+oI4RZfgZIFnlYmqrwhaCUwS3+fqNpyx5zzDabj/BByI/kPK3ePQK+p1fa8ejjXzEiWTaXqxNevRRnHjHB489nHjkQv0wh4M6yUgRkg0tcRcN1qJu20QANWGwK8oOAljPntboQ= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(39860400002)(376002)(346002)(396003)(136003)(46966005)(82310400003)(26005)(70206006)(70586007)(336012)(83380400001)(47076004)(7696005)(82740400003)(8676002)(8936002)(356005)(9786002)(44832011)(4326008)(5660300002)(54906003)(36756003)(426003)(1076003)(7636003)(316002)(2616005)(478600001)(2906002)(36906005)(186003)(110136005)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 21:28:37.5579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f62b2ae4-4349-4342-aff6-08d87d1ac38d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT064.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5064 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org This patch adds APIs to access to configure RPU and its processor-specific memory. That is query the run-time mode of RPU as either split or lockstep as well as API to set this mode. In addition add APIs to access configuration of the RPUs' tightly coupled memory (TCM). Signed-off-by: Ben Levinsky --- drivers/firmware/xilinx/zynqmp.c | 61 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 18 ++++++++ 2 files changed, 79 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index a966ee956573..b390a00338d0 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -846,6 +846,67 @@ int zynqmp_pm_release_node(const u32 node) } EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); +/** + * zynqmp_pm_get_rpu_mode() - Get RPU mode + * @node_id: Node ID of the device + * @rpu_mode: return by reference value + * either split or lockstep + * + * Return: return 0 on success or error+reason. + * if success, then rpu_mode will be set + * to current rpu mode. + */ +int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_GET_RPU_OPER_MODE, 0, 0, ret_payload); + + /* only set rpu_mode if no error */ + if (ret == XST_PM_SUCCESS) + *rpu_mode = ret_payload[0]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_rpu_mode); + +/** + * zynqmp_pm_set_rpu_mode() - Set RPU mode + * @node_id: Node ID of the device + * @rpu_mode: Argument 1 to requested IOCTL call. either split or lockstep + * + * This function is used to set RPU mode to split or + * lockstep + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_SET_RPU_OPER_MODE, (u32)rpu_mode, + 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode); + +/** + * zynqmp_pm_set_tcm_config - configure TCM + * @tcm_mode: Argument 1 to requested IOCTL call + * either PM_RPU_TCM_COMB or PM_RPU_TCM_SPLIT + * + * This function is used to set RPU mode to split or combined + * + * Return: status: 0 for success, else failure + */ +int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_TCM_COMB_CONFIG, (u32)tcm_mode, 0, + NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config); + /** * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to * be powered down forcefully diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 6241c5ac51b3..79aa2fcbcd54 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -385,6 +385,9 @@ int zynqmp_pm_request_wake(const u32 node, const bool set_addr, const u64 address, const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); +int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1); +int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -549,6 +552,21 @@ static inline int zynqmp_pm_request_wake(const u32 node, { return -ENODEV; } + +static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Fri Oct 30 21:28:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Levinsky X-Patchwork-Id: 11870863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B5FB61C for ; Fri, 30 Oct 2020 21:29:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C396221FA for ; Fri, 30 Oct 2020 21:29:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="Rty4k++v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727660AbgJ3V3F (ORCPT ); Fri, 30 Oct 2020 17:29:05 -0400 Received: from mail-mw2nam10on2079.outbound.protection.outlook.com ([40.107.94.79]:39360 "EHLO NAM10-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726163AbgJ3V2l (ORCPT ); Fri, 30 Oct 2020 17:28:41 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QO8c8x4NbuXT02V0wW26hgoKxKTxfyv3onQv1l359gcLllG7edePW/900dL5dYW7HxWVoVd+DFBjQW5JqhiTYGZaTMCUVPGXRNSxKw7D3BQn6XF17Ks8ZLGIqOLwX84owQC5VAF1HmKMIr99bOHSxCMFUk5BxlFJlNtJFw4CDOsmoGetklY0boWX4qIEwxorNwycU7uPTlQ+Hmi/vZIYxKCmIkoeGhXwes3qS6OHY9vtaxKTaiUuj51nn730xQyY14ptq+V+PB0konvRemjbhaCxqzrDhZd5G8VLukIe3yGEs2yVpYrbQJRAe8pdV43hwageWuDjwEr6dQwyzMZzvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jSBpjDU5RzhFqD03KFq84A3tCc6J+wP0V9a9CDG9kDg=; b=nUaI06GI2E80VJy590kW6mh787ZGQ7s0vYvfL+B6b0N+g6vSaFnKRGTSo8GYt13WQ6CY/h0DxOuWoYs6Y7Mu8R+qc78nHgO+J9nTBYvA505R14fAkJkToiDO/7keC4tpc89WZMwpnoMFwgJEdEUiVGnvEla2wcyY/SSGvD88mWvIIVEgzRzYREMmwvhjDP8t58FItyqRK3PdWyp/yEjFMrrTDZaWX6hkzCwnpk4zdVg9LFEAUX48xp4lWrcmdNC+tflBgJF+A7qfpkvDyJiQkksyLBOhh7dLzJzGKWXz1kK/eL7b+1uEgx+nzk7G8Z/GsK/p3uEuxRsrkmPgoUVAaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jSBpjDU5RzhFqD03KFq84A3tCc6J+wP0V9a9CDG9kDg=; b=Rty4k++vp1mtu/EozRJWylVEr8l51SSXbMi4c2L1k3CI3N7AO0bLMLPrUkrYz4i/XjcIxY06v19/R7ADx7pG358nlaH3uQPjwcxqXN3YFIvBUYbn6uF0AZoOW2Q3GebB+tOD7ZHYfoO8bW48RG7D9bdCfaQJ+wazw28xG6SJrlo= Received: from DM5PR16CA0020.namprd16.prod.outlook.com (2603:10b6:3:c0::30) by MN2PR02MB6640.namprd02.prod.outlook.com (2603:10b6:208:1d0::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.27; Fri, 30 Oct 2020 21:28:38 +0000 Received: from CY1NAM02FT015.eop-nam02.prod.protection.outlook.com (2603:10b6:3:c0:cafe::d) by DM5PR16CA0020.outlook.office365.com (2603:10b6:3:c0::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 21:28:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT015.mail.protection.outlook.com (10.152.75.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3520.15 via Frontend Transport; Fri, 30 Oct 2020 21:28:38 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 30 Oct 2020 14:28:34 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 30 Oct 2020 14:28:34 -0700 Envelope-to: stefanos@xilinx.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.2.206] (port=56470 helo=xsjblevinsk50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kYbwo-0003JM-F0; Fri, 30 Oct 2020 14:28:34 -0700 From: Ben Levinsky To: , CC: , , , , Subject: [PATCH v20 4/5] dt-bindings: remoteproc: Add documentation for ZynqMP R5 rproc bindings Date: Fri, 30 Oct 2020 14:28:33 -0700 Message-ID: <20201030212834.18270-5-ben.levinsky@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201030212834.18270-1-ben.levinsky@xilinx.com> References: <20201030212834.18270-1-ben.levinsky@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 70c9f6a3-11e8-424a-44f0-08d87d1ac3f4 X-MS-TrafficTypeDiagnostic: MN2PR02MB6640: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e8y1IAOHJFxDSJHz4mJJay8DjpqJ9AsnCQIvSVMYNcHLdWj+ubFrKST/3KYXONCtyI7L/mKddbzoOT6b3VOeHiHlHlypKJ13cDX+nCx6daowKjTRfcbVkHARubYSjbp3K82YILtwRKeFLjX2uLy2gIzNBbYATC00askOr7mk/nyGBqEpDseN21TbCaoOO8F/pzffBVMM04NP4LIWO0I5BfHHqVbxn0ss4gcqck5DnP4xXJffdKc+13W3r5+CPuZ5ThvOKx5fgHbjOlexrtKY0PRFAXZNZ+3GvNfcnkRfKSBiAScrC/SFt87Ut34MxmwderWI9UyVLp8/df7CG+BX82PEqjA73q1e9b7IxYS+qV+TPu7XtCWR0i9YZxeiaE4lHLmOx2OwQrWox1YyXrrfv7R+pCnxq0kHH1WftmeB8ZIsUSMvPnpvbu+fJtgd/f7hMDaxHL9l334Nk50iOTjRs1t8prgEKfRBIc3udvf5JDwVCt2jQazrwUJavPikZuDP X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(136003)(346002)(376002)(396003)(39860400002)(46966005)(47076004)(316002)(44832011)(82310400003)(82740400003)(7636003)(2616005)(36756003)(4326008)(54906003)(478600001)(26005)(8676002)(186003)(2906002)(70206006)(356005)(110136005)(8936002)(70586007)(336012)(36906005)(7696005)(5660300002)(83380400001)(426003)(9786002)(1076003)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 21:28:38.2462 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70c9f6a3-11e8-424a-44f0-08d87d1ac3f4 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add binding for ZynqMP R5 OpenAMP. Represent the RPU domain resources in one device node. Each RPU processor is a subnode of the top RPU domain node. Signed-off-by: Jason Wu Signed-off-by: Wendy Liang Signed-off-by: Michal Simek Signed-off-by: Ben Levinsky --- v20: - update typos and style - add compat string for singular r5 core to accomodate devm_of_platform_populate --- .../xilinx,zynqmp-r5-remoteproc.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.yaml b/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.yaml new file mode 100644 index 000000000000..9cb358389cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/xilinx,zynqmp-r5-remoteproc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xilinx R5 remote processor controller bindings + +description: + This document defines the binding for the remoteproc component that loads and + boots firmwares on the Xilinx Zynqmp and Versal family chipset. + + Note that the Linux has global addressing view of the R5-related memory (TCM) + so the absolute address ranges are provided in TCM reg's. + +maintainers: + - Ed Mooring + - Ben Levinsky + +properties: + compatible: + const: xlnx,zynqmp-r5-remoteproc + + lockstep-mode: + description: + If this property is present, then the configuration is lock-step. + Otherwise RPU is split. + type: boolean + maxItems: 1 + + interrupts: + description: + Interrupt mapping for remoteproc IPI. It is required if the + user uses the remoteproc driver with the RPMsg kernel driver. + maxItems: 6 + + memory-regions: + description: + Collection of memory carveouts used for elf-loading and inter-processor + communication. each carveout in this case should be in DDR, not + chip-specific memory. In Xilinx case, this is TCM, OCM, BRAM, etc. + $ref: /schemas/types.yaml#/definitions/phandle-array + + meta-memory-regions: + description: + Collection of memories that are not present in the top level memory + nodes' mapping. For example, R5s' TCM banks. These banks are needed + for R5 firmware meta data such as the R5 firmware's heap and stack. + To be more precise, this is on-chip reserved SRAM regions, e.g. TCM, + BRAM, OCM, etc. + $ref: /schemas/types.yaml#/definitions/phandle-array + + pnode-id: + maxItems: 1 + description: + Power node id that is used to uniquely identify the node for Xilinx + Power Management. The value is then passed to Xilinx platform + manager for power on/off and access. + $ref: /schemas/types.yaml#/definitions/uint32 + + mboxes: + description: + Array of phandles that describe the rx and tx for xilinx zynqmp + mailbox driver. order of rx and tx is described by the mbox-names + property. This will be used for communication with remote + processor. + maxItems: 2 + + mbox-names: + description: + Array of strings that denote which item in the mboxes property array + are the rx and tx for xilinx zynqmp mailbox driver + maxItems: 2 + $ref: /schemas/types.yaml#/definitions/string-array + + +examples: + - | + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + elf_load: rproc@3ed000000 { + no-map; + reg = <0x3ed00000 0x40000>; + }; + + rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 { + no-map; + reg = <0x3ed40000 0x4000>; + }; + rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 { + no-map; + reg = <0x3ed44000 0x4000>; + }; + rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 { + no-map; + reg = <0x3ed48000 0x100000>; + }; + + }; + + /* + * Below nodes are required if using TCM to load R5 firmware + * if not, then either do not provide nodes or label as disabled in + * status property + */ + tcm0a: tcm_0a@ffe00000 { + reg = <0xffe00000 0x10000>; + pnode-id = <0xf>; + no-map; + status = "okay"; + phandle = <0x40>; + }; + tcm0b: tcm_1a@ffe20000 { + reg = <0xffe20000 0x10000>; + pnode-id = <0x10>; + no-map; + status = "okay"; + phandle = <0x41>; + }; + + rpu { + compatible = "xlnx,zynqmp-r5-remoteproc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + lockstep-mode; + r5_0 { + compatible = "xlnx,zynqmp-r5-single-remoteproc"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + memory-regions = <&elf_load>, + <&rpu0vdev0vring0>, + <&rpu0vdev0vring1>, + <&rpu0vdev0buffer>; + meta-memory-regions = <&tcm_0a>, <&tcm_0b>; + pnode-id = <0x7>; + }; + }; + +... From patchwork Fri Oct 30 21:28:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Levinsky X-Patchwork-Id: 11870869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D04766A2 for ; Fri, 30 Oct 2020 21:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 935FB22202 for ; Fri, 30 Oct 2020 21:30:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="TMi4axAu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727827AbgJ3VaV (ORCPT ); Fri, 30 Oct 2020 17:30:21 -0400 Received: from mail-dm6nam11on2065.outbound.protection.outlook.com ([40.107.223.65]:30433 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727846AbgJ3VaV (ORCPT ); Fri, 30 Oct 2020 17:30:21 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KIaf7XKtDYklcNtdgROYuQeJWZ7SYLZqKziaIHEPSxAW/+eOb5SurOszAPSS9akFtzLn2mZVl29pwfcxjL+AzXkJ4D1Rjsb0DUwmHz9FGkrygkI4lu65HVZv3FcYAgwfmB7GNN/lE2kqUzVvBsGgMR1w/E1G7jCjIZHzDJGsI7KSunJuzDDqMi0u+tSrah+GnPlaJrNHvkX/M0cjt+HPirJtF/ulQvBUys2uv4uiBwqtebzqd6gqjoUdpRV/zfYtiUj/FRdfxAE8hoADDYRvdGk4NKvpT7ZIFA+Yubm59+Tb4nI+F6SrKFZHlCa8JiksK68DB4topRyXquCqk1tETA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2OFLdn3xKBjW7pyJILimJe8I2KKLXK6OOdvzrORoOBs=; b=I106Yrx113VmdTtWlGo3mYxmVIi7Ic6LWaEB9SVCBAHH4WvAfEk+EKTtgu3eTg2z7n6gwsft6KaWZVUUBuccsKwxCN0diHoCbxidgwPDXLJtXOfxZIjY87Mp6zVbwawTEZCL5C1DhOWuWIfl4N+SsHDQgRw4d6ZE9nOVkuVSWOlMVkGpatdusT5jg4NpUJRLfFEOHRwbXvYjSz1cMRiJg8yOB+y5Ik2SOOjGweblRVf+P72tZl0wVU3ul9185icHs9FDtdUqhI1OpJs4DtL/xEdx8TDVjkFDvYJi4DPIOS3fgM173vpGoVcFWHxFKuf4c/xy+/sXpEE67vNXU+Xi3A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2OFLdn3xKBjW7pyJILimJe8I2KKLXK6OOdvzrORoOBs=; b=TMi4axAuycSmVJHl2jPLKmJIOl9vB1JXDfsZdmJAiaSA2uomkgVepfWQD2kW9vxqgbOAjKt1QBy2E7zUMYx0TpqhGK+UEzlQs2PoTmDmQRKKb733j7BxzBg52piucFcu2RXPfn5G+i3+kttxaawVAqW2VRseMLYyzUwAlw4o3xg= Received: from DM5PR16CA0004.namprd16.prod.outlook.com (2603:10b6:3:c0::14) by MN2PR02MB6384.namprd02.prod.outlook.com (2603:10b6:208:1b8::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.28; Fri, 30 Oct 2020 21:28:39 +0000 Received: from CY1NAM02FT015.eop-nam02.prod.protection.outlook.com (2603:10b6:3:c0:cafe::41) by DM5PR16CA0004.outlook.office365.com (2603:10b6:3:c0::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 21:28:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT015.mail.protection.outlook.com (10.152.75.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3520.15 via Frontend Transport; Fri, 30 Oct 2020 21:28:38 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Fri, 30 Oct 2020 14:28:34 -0700 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Fri, 30 Oct 2020 14:28:34 -0700 Envelope-to: stefanos@xilinx.com, mathieu.poirier@linaro.org, devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.2.206] (port=56470 helo=xsjblevinsk50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kYbwo-0003JM-FP; Fri, 30 Oct 2020 14:28:34 -0700 From: Ben Levinsky To: , CC: , , , , Subject: [PATCH v20 5/5] remoteproc: Add initial zynqmp R5 remoteproc driver Date: Fri, 30 Oct 2020 14:28:34 -0700 Message-ID: <20201030212834.18270-6-ben.levinsky@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201030212834.18270-1-ben.levinsky@xilinx.com> References: <20201030212834.18270-1-ben.levinsky@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f54587ef-1288-4299-4930-08d87d1ac44a X-MS-TrafficTypeDiagnostic: MN2PR02MB6384: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:225; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bombXsZHgUKeyOjUhQNZmnWgISFBeu1Jc1yhK7fvJ6ZkpPCqVsVPq1g+1fK7y38Qc5zdVSJI8z35LQDr4R714LfQMfd+N7fJgSUAJQbI7vS/vceAjce5zjGGsvHwvZE9DGWCKJO6CyUcGyOOAp3FrbzlRvOZzyN/JgLF/JjUsywz6zMV/O3OLFj3EqVIZG/r8zl7SbJPmKsiQfGjai1Xx3S+DvWW9EBwGyK99du/kkOkH+hCjIHvub/+RPdWcYclPe1p/xTaiYrtLPy6etS6Y/PtZtkzWLL3M0d5J2bF6CZpQ7igANAm+9f0iTqqjDQgfjM4xTEyEdYGrWFRdE1LAD0XeuYegGCkRMoyoh//yCXpJfQSFwpoH+k7IxhIDm4JREC16IEeLe5L8ilsAfARhCkSMPycGysy0OBldG5J9Sc= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(396003)(376002)(136003)(39860400002)(346002)(46966005)(7636003)(8676002)(2906002)(70586007)(356005)(336012)(9786002)(82310400003)(44832011)(8936002)(70206006)(186003)(26005)(426003)(7696005)(1076003)(83380400001)(2616005)(82740400003)(5660300002)(47076004)(36756003)(36906005)(4326008)(54906003)(478600001)(110136005)(316002)(30864003)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 21:28:38.8119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f54587ef-1288-4299-4930-08d87d1ac44a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6384 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org R5 is included in Xilinx Zynq UltraScale MPSoC so by adding this remotproc driver, we can boot the R5 sub-system in different 2 configurations - * split * lock-step The Xilinx R5 Remoteproc Driver boots the R5's via calls to the Xilinx Platform Management Unit that handles the R5 configuration, memory access and R5 lifecycle management. The interface to this manager is done in this driver via zynqmp_pm_* function calls. Signed-off-by: Wendy Liang Signed-off-by: Michal Simek Signed-off-by: Ed Mooring Signed-off-by: Jason Wu Signed-off-by: Ben Levinsky --- - remove zynqmp_r5_rproc::dt_node and replace usage with zynqmp_r5_rproc->dev->of_node throughout file - emulate TI K3 R5 probe use of devm_of_platform_populate to set devices for each R5 core's corresponding remoteproc device - replace zynqmp_r5_rproc var name 'core' to 'z_rproc' throughout file for consistency - update indentation - remove unused var in zynqmp_r5_remoteproc_probe - update typo in Kconfig --- drivers/remoteproc/Kconfig | 8 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/zynqmp_r5_remoteproc.c | 771 ++++++++++++++++++++++ 3 files changed, 780 insertions(+) create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index c6659dfea7c7..c2fe54b1d94f 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -275,6 +275,14 @@ config TI_K3_DSP_REMOTEPROC It's safe to say N here if you're not interested in utilizing the DSP slave processors. +config ZYNQMP_R5_REMOTEPROC + tristate "ZynqMP R5 remoteproc support" + depends on PM && ARCH_ZYNQMP + select RPMSG_VIRTIO + select ZYNQMP_IPI_MBOX + help + Say y or m here to support ZynqMP R5 remote processors via the remote + processor framework. endif # REMOTEPROC endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 3dfa28e6c701..ef1abff654c2 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -33,3 +33,4 @@ obj-$(CONFIG_ST_REMOTEPROC) += st_remoteproc.o obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o +obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c b/drivers/remoteproc/zynqmp_r5_remoteproc.c new file mode 100644 index 000000000000..9c917305bdae --- /dev/null +++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq R5 Remote Processor driver + * + * Based on origin OMAP and Zynq Remote Processor driver + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +#define MAX_RPROCS 2 /* Support up to 2 RPU */ +#define MAX_MEM_PNODES 4 /* Max power nodes for one RPU memory instance */ + +#define BANK_LIST_PROP "meta-memory-regions" +#define DDR_LIST_PROP "memory-regions" + +/* IPI buffer MAX length */ +#define IPI_BUF_LEN_MAX 32U +/* RX mailbox client buffer max length */ +#define RX_MBOX_CLIENT_BUF_MAX (IPI_BUF_LEN_MAX + \ + sizeof(struct zynqmp_ipi_message)) + +/** + * struct zynqmp_r5_mem - zynqmp rpu memory data + * @pnode_id: TCM power domain ids + * @res: memory resource + * @node: list node + */ +struct zynqmp_r5_mem { + u32 pnode_id[MAX_MEM_PNODES]; + struct resource res; + struct list_head node; +}; + +/** + * struct zynqmp_r5_rproc - zynqmp rpu remote processor state + * this is for each individual R5 core's state + * + * @rx_mc_buf: rx mailbox client buffer to save the rx message + * @tx_mc: tx mailbox client + * @rx_mc: rx mailbox client * @dev: device of RPU instance + * @mbox_work: mbox_work for the RPU remoteproc + * @tx_mc_skbs: socket buffers for tx mailbox client + * @dev: device of RPU instance + * @rproc: rproc handle + * @tx_chan: tx mailbox channel + * @rx_chan: rx mailbox channel + * @pnode_id: RPU CPU power domain id + * @elem: linked list item + * @dt_node: device tree node that holds information for 1 R5 core. + */ +struct zynqmp_r5_rproc { + unsigned char rx_mc_buf[RX_MBOX_CLIENT_BUF_MAX]; + struct mbox_client tx_mc; + struct mbox_client rx_mc; + struct work_struct mbox_work; + struct sk_buff_head tx_mc_skbs; + struct device *dev; + struct rproc *rproc; + struct mbox_chan *tx_chan; + struct mbox_chan *rx_chan; + u32 pnode_id; + struct list_head elem; +}; + +/* + * r5_set_mode - set RPU operation mode + * @z_rproc: Remote processor private data + * @rpu_mode: mode specified by device tree to configure the RPU to + * + * set RPU operation mode + * + * Return: 0 for success, negative value for failure + */ +static int r5_set_mode(struct zynqmp_r5_rproc *z_rproc, + enum rpu_oper_mode rpu_mode) +{ + enum rpu_tcm_comb tcm_mode; + enum rpu_oper_mode cur_rpu_mode; + int ret; + + ret = zynqmp_pm_get_rpu_mode(z_rproc->pnode_id, &cur_rpu_mode); + if (ret < 0) + return ret; + + if (rpu_mode != cur_rpu_mode) { + ret = zynqmp_pm_set_rpu_mode(z_rproc->pnode_id, + rpu_mode); + if (ret < 0) + return ret; + } + + tcm_mode = (rpu_mode == PM_RPU_MODE_LOCKSTEP) ? + PM_RPU_TCM_COMB : PM_RPU_TCM_SPLIT; + return zynqmp_pm_set_tcm_config(z_rproc->pnode_id, tcm_mode); +} + +/* + * release TCM banks when powering down R5 core + */ +static int tcm_mem_release(struct rproc *rproc, struct rproc_mem_entry *mem) +{ + u32 pnode_id = (u64)mem->priv; + + iounmap(mem->va); + return zynqmp_pm_release_node(pnode_id); +} + +/* + * given ID corresponding to R5 core in Xilinx Platform management (xpm) API, + * try to use xpm wake call to wake R5 core + */ +static int zynqmp_r5_rproc_start(struct rproc *rproc) +{ + struct zynqmp_r5_rproc *z_rproc = rproc->priv; + enum rpu_boot_mem bootmem; + + bootmem = (rproc->bootaddr & 0xF0000000) == 0xF0000000 ? + PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC; + + dev_dbg(rproc->dev.parent, "RPU boot from %s.", + bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM"); + + return zynqmp_pm_request_wake(z_rproc->pnode_id, 1, + bootmem, ZYNQMP_PM_REQUEST_ACK_NO); +} + +/* + * given ID corresponding to R5 core in Xilinx Platform management (xpm) API, + * try to use xpm power down call to power off R5 core + */ +static int zynqmp_r5_rproc_stop(struct rproc *rproc) +{ + struct zynqmp_r5_rproc *z_rproc = rproc->priv; + + return zynqmp_pm_force_pwrdwn(z_rproc->pnode_id, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); +} + +/* + * map in physical addr for DDR mem carveout in rproc + */ +static int zynqmp_r5_rproc_mem_alloc(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + void *va; + + va = ioremap_wc(mem->dma, mem->len); + if (IS_ERR_OR_NULL(va)) + return -ENOMEM; + + /* Update memory entry va */ + mem->va = va; + + return 0; +} + +/* unmap rproc_mem_entry virtual addr */ +static int zynqmp_r5_rproc_mem_release(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + iounmap(mem->va); + return 0; +} + +/* construct rproc mem carveouts for DDR regions specified in device tree */ +static int parse_mem_regions(struct rproc *rproc) +{ + int num_mems, i; + struct zynqmp_r5_rproc *z_rproc = rproc->priv; + struct device *dev = &rproc->dev; + struct device_node *np = z_rproc->dev->of_node; + struct rproc_mem_entry *mem; + + num_mems = of_count_phandle_with_args(np, DDR_LIST_PROP, NULL); + if (num_mems <= 0) + return 0; + + for (i = 0; i < num_mems; i++) { + struct device_node *node; + struct reserved_mem *rmem; + + node = of_parse_phandle(np, DDR_LIST_PROP, i); + if (!node) + return -EINVAL; + + rmem = of_reserved_mem_lookup(node); + if (!rmem) + return -EINVAL; + + if (strstr(node->name, "vdev0vring")) { + int vring_id; + char name[16]; + + /* + * expecting form of "rpuXvdev0vringX as documented + * in xilinx remoteproc device tree binding + */ + if (strlen(node->name) < 15) { + dev_err(dev, "%pOF is less than 14 chars", + node); + return -EINVAL; + } + + /* + * can be 1 of multiple vring IDs per IPC channel + * e.g. 'vdev0vring0' and 'vdev0vring1' + */ + vring_id = node->name[14] - '0'; + snprintf(name, sizeof(name), "vdev0vring%d", vring_id); + /* Register vring */ + mem = rproc_mem_entry_init(dev, NULL, + (dma_addr_t)rmem->base, + rmem->size, rmem->base, + zynqmp_r5_rproc_mem_alloc, + zynqmp_r5_rproc_mem_release, + name); + } else { + /* Register DMA region */ + int (*alloc)(struct rproc *r, + struct rproc_mem_entry *rme); + int (*release)(struct rproc *r, + struct rproc_mem_entry *rme); + char name[20]; + + if (strstr(node->name, "vdev0buffer")) { + alloc = NULL; + release = NULL; + strcpy(name, "vdev0buffer"); + } else { + alloc = zynqmp_r5_rproc_mem_alloc; + release = zynqmp_r5_rproc_mem_release; + strcpy(name, node->name); + } + + mem = rproc_mem_entry_init(dev, NULL, + (dma_addr_t)rmem->base, + rmem->size, rmem->base, + alloc, release, name); + } + if (!mem) + return -ENOMEM; + + rproc_add_carveout(rproc, mem); + } + + return 0; +} + +/* call Xilinx Platform manager to request access to TCM bank */ +static int zynqmp_r5_pm_request_tcm(struct device_node *tcm_node, + struct device *dev, u32 *pnode_id) +{ + int ret; + + ret = of_property_read_u32(tcm_node, "pnode-id", pnode_id); + if (ret) + return ret; + + return zynqmp_pm_request_node(*pnode_id, ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); +} + +/* + * Given TCM bank entry, + * this callback will set device address for R5 running on TCM + * and also setup virtual address for TCM bank remoteproc carveout + */ +static int tcm_mem_alloc(struct rproc *rproc, + struct rproc_mem_entry *mem) +{ + void *va; + struct device *dev = rproc->dev.parent; + + va = ioremap_wc(mem->dma, mem->len); + if (IS_ERR_OR_NULL(va)) + return -ENOMEM; + + /* Update memory entry va */ + mem->va = va; + + va = devm_ioremap_wc(dev, mem->da, mem->len); + if (!va) + return -ENOMEM; + /* As R5 is 32 bit, wipe out extra high bits */ + mem->da &= 0x000fffff; + /* + * TCM Banks 0A and 0B (0xffe00000 and 0xffe20000) + * are handled with the above line of code so do nothing + * for this 2 banks + */ + + /* + * TCM Banks 1A and 1B (0xffe90000 and 0xffeb0000) still + * need to be translated to 0x0 and 0x20000 + */ + if (mem->da == 0x90000 || mem->da == 0xB0000) + mem->da -= 0x90000; + + /* if translated TCM bank address is not valid report error */ + if (mem->da != 0x0 && mem->da != 0x20000) { + dev_err(dev, "invalid TCM bank address: %x\n", mem->da); + return -EINVAL; + } + + return 0; +} + +/* + * Given R5 node in remoteproc instance + * allocate remoteproc carveout for TCM memory + * needed for firmware to be loaded + */ +static int parse_tcm_banks(struct rproc *rproc) +{ + int i, num_banks; + struct zynqmp_r5_rproc *z_rproc = rproc->priv; + struct device *dev = &rproc->dev; + struct device_node *r5_node = z_rproc->dev->of_node; + + /* go through TCM banks for r5 node */ + num_banks = of_count_phandle_with_args(r5_node, BANK_LIST_PROP, NULL); + if (num_banks <= 0) { + dev_err(dev, "need to specify TCM banks\n"); + return -EINVAL; + } + for (i = 0; i < num_banks; i++) { + struct resource rsc; + resource_size_t size; + struct device_node *dt_node; + struct rproc_mem_entry *mem; + int ret; + u32 pnode_id; /* zynqmp_pm* fn's expect u32 */ + + dt_node = of_parse_phandle(r5_node, BANK_LIST_PROP, i); + if (!dt_node) + return -EINVAL; + + if (of_device_is_available(dt_node)) { + ret = of_address_to_resource(dt_node, 0, &rsc); + if (ret < 0) + return ret; + + ret = zynqmp_r5_pm_request_tcm(dt_node, dev, &pnode_id); + if (ret < 0) + return ret; + + /* add carveout */ + size = resource_size(&rsc); + mem = rproc_mem_entry_init(dev, NULL, rsc.start, + (int)size, rsc.start, + tcm_mem_alloc, + tcm_mem_release, + rsc.name); + if (!mem) + return -ENOMEM; + + mem->priv = (void *)(u64)pnode_id; + rproc_add_carveout(rproc, mem); + } + } + + return 0; +} + +/* + * when loading firmware, load in needed DDR, TCM memory regions and wire + * these into remoteproc core's carveouts + */ +static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw) +{ + int ret; + + ret = parse_tcm_banks(rproc); + if (ret) + return ret; + + ret = parse_mem_regions(rproc); + if (ret) + return ret; + + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret == -EINVAL) { + /* + * resource table only required for IPC. + * if not present, this is not necessarily an error; + * for example, loading r5 hello world application + * so simply inform user and keep going. + */ + dev_info(&rproc->dev, "no resource table found.\n"); + ret = 0; + } + return ret; +} + +/* kick a firmware */ +static void zynqmp_r5_rproc_kick(struct rproc *rproc, int vqid) +{ + struct sk_buff *skb; + unsigned int skb_len; + struct zynqmp_ipi_message *mb_msg; + int ret; + + struct device *dev = rproc->dev.parent; + struct zynqmp_r5_rproc *z_rproc = rproc->priv; + + skb_len = (unsigned int)(sizeof(vqid) + sizeof(mb_msg)); + skb = alloc_skb(skb_len, GFP_ATOMIC); + if (!skb) + return; + + mb_msg = (struct zynqmp_ipi_message *)skb_put(skb, skb_len); + mb_msg->len = sizeof(vqid); + memcpy(mb_msg->data, &vqid, sizeof(vqid)); + skb_queue_tail(&z_rproc->tx_mc_skbs, skb); + ret = mbox_send_message(z_rproc->tx_chan, mb_msg); + if (ret < 0) { + dev_warn(dev, "Failed to kick remote.\n"); + skb_dequeue_tail(&z_rproc->tx_mc_skbs); + kfree_skb(skb); + } +} + +static struct rproc_ops zynqmp_r5_rproc_ops = { + .start = zynqmp_r5_rproc_start, + .stop = zynqmp_r5_rproc_stop, + .load = rproc_elf_load_segments, + .parse_fw = zynqmp_r5_parse_fw, + .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, + .sanity_check = rproc_elf_sanity_check, + .get_boot_addr = rproc_elf_get_boot_addr, + .kick = zynqmp_r5_rproc_kick, +}; + +/** + * event_notified_idr_cb() - event notified idr callback + * @id: idr id + * @ptr: pointer to idr private data + * @data: data passed to idr_for_each callback + * + * Pass notification to remoteproc virtio + * + * Return: 0. having return is to satisfy the idr_for_each() function + * pointer input argument requirement. + **/ +static int event_notified_idr_cb(int id, void *ptr, void *data) +{ + struct rproc *rproc = data; + + (void)rproc_vq_interrupt(rproc, id); + return 0; +} + +/** + * handle_event_notified() - remoteproc notification work funciton + * @work: pointer to the work structure + * + * It checks each registered remoteproc notify IDs. + */ +static void handle_event_notified(struct work_struct *work) +{ + struct rproc *rproc; + struct zynqmp_r5_rproc *z_rproc; + + z_rproc = container_of(work, struct zynqmp_r5_rproc, mbox_work); + + (void)mbox_send_message(z_rproc->rx_chan, NULL); + rproc = z_rproc->rproc; + /* + * We only use IPI for interrupt. The firmware side may or may + * not write the notifyid when it trigger IPI. + * And thus, we scan through all the registered notifyids. + */ + idr_for_each(&rproc->notifyids, event_notified_idr_cb, rproc); +} + +/** + * zynqmp_r5_mb_rx_cb() - Receive channel mailbox callback + * @cl: mailbox client + * @mssg: message pointer + * + * It will schedule the R5 notification work. + */ +static void zynqmp_r5_mb_rx_cb(struct mbox_client *cl, void *mssg) +{ + struct zynqmp_r5_rproc *z_rproc; + + z_rproc = container_of(cl, struct zynqmp_r5_rproc, rx_mc); + if (mssg) { + struct zynqmp_ipi_message *ipi_msg, *buf_msg; + size_t len; + + ipi_msg = (struct zynqmp_ipi_message *)mssg; + buf_msg = (struct zynqmp_ipi_message *)z_rproc->rx_mc_buf; + len = (ipi_msg->len >= IPI_BUF_LEN_MAX) ? + IPI_BUF_LEN_MAX : ipi_msg->len; + buf_msg->len = len; + memcpy(buf_msg->data, ipi_msg->data, len); + } + schedule_work(&z_rproc->mbox_work); +} + +/** + * zynqmp_r5_mb_tx_done() - Request has been sent to the remote + * @cl: mailbox client + * @mssg: pointer to the message which has been sent + * @r: status of last TX - OK or error + * + * It will be called by the mailbox framework when the last TX has done. + */ +static void zynqmp_r5_mb_tx_done(struct mbox_client *cl, void *mssg, int r) +{ + struct zynqmp_r5_rproc *z_rproc; + struct sk_buff *skb; + + if (!mssg) + return; + z_rproc = container_of(cl, struct zynqmp_r5_rproc, tx_mc); + skb = skb_dequeue(&z_rproc->tx_mc_skbs); + kfree_skb(skb); +} + +/** + * zynqmp_r5_setup_mbox() - Setup mailboxes + * this is used for each individual R5 core + * + * @z_rproc: pointer to the ZynqMP R5 processor platform data + * @node: pointer of the device node + * + * Function to setup mailboxes to talk to RPU. + * + * Return: 0 for success, negative value for failure. + */ +static int zynqmp_r5_setup_mbox(struct zynqmp_r5_rproc *z_rproc, + struct device_node *node) +{ + struct mbox_client *mclient; + + /* Setup TX mailbox channel client */ + mclient = &z_rproc->tx_mc; + mclient->rx_callback = NULL; + mclient->tx_block = false; + mclient->knows_txdone = false; + mclient->tx_done = zynqmp_r5_mb_tx_done; + mclient->dev = z_rproc->dev; + + /* Setup TX mailbox channel client */ + mclient = &z_rproc->rx_mc; + mclient->dev = z_rproc->dev; + mclient->rx_callback = zynqmp_r5_mb_rx_cb; + mclient->tx_block = false; + mclient->knows_txdone = false; + + INIT_WORK(&z_rproc->mbox_work, handle_event_notified); + + /* Request TX and RX channels */ + z_rproc->tx_chan = mbox_request_channel_byname(&z_rproc->tx_mc, "tx"); + if (IS_ERR(z_rproc->tx_chan)) { + dev_err(z_rproc->dev, "failed to request mbox tx channel.\n"); + z_rproc->tx_chan = NULL; + return -EINVAL; + } + + z_rproc->rx_chan = mbox_request_channel_byname(&z_rproc->rx_mc, "rx"); + if (IS_ERR(z_rproc->rx_chan)) { + dev_err(z_rproc->dev, "failed to request mbox rx channel.\n"); + z_rproc->rx_chan = NULL; + return -EINVAL; + } + skb_queue_head_init(&z_rproc->tx_mc_skbs); + + return 0; +} + +/** + * zynqmp_r5_probe() - Probes ZynqMP R5 processor device node + * this is called for each individual R5 core to + * set up mailbox, Xilinx platform manager unique ID, + * add to rproc core + * + * @z_rproc: pointer to the ZynqMP R5 processor platform data + * @pdev: parent RPU domain platform device + * @node: pointer of the device node + * @rpu_mode: mode to configure RPU, split or lockstep + * @z_rproc: Xilinx specific remoteproc structure used later to link + * in to cluster of cores + * + * Function to retrieve the information of the ZynqMP R5 device node. + * + * Return: 0 for success, negative value for failure. + */ +static int zynqmp_r5_probe(struct platform_device *pdev, + struct device_node *node, + enum rpu_oper_mode rpu_mode, + struct zynqmp_r5_rproc **core) +{ + int ret; + struct device *dev = &pdev->dev; + struct rproc *rproc_ptr; + struct zynqmp_r5_rproc *z_rproc; + + /* Allocate remoteproc instance */ + /* dev here is parent device of the allocated rproc's dev field */ + rproc_ptr = rproc_alloc(dev, dev_name(dev), &zynqmp_r5_rproc_ops, + NULL, sizeof(struct zynqmp_r5_rproc)); + if (!rproc_ptr) + return -ENOMEM; + z_rproc = rproc_ptr->priv; + z_rproc->rproc = rproc_ptr; + z_rproc->dev = dev; + /* Set up DMA mask */ + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (ret) + goto error; + /* Get R5 power domain node */ + ret = of_property_read_u32(node, "pnode-id", &z_rproc->pnode_id); + if (ret) + goto error; + + ret = r5_set_mode(z_rproc, rpu_mode); + if (ret) + return ret; + + if (of_property_read_bool(node, "mboxes")) { + ret = zynqmp_r5_setup_mbox(z_rproc, node); + if (ret) + goto error; + } + /* Add R5 remoteproc */ + ret = rproc_add(rproc_ptr); + if (ret) + goto error; + *core = z_rproc; + + return 0; +error: + if (z_rproc->rproc) + rproc_free(z_rproc->rproc); + z_rproc->rproc = NULL; + return ret; +} + +/* + * called when driver is probed, for each R5 core specified in DT, + * setup as needed to do remoteproc-related operations + */ +static int zynqmp_r5_remoteproc_probe(struct platform_device *pdev) +{ + int ret, i; + struct device *dev = &pdev->dev; + struct device_node *nc; + enum rpu_oper_mode rpu_mode; + struct list_head *cluster; /* list to track each core's rproc */ + struct zynqmp_r5_rproc *z_rproc; + struct platform_device *child_pdev; + + rpu_mode = of_property_read_bool(dev->of_node, "lockstep-mode") ? + PM_RPU_MODE_LOCKSTEP : PM_RPU_MODE_SPLIT; + dev_dbg(dev, "RPU configuration: %s\n", + rpu_mode == PM_RPU_MODE_LOCKSTEP ? "lockstep" : "split"); + + /* + * if 2 RPUs provided but one is lockstep, then we have an + * invalid configuration. + */ + i = of_get_available_child_count(dev->of_node); + if ((rpu_mode == PM_RPU_MODE_LOCKSTEP && i != 1) || i > MAX_RPROCS) + return -EINVAL; + + cluster = devm_kzalloc(dev, sizeof(cluster), GFP_KERNEL); + ret = devm_of_platform_populate(dev); + if (ret) { + dev_err(dev, "devm_of_platform_populate failed, ret = %d\n", + ret); + return ret; + } + INIT_LIST_HEAD(cluster); + /* probe each individual r5 core's remoteproc-related info */ + for_each_available_child_of_node(dev->of_node, nc) { + child_pdev = of_find_device_by_node(nc); + if (!child_pdev) { + dev_err(dev, "could not get R5 core platform device\n"); + return -ENODEV; + } + + ret = zynqmp_r5_probe(child_pdev, nc, rpu_mode, &z_rproc); + dev_dbg(dev, "%s to probe rpu %pOF\n", + ret ? "Failed" : "Able", + nc); + if (ret) + return ret; + if (!z_rproc) + return -EINVAL; + list_add_tail(&z_rproc->elem, cluster); + i++; + } + /* wire in so each core can be cleaned up at drive remove */ + platform_set_drvdata(pdev, cluster); + + return 0; +} + +/* + * for each core, clean up the following: + * single rproc entry + * mailbox tx, rx + */ +static int zynqmp_r5_remoteproc_remove(struct platform_device *pdev) +{ + struct list_head *pos, *cluster = (struct list_head *) + platform_get_drvdata(pdev); + struct zynqmp_r5_rproc *z_rproc = NULL; + struct rproc *rproc = NULL; + + list_for_each(pos, cluster) { + z_rproc = list_entry(pos, struct zynqmp_r5_rproc, elem); + if (!z_rproc) + return -EINVAL; + rproc = z_rproc->rproc; + if (rproc) { + rproc_del(rproc); + rproc_free(rproc); + z_rproc->rproc = NULL; + } + + if (z_rproc->tx_chan) { + mbox_free_channel(z_rproc->tx_chan); + z_rproc->tx_chan = NULL; + } + if (z_rproc->rx_chan) { + mbox_free_channel(z_rproc->rx_chan); + z_rproc->rx_chan = NULL; + } + } + return 0; +} + +/* Match table for OF platform binding */ +static const struct of_device_id zynqmp_r5_remoteproc_match[] = { + { .compatible = "xlnx,zynqmp-r5-remoteproc", }, + { /* end of list */ }, +}; +MODULE_DEVICE_TABLE(of, zynqmp_r5_remoteproc_match); + +static struct platform_driver zynqmp_r5_remoteproc_driver = { + .probe = zynqmp_r5_remoteproc_probe, + .remove = zynqmp_r5_remoteproc_remove, + .driver = { + .name = "zynqmp_r5_remoteproc", + .of_match_table = zynqmp_r5_remoteproc_match, + }, +}; +module_platform_driver(zynqmp_r5_remoteproc_driver); + +MODULE_AUTHOR("Ben Levinsky "); +MODULE_LICENSE("GPL v2");