From patchwork Mon Nov 2 14:30:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Qilong X-Patchwork-Id: 11873959 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2A3C92C for ; Mon, 2 Nov 2020 14:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D437920679 for ; Mon, 2 Nov 2020 14:20:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725959AbgKBOUR (ORCPT ); Mon, 2 Nov 2020 09:20:17 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:7033 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726096AbgKBOUJ (ORCPT ); Mon, 2 Nov 2020 09:20:09 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CPw6X5scHzhdVF; Mon, 2 Nov 2020 22:20:04 +0800 (CST) Received: from huawei.com (10.90.53.225) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Mon, 2 Nov 2020 22:20:00 +0800 From: Zhang Qilong To: , , , , CC: , Subject: [PATCH] PCI: dwc: fix reference leak in pex_ep_event_pex_rst_deassert Date: Mon, 2 Nov 2020 22:30:45 +0800 Message-ID: <20201102143045.142121-1-zhangqilong3@huawei.com> X-Mailer: git-send-email 2.26.0.106.g9fadedd MIME-Version: 1.0 X-Originating-IP: [10.90.53.225] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to pm_runtime_put_noidle will result in reference leak in pex_ep_event_pex_rst_deassert, so we should fix it. Fixes: c57247f940e8e ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Signed-off-by: Zhang Qilong --- drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f920e7efe118..936510b5c649 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1662,6 +1662,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) ret = pm_runtime_get_sync(dev); if (ret < 0) { + pm_runtime_put_noidle(dev); dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", ret); return;