From patchwork Fri Nov 6 09:27:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C69C55178 for ; Fri, 6 Nov 2020 09:29:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 827FE20B80 for ; Fri, 6 Nov 2020 09:29:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="H3Ew2dI/"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ZffDnels" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 827FE20B80 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=LuLuKSuHmsJmb95CdaSGTgXsaMePAUcQu83IaCAzGws=; b=H3Ew2dI/wD7qa5jZ5JhNdpuNv iPYAj0m5Tb4+aVV+hg0tJAS+ARJBeYlibmAVaMD1K8CSsnR8sFNXjwrYF6xtm3cv7qCa1797MkE9U xwebOG0/TrdsQ2PRMhHuCoDk0hrW07LLVg2P2EmLbbslDHc3aD2IEGAF5F8Gbj1XJQ5E8K+CguQyh 3N0J+/zrk8R7xqx4EXRjLWbui2+ajVQ2RfYMUXD6npWdxtS97TUSsw+ABZ1xXqCpovIJP87HJuIzw 3K6d/AnmRpSPpFNIvguE2TynebEHG7SsxLyordU/SJsEyE/6DnFAEzMVL0jkChJl+SxMV+FGcPfid YzA9oM25g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2l-0000j3-FW; Fri, 06 Nov 2020 09:28:27 +0000 Received: from esa5.microchip.iphmx.com ([216.71.150.166]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2f-0000f6-1z for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654901; x=1636190901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=QpD53wBg29UptUvVNqRf5JTCpttxxocLcDTpaKiBG1k=; b=ZffDnelsJTyj50VwMLoLyi4FazklPyG6L1LGy/2g8/79uxjDpBpj+oXt +0x4nGpdCpNZ7XxuYDfs/ZFj1Gog+Pl+TZLtYuKw7gx+8Vdec386nmDj0 41Hkw7lXzMGQohDfyfo6buwbDoIucNC79dyXGQ7ovXR9YOrbh7pyTr3kF fo0rF4eV8EfkLwtXei1QwXKfoSoMzIJEx+IwPpRvP8khfj7lnXCd4xZzx eJc9jDCF175n40Cezid/3dCkO1PB2a+8oyUVpWz0ABwFBH2gSxQW2FNBK tfw/A0Zm/9/RSaKWR1wV7rKSMaBW5ZXyGrtNzP3OlLHFTBmReNHBpzI1f g==; IronPort-SDR: EjMR1QoQACNq8qJ+vGWcjbpfR6eyDPZMDPaO9xVEWTcaYvRGqEWZCJIDjSz1tL/ioLl1LhWUpm apl9uqDeN85uGlaSBfdAsxSah/yZkOFuSmC0QaYpQ9f7YEWQ9/uZrbGu5s0EKzU29nwWW3IhB2 7awICnlRDF3/xI2XkNR7lvqQcQW+ifxHhW1iMj4haeI3+iw+NIuFytHLa+kaS8lMtYjWOMEZkF f5vCUJJIa5SEWqOQIn13iztIbjR3t07QoWkEEyGmeWmpSD0QGaqPSCFjCLJnEhH4ABi7TX+WqN 3Ho= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="97423916" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:20 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:20 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:15 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 01/11] clk: at91: sama7g5: fix compilation error Date: Fri, 6 Nov 2020 11:27:54 +0200 Message-ID: <1604654884-30339-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042821_316839_7178D4F3 X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org pmc_data_allocate() has been changed. pmc_data_free() was removed. Adapt the code taking this into consideration. With this the programmable clocks were also saved in sama7g5_pmc so that they could be later referenced. Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 0db2ab3eca14..a092a940baa4 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -838,7 +838,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), - nck(sama7g5_gck)); + nck(sama7g5_gck), 8); if (!sama7g5_pmc) return; @@ -980,6 +980,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_prog_mux_table); if (IS_ERR(hw)) goto err_free; + + sama7g5_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { @@ -1052,7 +1054,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) kfree(alloc_mem); } - pmc_data_free(sama7g5_pmc); + kfree(sama7g5_pmc); } /* Some clks are used for a clocksource */ From patchwork Fri Nov 6 09:27:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E61D9C2D0A3 for ; Fri, 6 Nov 2020 09:30:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59977208B3 for ; Fri, 6 Nov 2020 09:30:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="USvsOS9H"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Agrmwwrm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 59977208B3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TLh6pAhzTOP7NZGUtwWTs4dn87cIYxdUnxHp/ZkoZbs=; b=USvsOS9HIPn74xt94lHa8YEhs MzJdJsdYCxGO9G0oRRrn7JUQMx83bWEfFO6S26l6MSq5JQc65Bj9lSyVDFNARV9++QllGksR/z+Tg dNTVQy2ab7VHkiFcZE1Ka3b7+sYc2XM2hZyNVw6liIifREHa6sUT2IHZQeB+iccnI4L/3N3uAIiiv d/+lFDBMsY1eFVLaQRnPhRl8KLGns2Hc7JKJvpB16voDnoPdJIa7pSYGHarKLYrlu1goImHhYS3fC s240BcM+Sz8FerfIx4RHwD6FZZjGnGnMLzYgvPbqJM1UrqxZuGgPPR+6+oQbQj8CDc2vxyuJyttXt vUXIt2AJA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2r-0000lr-73; Fri, 06 Nov 2020 09:28:33 +0000 Received: from esa5.microchip.iphmx.com ([216.71.150.166]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2j-0000f6-NY for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654905; x=1636190905; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=B6iK+n7nM/nQQNkN9ji7/vC55A4k5oqZAjN/W6Ui+Vw=; b=Agrmwwrm74pUUc3UFFOW+mx2j7ehlR5kGLYujxNWL5AntIsoUfz56ZqP AvG+xtEO0PzIa6Z/sldmJlX52h/lCZH/qFPc38BBxjnuM9wJiZqAaGo6H VMz/8bJR7zNROsZWGGcherFGepoz0YHUvoeEKtHrKLhwxC6H4y4MLmUZD MJTrAZfxp52I820HB9JGo22TWxtGaBSM9hCoI6gMHeZrzQcB9nEoXWYYS SQZd0vdBPi29ZKmcUsuuEuZDHhVneSqj8aGQRvfp69YXX6A4b5smtPj2i sSaYdzVEIiwVbXZzw6OHfBzE1LsTwZgIaxNtzYOn7t6k9RjWqHQf6kwdU w==; IronPort-SDR: le04PSe6TD0jb7YDhgqoMvNMuB+xCV+VB/N2BQM6pId8Uy0BK04ZGNpE6/q3ceP+R+vjSWCGkI PVSWuUnIFtXGWoxrAguGG26zv/HpFqzLfmuvfyX9FsQtzvK3KlS6tlvlLY2xZa564/1fQ6mCX7 y00fN8WHAUmbgoRCsCzrTGT9lyAOhVHYX6OE4qbo0Hb7vGnUuyFeSjuLUVgcwl61h+9GIvDSsx QRfKuAV/LoionQCXCtCZQEbVQn9oVy0ee3IIlTzGI1qL7y4POCSgWJmyCSIBkWmJoRjuBABdaX KM0= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="97423939" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:25 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:20 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 02/11] dt-bindings: clock: at91: add sama7g5 pll defines Date: Fri, 6 Nov 2020 11:27:55 +0200 Message-ID: <1604654884-30339-3-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042826_061090_6A35BFC8 X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Eugen Hristev Add SAMA7G5 specific PLL defines to be referenced in a phandle as a PMC_TYPE_CORE clock. Suggested-by: Claudiu Beznea Signed-off-by: Eugen Hristev [claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 6 +++--- include/dt-bindings/clock/at91.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index a092a940baa4..7ef7963126b6 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -182,13 +182,13 @@ static const struct { .p = "audiopll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .eid = PMC_I2S0_MUX, }, + .eid = PMC_AUDIOPMCPLL, }, { .n = "audiopll_diviock", .p = "audiopll_fracck", .l = &pll_layout_divio, .t = PLL_TYPE_DIV, - .eid = PMC_I2S1_MUX, }, + .eid = PMC_AUDIOIOPLL, }, }, [PLL_ID_ETH] = { @@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, + sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index eba17106608b..fab313f62e8f 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -25,6 +25,16 @@ #define PMC_PLLBCK 8 #define PMC_AUDIOPLLCK 9 +/* SAMA7G5 */ +#define PMC_CPUPLL (PMC_MAIN + 1) +#define PMC_SYSPLL (PMC_MAIN + 2) +#define PMC_DDRPLL (PMC_MAIN + 3) +#define PMC_IMGPLL (PMC_MAIN + 4) +#define PMC_BAUDPLL (PMC_MAIN + 5) +#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) +#define PMC_AUDIOIOPLL (PMC_MAIN + 7) +#define PMC_ETHPLL (PMC_MAIN + 8) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ From patchwork Fri Nov 6 09:27:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9218C388F2 for ; Fri, 6 Nov 2020 09:30:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 58E8C20B80 for ; Fri, 6 Nov 2020 09:30:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="T0i54jK5"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PuAvjWkw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 58E8C20B80 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PnAAeAErwwYwjvNjH9i6SmO6WRB501coQbuP/9znHuo=; b=T0i54jK5IUJnT0HbwfiHlM+Gr 73ORARPSUy9HjIUWRFpNTCpfR78H25+ooh77FW7ilXIZ0Vw87j0J/yfLxIXIgX/Z083H49O9h7qET gfSWpo5DgaFVoSsKKLnXp+eZORNcjpk2cQyxcKrpBT+KCUcNU7+Xgy12ai3ZCiuPe3o/9nLKUET6h E+2wxs5CHGiZUMLJKrdsOGF8gcEDzXpxLSsaEXaz94bgjloaqifhMVwwcpJCPEKPCgMbyG7ZoelUZ upTby6R2ihz1QkSMXHJq9nrojF+C4ntg2xZmB4+MZBGpAO2DALJmznwGU4nYNJ7ioo/XPsK99TfDJ tav/byEDw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2w-0000nW-Cn; Fri, 06 Nov 2020 09:28:38 +0000 Received: from esa6.microchip.iphmx.com ([216.71.154.253]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2q-0000lL-CP for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654912; x=1636190912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=5kPPY8aoeoIt3eWzwt2rrqZVySb3GOzC6e0UsowoKcY=; b=PuAvjWkwC6D2OorK8OipBrUJjU3JSRPz0Tk9zixFiHtgQuP5St8mBlJr kc2TjtCyS1T0W+Ai5l4pEdOI4racXMDuu9vSW41BkEUh9ZACxG8C0OCbZ RmGO2+hXNjw+RmePZxraTGQnC2pfR7LyLL2DeYIeRZViu1ohvwQGu35I2 D2Iwy4gtneLjp4a+oNTSnLAgpC9QnSON9EJ66H97QKpUAqjC5r6v4D/hV YXEjvWbE0/Can4Sqz2xPAQwzzQEcELlLTkQJ4riQzAvFljhRWAR6Gi04i 4v86nXJwEfDCoXLuHlYh3xgi/kAMlrjoxCNFGYFr6mqAqE12cdMwMpGCI w==; IronPort-SDR: 1fjsl6yYM7fNbXBvBe9gzLHQ8E82cXtCSuTOF+YjYmt0o7jEVNsUR9B9RX2OlFcluwUZ2pNLXF FTZTrE8/A/GQmH+DU5946tlGOgKkkrrt2GLXUKDzlHMgc9Oc/36wd6Aox5nJvuLvqmV2W8wutL tkh5ypAVgVXZuPlycp2cvFQEedgMAR7oz3Nnq48ChVDN6jpo6I7iTg4DjI7hIRAhmVzsaRxsMk yq+jtBmjXYD/H3ZimlUoZ2bxn76JVktCfqSNP1E4y8t7Hb/kyAdK6ssR/UWp4N/TPBQvKqNUt8 POY= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32677730" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:30 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:25 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT Date: Fri, 6 Nov 2020 11:27:56 +0200 Message-ID: <1604654884-30339-4-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042832_647222_F92C75F6 X-CRM114-Status: GOOD ( 11.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Eugen Hristev Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Suggested-by: Claudiu Beznea Signed-off-by: Eugen Hristev [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 7ef7963126b6..d3c3469d47d9 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -117,7 +117,8 @@ static const struct { .p = "cpupll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_CPUPLL, }, }, [PLL_ID_SYS] = { @@ -131,7 +132,8 @@ static const struct { .p = "syspll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_SYSPLL, }, }, [PLL_ID_DDR] = { From patchwork Fri Nov 6 09:27:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BCE2C388F2 for ; Fri, 6 Nov 2020 09:30:19 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA399208B3 for ; Fri, 6 Nov 2020 09:30:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Nt9CT62y"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="SZYb3XXW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA399208B3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vt4406b9YUIjFGTzBl48ps2T74N6V3NOoaq5POMqiKo=; b=Nt9CT62yrMe/ip44WAXNHchYs jHh4X5znJlQyzorLLM5MACsnsRf+ewjw8KC/3R2Itkw98I6gUExeUPEgmKhwJ3SgMVXlCd+j334hh JzkWk4VJndeaTOHlEY9gDnj7Yq0yjguooJF5v7w5ZDVSw+ZEUCyMC3fIhmkvVx8IoAkiknDFIIKaw tZd66rTABNx13gnbIm2peuE9o68jxac2eLEzbsiyYbfwy9bPMhKhqULIPQuNjD9/+bdVgdV6TBHlZ EpIIlLsCxU9LfkHV3ELqAOU/Gv8TlDCEtOZWQyLQMkjn5Lv6/+InIv52Aeq98w7k3N0bKiPuecm02 q72puOXig==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay30-0000qh-Rd; Fri, 06 Nov 2020 09:28:42 +0000 Received: from esa6.microchip.iphmx.com ([216.71.154.253]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay2u-0000lL-At for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654916; x=1636190916; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=FrCYjC2ukUCDH3p6+EqKIEI32HKV++foBRusYDNEF6Q=; b=SZYb3XXWFYH78Qib0haA6R5vI/tek3pMcNDldsf0OL8dTfuorF+YIJA6 NakAMI9rb/maBG4otYoQ15X9leCzKOcjBOEuPapw31akS0+vGh61MR0pL nWtPDD/2SCSeqskOk4AsLayyZegdEHl+N7mzllr/5tI7mimZRX7dJ7dq6 92mX6vMk1YvW/0WriGElKEiXgwGDkqu0lMyNQLVIx9vf9HENxFMgKPGIu KpjDF7hEeE4ldk63XlZ8b6+tJ96ubQEADNMnQQCddQ+V4sUnIDq39PK65 BTLkhaH2LAwOQ0TUUwIomDgVj2rKZJ/2c4a7YyzMrrPii5NfPFW6QFKAU A==; IronPort-SDR: H/FDb0C7Mp7tEma+OaaL1ahIxFyUntfeDNaI4OcpzszzpXMyKTBPfGz3+WXpyNXWVXvnYN9dp3 NPMKOv6ceYHGDHL0pbhJeEYfvS3sl1qHDt3f+M99ND9f7KaS5lBbDq04C86i6oCcQ1e1/l8IEW 7I53ojWYyEIvQx8D2+UCET5iouh6xxHXlqGnfSIumpT9L75qRkqH063Si4h8+L0wFLo6KdZaza HxKBjjNfB0nJJgFjeALCD2jLMKUSQmseL3+bkdlgj2sDc+gS+5rTsCYt+jLze1wWf/LmW/MtB0 TNk= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32677742" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:35 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:35 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:30 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 04/11] clk: at91: clk-master: add 5th divisor for mck master Date: Fri, 6 Nov 2020 11:27:57 +0200 Message-ID: <1604654884-30339-5-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042836_618167_75542083 X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Eugen Hristev clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain Signed-off-by: Eugen Hristev Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index bd0d8a69a2cf..aafd003b30cf 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -15,7 +15,7 @@ #define MASTER_PRES_MASK 0x7 #define MASTER_PRES_MAX MASTER_PRES_MASK #define MASTER_DIV_SHIFT 8 -#define MASTER_DIV_MASK 0x3 +#define MASTER_DIV_MASK 0x7 #define PMC_MCR 0x30 #define PMC_MCR_ID_MSK GENMASK(3, 0) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 7b86affc6d7c..0a9364bde339 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout; struct clk_master_characteristics { struct clk_range output; - u32 divisors[4]; + u32 divisors[5]; u8 have_div3_pres; }; From patchwork Fri Nov 6 09:27:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8862DC2D0A3 for ; Fri, 6 Nov 2020 09:31:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D49E120B80 for ; Fri, 6 Nov 2020 09:31:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="VXUVtlm+"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="uKvLFggs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D49E120B80 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ANEZIPHECFNoq25orPTk89kdIbKOIFo8M21urvT+YV4=; b=VXUVtlm+RhUfBSQFCYDxuwGuD EoxuoPR2KRuugwY5o1JA+u7AqGUxDLjNY++3ZmQ0zE8t7uslUzuiKCiUFnOCVzGP61PoGPdL3pnup jakfIUkcBgT7E6IogHonHYCjbLIOIt0xf7QR8+q6Y22tDkaSFGx8e/L+5KiLHkam9FkmzjRdrZRQg NoYp9EdwcF1jAa4HKP4QJLBt9lP3aZs5v/G6Rgk3FzDjRHUTNffSgZwshGN9j0wOCXy3+pelg09aJ 0/DKCdgmQs3nLLui5R6u5iZNjbUCHByQbvdVzR99OcXn7Drr6ztQ2s4XHnaibyIS2xGXNevBE0crE kg8KFZPuA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3F-0000xC-KN; Fri, 06 Nov 2020 09:28:57 +0000 Received: from esa2.microchip.iphmx.com ([68.232.149.84]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay31-0000q5-5E for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654923; x=1636190923; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=jpoo8lswkA0HTqIME8fJoefP6IOmvgmdgVpF/Ams+UA=; b=uKvLFggsUdVdUwHEqgNviucVjkysVb6teDO2zcYqW6+UgGCTClE2heRU lnQFfeIHb77UJHDmY7fRhEZ0uKqQgNXv8/cz9A5+c2apn2DmjgC63XrqQ 4ZlAniobazj3YJDjD0XpHy+oXF/AR/0ahJX2FKjkFp9qXiKwnPCJheg0z 3scQ7kGCD3/G++Eo1bC57s60UHQe9cfn+yK1j6ZT+jjmlY2lZyskRuasj /g2pHGRSKfXza+8s1yAMAsOSpFTEJZFemCb3rQouA5xY5FMtnEDxjw1AW +xxIFcrQhkIiyNZfcrK0pPabH9smMIzQzHN6Z7HJ08bhCf+vZwNkHVDs+ A==; IronPort-SDR: RIrErMtxQQrdjS18MOl7nSMxJIZ58gX/nGIGWO6iFdoFl+HAzk9qXbsoYqIXFxIfG24vJ3EcVB Z8YEyEqrpcJ5TMUWYbor0nO94kZW7IN0AAH+tHdMX9HJ0meKvdxpiMn1xYqA4F1UFSskxe9F5w NEng4w8GyM67Xj/iseDg2VXDje5kE0o0X0lIVMBHeC7VdBBkwzclrZIy8W/TfG6BGNY+Tsq2gz S7nMVA5NshLpCoSCYLFg1dIQjVxTu6baFXhhL8eyC7wCbfdWmhMxiNQVsTorLJ6AZflXn9e3v/ +4c= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="95340994" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:41 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:40 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:35 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics Date: Fri, 6 Nov 2020 11:27:58 +0200 Message-ID: <1604654884-30339-6-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042843_362562_EDE20A7D X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Eugen Hristev This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain Signed-off-by: Eugen Hristev Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index d3c3469d47d9..d685e22b2014 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -775,13 +775,13 @@ static const struct clk_pll_characteristics pll_characteristics = { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { .output = { .min = 140000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3 }, + .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; /* MCK0 layout. */ static const struct clk_master_layout mck0_layout = { - .mask = 0x373, + .mask = 0x773, .pres_shift = 4, .offset = 0x28, }; From patchwork Fri Nov 6 09:27:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A654C388F2 for ; Fri, 6 Nov 2020 09:31:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 036A6208B3 for ; Fri, 6 Nov 2020 09:31:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FlvPzkfD"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="TMXpfb6E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 036A6208B3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+m1wT59+kSVz8+ISf6dbjMtzf53inqOqxTc0i1VHa10=; b=FlvPzkfDkH5p8LHI0A+Ta3vdM rQYJsQ4w9f0uIh3vq9RdQHIq14nQo9HftHxGT0EPU186ANdvy7zK6HJx7dZdwW1T0UpdY69U9u2CO 99c0CBnlYr1j9SLeb0vlzfdRWKs090gao2m8fo7JEDS69vdbhBh5QJezC51g+G6EEsdQlinTBbqFr HlAIXjvw2955VZcDoSw3V+6Rus82fRV4Xd5rpOFq3v0n0jLWo3NfUh9EUSNBIy/oAIPP8nqVc58AK iSBUV1NPVjoF8wYehUdhI7XF5y2qgkMOAU9bRADPvJzm0Wq/9BvXiKUla7oHi3p80g0++fkLJqxPV 74E4qd0yg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3R-000119-Ty; Fri, 06 Nov 2020 09:29:10 +0000 Received: from esa5.microchip.iphmx.com ([216.71.150.166]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay34-0000sh-Uz for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654927; x=1636190927; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=en16SVLAKrczUT/KRFuaGjEExoJsYxU+UhGvhOduIqk=; b=TMXpfb6Ei1NqnH8IWYuXtE2LVundYMMS7VtfF/5MCWCXSRAW8jTBWfbl 4IjzHiLGKWYxfQRxrdkU3aesbrObphPVZwByaRH1H3/Myjpc5xGJXZldN c5FttjgH+hbo0JDhgDAaXXSf9Q34H6weq+R6CMGa3R7a0rJ0/MvHTe19m 3ItgM7457/OzXj/q3m1cJ30ulb03NiMzWwCu/KsfMYGBornIm6PpHkANK W1CpTfZTCBFVGVlYCaPdC7G45nSPQq+kgL9rqQYi+ABJBW5T1H28bh1R5 8fqqIfGBFSHB9Te6bNikfJ/RiFgvx/z/gPJOR1LAv7a5UZuIrQATJKo3e A==; IronPort-SDR: haOP7QTXhcP1Y5Ev1/a+TYgCc6CpRDlzu872WyWQdruXIrQr2xvwihQjtKIfnWMH9BFXCx4m8Z tqixvFX+PWlwlXBO9P5VlD3TQqmBh63GM6X61eNtq6n1k0Icxnhl7vKgXi60cFmJg5Ybccrc4l pj52MmbZMzjJs1Fq4AW/yTkyXq54ari8687/SDHbHUCs6TL7t3CZ5mKhTMMUU+eIIUfvCN/FX3 D4w9Zor/dVDtjVSIc3+0GCqmo5R+OCAwIRKrk+fZIu6Us3Q3MwiOIyHU8md6W81lIP7gehrWKj G5M= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="97424028" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:45 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:41 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Date: Fri, 6 Nov 2020 11:27:59 +0200 Message-ID: <1604654884-30339-7-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042847_367795_77D3795E X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow runtime frequency changes for PLLs registered with proper flags. This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++++++++++------- drivers/clk/at91/pmc.h | 4 +- drivers/clk/at91/sam9x60.c | 13 +++-- drivers/clk/at91/sama7g5.c | 48 ++++++++++------- 4 files changed, 127 insertions(+), 40 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 78f458a7b2ef..6fe5d8530a0c 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -225,8 +225,51 @@ static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); + struct sam9x60_frac *frac = to_sam9x60_frac(core); + struct regmap *regmap = core->regmap; + unsigned long irqflags, clkflags = clk_hw_get_flags(hw); + unsigned int val, cfrac, cmul; + long ret; + + ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); + if (ret <= 0 || (clkflags & CLK_SET_RATE_GATE)) + return ret; + + spin_lock_irqsave(core->lock, irqflags); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, + core->id); + regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); + cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; + cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; + + if (cmul == frac->mul && cfrac == frac->frac) + goto unlock; + + regmap_write(regmap, AT91_PMC_PLL_CTRL1, + (frac->mul << core->layout->mul_shift) | + (frac->frac << core->layout->frac_shift)); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, + AT91_PMC_PLL_UPDT_UPDATE | core->id); + + regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, + AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, + AT91_PMC_PLL_CTRL0_ENLOCK | + AT91_PMC_PLL_CTRL0_ENPLL); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, + AT91_PMC_PLL_UPDT_UPDATE | core->id); - return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); + while (!sam9x60_pll_ready(regmap, core->id)) + cpu_relax(); + +unlock: + spin_unlock_irqrestore(core->lock, irqflags); + + return ret; } static const struct clk_ops sam9x60_frac_pll_ops = { @@ -378,9 +421,39 @@ static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); + struct regmap *regmap = core->regmap; + unsigned long irqflags, clkflags = clk_hw_get_flags(hw); + unsigned int val, cdiv; div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + if (clkflags & CLK_SET_RATE_GATE) + return 0; + + spin_lock_irqsave(core->lock, irqflags); + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, + core->id); + regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); + cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; + + /* Stop if nothing changed. */ + if (cdiv == div->div) + goto unlock; + + regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, + core->layout->div_mask, + (div->div << core->layout->div_shift)); + + regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, + AT91_PMC_PLL_UPDT_UPDATE | core->id); + + while (!sam9x60_pll_ready(regmap, core->id)) + cpu_relax(); + +unlock: + spin_unlock_irqrestore(core->lock, irqflags); + return 0; } @@ -398,12 +471,12 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical) + const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_frac *frac; struct clk_hw *hw; struct clk_init_data init; - unsigned long parent_rate, flags; + unsigned long parent_rate, irqflags; unsigned int val; int ret; @@ -418,9 +491,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, init.parent_names = &parent_name; init.num_parents = 1; init.ops = &sam9x60_frac_pll_ops; - init.flags = CLK_SET_RATE_GATE; - if (critical) - init.flags |= CLK_IS_CRITICAL; + init.flags = flags; frac->core.id = id; frac->core.hw.init = &init; @@ -429,7 +500,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, frac->core.regmap = regmap; frac->core.lock = lock; - spin_lock_irqsave(frac->core.lock, flags); + spin_lock_irqsave(frac->core.lock, irqflags); if (sam9x60_pll_ready(regmap, id)) { regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, id); @@ -457,7 +528,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, goto free; } } - spin_unlock_irqrestore(frac->core.lock, flags); + spin_unlock_irqrestore(frac->core.lock, irqflags); hw = &frac->core.hw; ret = clk_hw_register(NULL, hw); @@ -469,7 +540,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, return hw; free: - spin_unlock_irqrestore(frac->core.lock, flags); + spin_unlock_irqrestore(frac->core.lock, irqflags); kfree(frac); return hw; } @@ -478,12 +549,12 @@ struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical) + const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_div *div; struct clk_hw *hw; struct clk_init_data init; - unsigned long flags; + unsigned long irqflags; unsigned int val; int ret; @@ -498,10 +569,7 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, init.parent_names = &parent_name; init.num_parents = 1; init.ops = &sam9x60_div_pll_ops; - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT; - if (critical) - init.flags |= CLK_IS_CRITICAL; + init.flags = flags; div->core.id = id; div->core.hw.init = &init; @@ -510,14 +578,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, div->core.regmap = regmap; div->core.lock = lock; - spin_lock_irqsave(div->core.lock, flags); + spin_lock_irqsave(div->core.lock, irqflags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); - spin_unlock_irqrestore(div->core.lock, flags); + spin_unlock_irqrestore(div->core.lock, irqflags); hw = &div->core.hw; ret = clk_hw_register(NULL, hw); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0a9364bde339..bedcd85ad750 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -190,14 +190,14 @@ struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical); + const struct clk_pll_layout *layout, u32 flags); struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical); + const struct clk_pll_layout *layout, u32 flags); struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 3c4c95603595..e5094c69e606 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -228,13 +228,15 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", "mainck", sam9x60_pmc->chws[PMC_MAIN], 0, &plla_characteristics, - &pll_frac_layout, true); + &pll_frac_layout, + CLK_IS_CRITICAL | CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", "pllack_fracck", 0, &plla_characteristics, - &pll_div_layout, true); + &pll_div_layout, + CLK_IS_CRITICAL | CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -243,13 +245,16 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", "main_osc", main_osc_hw, 1, &upll_characteristics, - &pll_frac_layout, false); + &pll_frac_layout, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", "upllck_fracck", 1, &upll_characteristics, - &pll_div_layout, false); + &pll_div_layout, + CLK_SET_RATE_GATE | + CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index d685e22b2014..33faf7c6d9fb 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_layout_divio = { * @p: clock parent * @l: clock layout * @t: clock type - * @f: true if clock is critical and cannot be disabled + * @f: clock flags * @eid: export index in sama7g5->chws[] array */ static const struct { const char *n; const char *p; const struct clk_pll_layout *l; + u32 f; u8 t; - u8 c; u8 eid; } sama7g5_plls[][PLL_ID_MAX] = { [PLL_ID_CPU] = { @@ -111,13 +111,13 @@ static const struct { .p = "mainck", .l = &pll_layout_frac, .t = PLL_TYPE_FRAC, - .c = 1, }, + .f = CLK_IS_CRITICAL, }, { .n = "cpupll_divpmcck", .p = "cpupll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, + .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .eid = PMC_CPUPLL, }, }, @@ -126,13 +126,13 @@ static const struct { .p = "mainck", .l = &pll_layout_frac, .t = PLL_TYPE_FRAC, - .c = 1, }, + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, { .n = "syspll_divpmcck", .p = "syspll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, .eid = PMC_SYSPLL, }, }, @@ -141,55 +141,66 @@ static const struct { .p = "mainck", .l = &pll_layout_frac, .t = PLL_TYPE_FRAC, - .c = 1, }, + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, { .n = "ddrpll_divpmcck", .p = "ddrpll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, }, [PLL_ID_IMG] = { { .n = "imgpll_fracck", .p = "mainck", .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, }, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, { .n = "imgpll_divpmcck", .p = "imgpll_fracck", .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, }, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, }, [PLL_ID_BAUD] = { { .n = "baudpll_fracck", .p = "mainck", .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, }, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, { .n = "baudpll_divpmcck", .p = "baudpll_fracck", .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, }, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, }, [PLL_ID_AUDIO] = { { .n = "audiopll_fracck", .p = "main_xtal", .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, }, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, { .n = "audiopll_divpmcck", .p = "audiopll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, .eid = PMC_AUDIOPMCPLL, }, { .n = "audiopll_diviock", .p = "audiopll_fracck", .l = &pll_layout_divio, .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, .eid = PMC_AUDIOIOPLL, }, }, @@ -197,12 +208,15 @@ static const struct { { .n = "ethpll_fracck", .p = "main_xtal", .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, }, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, }, { .n = "ethpll_divpmcck", .p = "ethpll_fracck", .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, }, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, }, }, }; @@ -890,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_plls[i][j].p, parent_hw, i, &pll_characteristics, sama7g5_plls[i][j].l, - sama7g5_plls[i][j].c); + sama7g5_plls[i][j].f); break; case PLL_TYPE_DIV: @@ -899,7 +913,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_plls[i][j].p, i, &pll_characteristics, sama7g5_plls[i][j].l, - sama7g5_plls[i][j].c); + sama7g5_plls[i][j].f); break; default: From patchwork Fri Nov 6 09:28:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9040CC55178 for ; Fri, 6 Nov 2020 09:31:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF264208B3 for ; Fri, 6 Nov 2020 09:31:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EJR4Ctsq"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GXewzjYL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF264208B3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KxVaHZd4362xetNOmEJB4Ll604LN0vmyHaRc35Jj/mg=; b=EJR4CtsqxqDNTAdd30h2XGWU5 u2ZLuJQXcNZFffZCq12KYiymY9dAH+kUI7ovjN9npPgzGSG8R6Kgvr+gkcm/I3XxLkgDruoo1Qvqu L5gjarBlqJR/6ka4z++IpK1ogHSPUhN1OrE91VSpS0TgLdjGnN62gm7S3pIkY6tQoMdoL7HbrYH3u 1QxbN9AiacxbJgr8sQC4CDho7lwv/vo4GQhA5D0QZPzVAOfiwyXfBt9Y4jCSSixcTSXS2mC39c3K/ 9dmBCC86+lb0rJcOJ4SLSDEHno6ogAuy3ATd2eA9JruXN5xrkCJt7/SgfmK2PD7o/terX5VwTFxA+ sau7s8PlQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3j-0001Cp-3E; Fri, 06 Nov 2020 09:29:27 +0000 Received: from esa1.microchip.iphmx.com ([68.232.147.91]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay39-0000v1-WE for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654931; x=1636190931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=98KyUzL1G42E2CqSBWVfWz4SgFeNLS+jPn7ldi5xgeA=; b=GXewzjYLxZKosw1hZm/0gg3nyIzTcjR0jhi9yFOfOmM+DJxCwLY8JDxe AzbGzBNvwtTXRGxfBI1M8cqdBYCApb+Dy2qp6h1tfTVUYsDYEu7xb0gPH rsR0hsHjy0ngPE4xZjlsvNLiEdaO4sprua69njcJhIb+2/o7zS+grmNnv qTJOq2N8Qv4bg17NDtmhL0+kekSeZtONWxeVeqMcyuOmAQyZSZalJqSVU oO+QWxzA28lY4ErHQJVFIcxTHw1x/zwr90SZEPLe+5PGZfaueA6DXloRF uO8Or5Q85b8LjtQx1VSWP9fWd5IOUcgpektK9j/c8WF2jgu5S9OQsulp5 w==; IronPort-SDR: Qa6bBIhOXyAqYbQx8y42zLJHd7l2KphHnyk2UKMmYai3v5HUYFQTYBTsKFTkShwYGzdnN/U+6P DDNeprDKWznosYc9XBHCAycflZkzr5+ddWiGb76I0bqKr2yJ6V2hYUSsLqj7k10xVqlxBxalB4 zE4tZtFcX9nRd6GBzdJ8JSbpruTHZ3ukB37bxVaPFYIG7nLC1N19RPUBcCEo4YHsexwylAF3kp t6PJ/Q/MWntAD9peGebvU9BUxdupZTSdjTXrA+RqIqwwmSGJ/mkYX0iFNXMjZIhD05uAs/xphK iyY= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="102448295" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:49 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:45 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks Date: Fri, 6 Nov 2020 11:28:00 +0200 Message-ID: <1604654884-30339-8-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042852_303580_BD08AEF8 X-CRM114-Status: GOOD ( 13.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MCK0 is changed at runtime by DVFS. Due to this, since not all IPs are glitch free aware at MCK0 changes, remove MCK0 from parent list of other clocks (e.g. generic clock, programmable/system clock, MCKX). Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 33faf7c6d9fb..88ad0c70ca98 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -261,7 +261,7 @@ static const struct { .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, .ep_mux_table = { 5, 6, 7, }, .ep_count = 3, - .ep_chg_id = 6, }, + .ep_chg_id = 5, }, { .n = "mck4", .id = 4, @@ -294,7 +294,7 @@ static const struct { }; /* Mux table for programmable clocks. */ -static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, }; +static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; /** * Peripheral clock description @@ -417,7 +417,7 @@ static const struct { .pp = { "audiopll_divpmcck", }, .pp_mux_table = { 9, }, .pp_count = 1, - .pp_chg_id = 4, }, + .pp_chg_id = 3, }, { .n = "csi_gclk", .id = 33, @@ -529,7 +529,7 @@ static const struct { .pp = { "ethpll_divpmcck", }, .pp_mux_table = { 10, }, .pp_count = 1, - .pp_chg_id = 4, }, + .pp_chg_id = 3, }, { .n = "gmac1_gclk", .id = 52, @@ -561,7 +561,7 @@ static const struct { .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, .pp_mux_table = { 5, 9, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "i2smcc1_gclk", .id = 58, @@ -569,7 +569,7 @@ static const struct { .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, .pp_mux_table = { 5, 9, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "mcan0_gclk", .id = 61, @@ -711,7 +711,7 @@ static const struct { .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, .pp_mux_table = { 5, 8, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "sdmmc1_gclk", .id = 81, @@ -719,7 +719,7 @@ static const struct { .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, .pp_mux_table = { 5, 8, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "sdmmc2_gclk", .id = 82, @@ -727,7 +727,7 @@ static const struct { .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, .pp_mux_table = { 5, 8, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "spdifrx_gclk", .id = 84, @@ -735,7 +735,7 @@ static const struct { .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, .pp_mux_table = { 5, 9, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "spdiftx_gclk", .id = 85, @@ -743,7 +743,7 @@ static const struct { .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, .pp_mux_table = { 5, 9, }, .pp_count = 2, - .pp_chg_id = 5, }, + .pp_chg_id = 4, }, { .n = "tcb0_ch0_gclk", .id = 88, @@ -942,9 +942,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_names[0] = md_slck_name; parent_names[1] = td_slck_name; parent_names[2] = "mainck"; - parent_names[3] = "mck0"; for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { - u8 num_parents = 4 + sama7g5_mckx[i].ep_count; + u8 num_parents = 3 + sama7g5_mckx[i].ep_count; u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table), @@ -952,10 +951,10 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 4); - SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table, + SAMA7G5_INIT_TABLE(mux_table, 3); + SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, sama7g5_mckx[i].ep_count); - SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep, + SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, sama7g5_mckx[i].ep_count); hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, @@ -978,20 +977,19 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_names[0] = md_slck_name; parent_names[1] = td_slck_name; parent_names[2] = "mainck"; - parent_names[3] = "mck0"; - parent_names[4] = "syspll_divpmcck"; - parent_names[5] = "ddrpll_divpmcck"; - parent_names[6] = "imgpll_divpmcck"; - parent_names[7] = "baudpll_divpmcck"; - parent_names[8] = "audiopll_divpmcck"; - parent_names[9] = "ethpll_divpmcck"; + parent_names[3] = "syspll_divpmcck"; + parent_names[4] = "ddrpll_divpmcck"; + parent_names[5] = "imgpll_divpmcck"; + parent_names[6] = "baudpll_divpmcck"; + parent_names[7] = "audiopll_divpmcck"; + parent_names[8] = "ethpll_divpmcck"; for (i = 0; i < 8; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, - 10, i, + 9, i, &programmable_layout, sama7g5_prog_mux_table); if (IS_ERR(hw)) @@ -1028,9 +1026,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_names[0] = md_slck_name; parent_names[1] = td_slck_name; parent_names[2] = "mainck"; - parent_names[3] = "mck0"; for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { - u8 num_parents = 4 + sama7g5_gck[i].pp_count; + u8 num_parents = 3 + sama7g5_gck[i].pp_count; u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table), @@ -1038,10 +1035,10 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 4); - SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table, + SAMA7G5_INIT_TABLE(mux_table, 3); + SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, sama7g5_gck[i].pp_count); - SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp, + SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, sama7g5_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, From patchwork Fri Nov 6 09:28:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4C8CC2D0A3 for ; Fri, 6 Nov 2020 09:31:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B91F20B80 for ; Fri, 6 Nov 2020 09:31:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OswY3BWd"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="UpplPGLH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3B91F20B80 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hiIhEvgUBRDUg7p75xqwlXdhlLT9uRKXUSFC+I4X/s4=; b=OswY3BWdKZJf1zJOCDcQvY7v3 zPotatFWcpQmWMRUKf+lSpewDwsXQuLMemIFntiNAc8hP/6wI+SCAEMnomCDrTfpw/0wZsxPFCh7c vQM40td2kaUTWXOZI+dN5W7ptufgQP3KBlJjBgyOcqUw8HfRvs6RSPmu0gjQtLo2geQ8UzMnBW5WX oDnohLuzoiFtt6m6SOFtgfT6GyLR2JMqZiwvkRXCZv0ua293n0HjEnvQHYpTf6N86h+fplxRVj3WU FfmwVeKrU1zp8ymA9EKbj9Fa4y3e+AwQDpkwqHRESjxP7fPBY0MrpMi3OxALFHx4nPBtPE9c4n/e8 lM4wnAYyA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay48-0001KF-9i; Fri, 06 Nov 2020 09:29:52 +0000 Received: from esa1.microchip.iphmx.com ([68.232.147.91]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3D-0000v1-Rl for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:28:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654935; x=1636190935; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=jjMRv7q9dqqrQGmbGnrRipfXGN0KNE4iUh7ba8SylbQ=; b=UpplPGLHt7b4Y9RgOWpUa+/UsD3w5iPu9DTOk1ATEwKDLtyadjDztMan whEbm7BJK/71GGdQKrJ2xl0x2PbWl6lRcfQaNZlQQ54fUMEe5SwOUDx90 3Lc7bNfZG2T+WqI+j6G3aoRc/vlHQDOaP8B3ZMNR/wtyubKa+YpjcgzzZ l0oZ+1xYPrV3vAju6J8wdWkf1E37GGuLu0kP86D0c5gVNZ3SHFPA90Wtv rZD5IO56o+3gD3bvB6tXR9CTU20Uso0/v5N0pVctYOVdzRV+XzFckOPPG SIVMXBB391JyUngwO4KMSeBypQMQxMQgFQTyrKaEC9DOOD6Sqle/eKnS8 Q==; IronPort-SDR: tj1sQpRLPM1bEAO0MNm5WiMkq93uhUV9qLzGiQ4hn+/yRpjFKeQnj/cuHd9T0DjM1fd5Jt6ShE 2yEbjmmsX1sRtxZfDfScL8/C0G7eE8Se/MiYiDddC3s8N7WXaSXJ35hi0mMmk4GiqELyEcCGnk 18/pMdmdh77LLfdtJu7K7z/y9i+/YddxjlCixRpt6kA6gn02yGW7YArqyWru697x/qXBz7qI2H Gnqt04JZRsRxHnhAcktGXHwSRfuwATcy66gA9BJPkkBFS5o0udFHwIgW3cghviVx5UuQ7j9mal WHU= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="102448321" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:28:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:28:54 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:50 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate Date: Fri, 6 Nov 2020 11:28:01 +0200 Message-ID: <1604654884-30339-9-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042856_093089_3432BCAA X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 88ad0c70ca98..662e667d1098 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -788,7 +788,7 @@ static const struct clk_pll_characteristics pll_characteristics = { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, + .output = { .min = 50000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; From patchwork Fri Nov 6 09:28:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5ACDC2D0A3 for ; Fri, 6 Nov 2020 09:31:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AF62208FE for ; Fri, 6 Nov 2020 09:31:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LmBSa1k7"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aKAsl7gG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AF62208FE Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RJ2PXi/5H8A73IcUypBxcmEMcpL/902EvD3/sG5EO7k=; b=LmBSa1k7lalRSpZPpu4pyz0RX d7gcIkRcb33N9882Tb+EeHxnsJR25ipyiw78HGHTPxugKwUEp8Gx3BFbvYDsEEGeFG30rz8zhzquW VELQWMtkknRBU08xo1OPFtSpwrVIgj0+26WOy0YsFCyimgc2Y58vTp2wp4378aJbxUplyPybt+PeE J3Q9b7UZmmCMqrAAGGjYpH0xvL4fwsrLeytPAgxJkMz2zJSzMWZSmlPqtUi9JYxynIYnckt7NQRrp c2oH06FRqOdfvyZCGWkGLoGeDVizr4C4S0xvaA/X1Vu+IzSmlXu8hiE2L8y/Ze6zHQaOKxRN6xR+x 9p2l+lx2g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay4L-0001UF-Pl; Fri, 06 Nov 2020 09:30:06 +0000 Received: from esa6.microchip.iphmx.com ([216.71.154.253]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3U-00015O-5s for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:29:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654952; x=1636190952; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=LpIGdMXUlYBgp05KdV0472lXFhdS6mqxCl5tVnVr47M=; b=aKAsl7gGPZ72y6kZ15lvajP0kPaJ6AjpY9suKQ18N44Ye7RR53YAmxKc ajd7xz1W/DQnx7VqARc4YXG7fuR0SP+2TN3SFt3MZ63OGqDhzn6uYmYNN UEePDXq7/0GbnIb8Jdpw3RjmDNFPfuNmaaSre1pAlwPWt4g0bwU3qXyuA E6RmrHjCpgG1tFfSBQn6GXRSQcSST8Ss97ujh9d5E/IqFpJGbcw01t+YT xQXqsP/UwizEb1261P2uJZJ8s0e0G7/hwduh9S8kQCcNXliC0NHTm07Kc S2dpRA/KmIqXojEBY8TDjIzDAkhfBGibp1IMCfF6piX6oRJO0NL0xN2ny Q==; IronPort-SDR: 8bDfnoA8KAq+DUpq9a4Z8FNs32ZJgL2I7QvnrltMAbdRbur/wdRx9dWSY1pNJ32CzzjXZvPPya VrGrkfW820ob0wV0HMvnDYidZH1yYLZnlOOWEJcKa2x4gCBXqRUCZFCo3O6wcOA6cMJQX9I5Kc UOY6iXP30P1WgbAyPKBlgVtnjklXcw6bYfBEVujmE3HRaIYQEe7w7fMSrOQ/5B4rCrGISY0+ve N3e6Q/IHVg0hFDWrreurZMNbLsGaOc95qQ8H/eaLFubJ/gA8+QDYcSzw49OzOnaX15heqyqJJD rYM= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32677798" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:29:00 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:29:00 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:28:55 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz Date: Fri, 6 Nov 2020 11:28:02 +0200 Message-ID: <1604654884-30339-10-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042912_427863_F55F3C58 X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 662e667d1098..3924f256da67 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_layout_divio = { .endiv_shift = 30, }; +/* + * CPU PLL output range. + * Notice: The upper limit has been setup to 1000000002 due to hardware + * block which cannot output exactly 1GHz. + */ +static const struct clk_range cpu_pll_outputs[] = { + { .min = 2343750, .max = 1000000002 }, +}; + +/* PLL output range. */ +static const struct clk_range pll_outputs[] = { + { .min = 2343750, .max = 1200000000 }, +}; + +/* CPU PLL characteristics. */ +static const struct clk_pll_characteristics cpu_pll_characteristics = { + .input = { .min = 12000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(cpu_pll_outputs), + .output = cpu_pll_outputs, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics pll_characteristics = { + .input = { .min = 12000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(pll_outputs), + .output = pll_outputs, +}; + /** * PLL clocks description * @n: clock name * @p: clock parent * @l: clock layout + * @c: clock characteristics * @t: clock type * @f: clock flags * @eid: export index in sama7g5->chws[] array @@ -102,6 +131,7 @@ static const struct { const char *n; const char *p; const struct clk_pll_layout *l; + const struct clk_pll_characteristics *c; u32 f; u8 t; u8 eid; @@ -110,12 +140,14 @@ static const struct { { .n = "cpupll_fracck", .p = "mainck", .l = &pll_layout_frac, + .c = &cpu_pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_IS_CRITICAL, }, { .n = "cpupll_divpmcck", .p = "cpupll_fracck", .l = &pll_layout_divpmc, + .c = &cpu_pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .eid = PMC_CPUPLL, }, @@ -125,12 +157,14 @@ static const struct { { .n = "syspll_fracck", .p = "mainck", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, { .n = "syspll_divpmcck", .p = "syspll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, .eid = PMC_SYSPLL, }, @@ -140,12 +174,14 @@ static const struct { { .n = "ddrpll_fracck", .p = "mainck", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, { .n = "ddrpll_divpmcck", .p = "ddrpll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, }, @@ -154,12 +190,14 @@ static const struct { { .n = "imgpll_fracck", .p = "mainck", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, { .n = "imgpll_divpmcck", .p = "imgpll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, @@ -169,12 +207,14 @@ static const struct { { .n = "baudpll_fracck", .p = "mainck", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, { .n = "baudpll_divpmcck", .p = "baudpll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, @@ -184,12 +224,14 @@ static const struct { { .n = "audiopll_fracck", .p = "main_xtal", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, { .n = "audiopll_divpmcck", .p = "audiopll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -198,6 +240,7 @@ static const struct { { .n = "audiopll_diviock", .p = "audiopll_fracck", .l = &pll_layout_divio, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -208,12 +251,14 @@ static const struct { { .n = "ethpll_fracck", .p = "main_xtal", .l = &pll_layout_frac, + .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, { .n = "ethpll_divpmcck", .p = "ethpll_fracck", .l = &pll_layout_divpmc, + .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, @@ -774,18 +819,6 @@ static const struct { .pp_chg_id = INT_MIN, }, }; -/* PLL output range. */ -static const struct clk_range pll_outputs[] = { - { .min = 2343750, .max = 1200000000 }, -}; - -/* PLL characteristics. */ -static const struct clk_pll_characteristics pll_characteristics = { - .input = { .min = 12000000, .max = 50000000 }, - .num_output = ARRAY_SIZE(pll_outputs), - .output = pll_outputs, -}; - /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { .output = { .min = 50000000, .max = 200000000 }, @@ -902,7 +935,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, sama7g5_plls[i][j].p, parent_hw, i, - &pll_characteristics, + sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); break; @@ -911,7 +944,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, sama7g5_plls[i][j].p, i, - &pll_characteristics, + sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); break; From patchwork Fri Nov 6 09:28:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D1D3C388F2 for ; Fri, 6 Nov 2020 09:31:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CE58208B3 for ; Fri, 6 Nov 2020 09:31:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="qQYg9EeM"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="eURhXury" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CE58208B3 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=j6hAnUQ0EkfDPVxglV0TF4WY/lIRWW9Cd7O4zR0muLE=; b=qQYg9EeMpAw0qGxmcuS5a7WQT tmo00nQn6SKwePr34M4i2vhy3JjmsxRpEOK0x3tGvu2BakaruiL+ndQ3I4c0gIMWFnlNEL+ePRSmc TW+VMVCYTqJ7gN/xqXAwoRxG7ofqmEkx4NmSdC3NDphJwz6GBRbqoKA/9vPjUDyeySykOSpiy5xX8 wIXO3YwnjGykoKBAQr7Vi4wLWqtFNRGJz5KThGZ8M6AvxzbEyt+USPGBCCm8DHR5ue4gu2aabtCF5 mYUVCZuhOtHV8MXPaD0sqPsAMrXS7qwFacBG3J40f2FqLtf3jvF6Sn1pEJq+yXuWyhjU1ofJqpq1X a9WlFlLiw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay4o-0001m6-NS; Fri, 06 Nov 2020 09:30:34 +0000 Received: from esa6.microchip.iphmx.com ([216.71.154.253]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3V-00015O-Uj for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:29:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654953; x=1636190953; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=jRySOwngjZXetLWtyCkZ3n2Rb4qk8st7rZKktQp9ai4=; b=eURhXuryqTh9mvyHGZN/eJ8zoy3vAJuSANTV2DDyE1Rn9ALOKVidnchi 3fH/tl4fNe6Bko4JMKFEg3koOzmdV/poQiKFKF6I3RhX8UCuXkd3cV6ET ucievrd6WgjGPACVWGHwcykZo3IuJYs8G7B+urijJT/9586QBOd8hQHcl IQR3fAvDWYfFNKNENoFu7yqKDXHqVFgW9hONSRhPWAko1FozMyl7sLdIK CrOWGISnhbF562b52ZlAKdAgIK4eXnqxDhZILm0vbOx4mbUv3BdTka4FQ BIAzSQSGDtbA1nzxn8KCmDRsmg60CsH8OyPU9n3YPS52SJ36quRe7GDWr w==; IronPort-SDR: MaGgyc6S4wd+Js00sejIIvK7TLgA3+8nXdO9s/SzoT2vjvzdJFtUUxLrPljfhlnIPG5oxvOdab F5XtKvJqueztZOF8uqBWCLpTzsOCgyYqfbOcnuc1eRnwqArYeHbpr0vQqf6wZ4LZydGSuVn+ob tgF6GbktHhj5BqoPATdw46C/hT9DqEXTj0TxQTDFvJTI7SofDQSfFyPS92YDdHBK7xSIBY1LgF /532vyl97uOFmWaykMGtbeo7AvUKGLDfIobO/+l7SB909zq0a+QyeEnxvyIh5QnYPmycoMusac +vw= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32677812" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:29:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:29:05 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:29:00 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 10/11] clk: at91: clk-master: re-factor master clock Date: Fri, 6 Nov 2020 11:28:03 +0200 Message-ID: <1604654884-30339-11-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042914_344831_89FEE505 X-CRM114-Status: GOOD ( 16.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Re-factor master clock driver by splitting it into 2 clocks: prescaller and divider clocks. Based on registered clock flags the prescaler's rate could be changed at runtime. This is necessary for platforms supporting DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/at91rm9200.c | 21 ++- drivers/clk/at91/at91sam9260.c | 26 +++- drivers/clk/at91/at91sam9g45.c | 32 ++-- drivers/clk/at91/at91sam9n12.c | 36 +++-- drivers/clk/at91/at91sam9rl.c | 23 ++- drivers/clk/at91/at91sam9x5.c | 28 +++- drivers/clk/at91/clk-master.c | 326 +++++++++++++++++++++++++++++++++++------ drivers/clk/at91/dt-compat.c | 15 +- drivers/clk/at91/pmc.h | 16 +- drivers/clk/at91/sam9x60.c | 23 ++- drivers/clk/at91/sama5d2.c | 42 ++++-- drivers/clk/at91/sama5d3.c | 38 +++-- drivers/clk/at91/sama5d4.c | 40 +++-- drivers/clk/at91/sama7g5.c | 13 +- 14 files changed, 531 insertions(+), 148 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index 2c3d8e6ca63c..0fad1009f315 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(rm9200_mck_lock); + struct sck { char *n; char *p; @@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91rm9200_master_layout, - &rm9200_mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91rm9200_master_layout, + &rm9200_mck_characteristics, + &rm9200_mck_lock, CLK_SET_RATE_GATE, + INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91rm9200_master_layout, + &rm9200_mck_characteristics, + &rm9200_mck_lock, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91rm9200_periphck[i].n, - "masterck", + "masterck_div", at91rm9200_periphck[i].id); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index bb81ff731ad8..ceb5495f723a 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -32,6 +32,8 @@ struct at91sam926x_data { bool has_slck; }; +static DEFINE_SPINLOCK(at91sam9260_mck_lock); + static const struct clk_master_characteristics sam9260_mck_characteristics = { .output = { .min = 0, .max = 105000000 }, .divisors = { 1, 2, 4, 0 }, @@ -218,8 +220,8 @@ static const struct sck at91sam9261_systemck[] = { { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, { .n = "pck3", .p = "prog3", .id = 11 }, - { .n = "hclk0", .p = "masterck", .id = 16 }, - { .n = "hclk1", .p = "masterck", .id = 17 }, + { .n = "hclk0", .p = "masterck_div", .id = 16 }, + { .n = "hclk1", .p = "masterck_div", .id = 17 }, }; static const struct pck at91sam9261_periphck[] = { @@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91rm9200_master_layout, - data->mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91rm9200_master_layout, + data->mck_characteristics, + &at91sam9260_mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91rm9200_master_layout, + data->mck_characteristics, + &at91sam9260_mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, for (i = 0; i < data->num_pck; i++) { hw = at91_clk_register_peripheral(regmap, data->pck[i].n, - "masterck", + "masterck_div", data->pck[i].id); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index cb4a406ed15d..0214333dedd3 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(at91sam9g45_mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, @@ -40,10 +42,10 @@ static const struct { char *p; u8 id; } at91sam9g45_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, }; struct pck { @@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91rm9200_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91rm9200_master_layout, + &mck_characteristics, + &at91sam9g45_mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91rm9200_master_layout, + &mck_characteristics, + &at91sam9g45_mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; @@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91sam9g45_periphck[i].n, - "masterck", + "masterck_div", at91sam9g45_periphck[i].id); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 93f7eb216122..f9db5316a7f1 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(at91sam9n12_mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, @@ -54,12 +56,12 @@ static const struct { char *p; u8 id; } at91sam9n12_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, - { .n = "lcdck", .p = "masterck", .id = 3 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "lcdck", .p = "masterck_div", .id = 3 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, }; static const struct clk_pcr_layout at91sam9n12_pcr_layout = { @@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "pllbck"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91sam9x5_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91sam9x5_master_layout, + &mck_characteristics, + &at91sam9n12_mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, + &at91sam9n12_mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "pllbck"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; @@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9n12_pcr_layout, at91sam9n12_periphck[i].n, - "masterck", + "masterck_div", at91sam9n12_periphck[i].id, &range, INT_MIN); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index a343eb69bb35..66736e03cfef 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(sam9rl_mck_lock); + static const struct clk_master_characteristics sam9rl_mck_characteristics = { .output = { .min = 0, .max = 94000000 }, .divisors = { 1, 2, 4, 0 }, @@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91rm9200_master_layout, - &sam9rl_mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91rm9200_master_layout, + &sam9rl_mck_characteristics, + &sam9rl_mck_lock, CLK_SET_RATE_GATE, + INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91rm9200_master_layout, + &sam9rl_mck_characteristics, + &sam9rl_mck_lock, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; @@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91sam9rl_periphck[i].n, - "masterck", + "masterck_div", at91sam9rl_periphck[i].id); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 22b9aad9efb8..79b9d3667228 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, @@ -41,7 +43,7 @@ static const struct { char *p; u8 id; } at91sam9x5_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, { .n = "smdck", .p = "smdclk", .id = 4 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, @@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91sam9x5_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; @@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, } if (has_lcdck) { - hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3); + hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3); if (IS_ERR(hw)) goto err_free; @@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, - "masterck", + "masterck_div", at91sam9x5_periphck[i].id, &range, INT_MIN); if (IS_ERR(hw)) @@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, - "masterck", + "masterck_div", extra_pcks[i].id, &range, INT_MIN); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index aafd003b30cf..32af4f65bb23 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -58,83 +58,308 @@ static inline bool clk_master_ready(struct clk_master *master) static int clk_master_prepare(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); + unsigned long flags; + + spin_lock_irqsave(master->lock, flags); while (!clk_master_ready(master)) cpu_relax(); + spin_unlock_irqrestore(master->lock, flags); + return 0; } static int clk_master_is_prepared(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); + unsigned long flags; + bool status; - return clk_master_ready(master); + spin_lock_irqsave(master->lock, flags); + status = clk_master_ready(master); + spin_unlock_irqrestore(master->lock, flags); + + return status; } -static unsigned long clk_master_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - u8 pres; u8 div; - unsigned long rate = parent_rate; + unsigned long flags, rate = parent_rate; struct clk_master *master = to_clk_master(hw); const struct clk_master_layout *layout = master->layout; const struct clk_master_characteristics *characteristics = master->characteristics; unsigned int mckr; + spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); + mckr &= layout->mask; - pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; - if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) - rate /= 3; - else - rate >>= pres; - rate /= characteristics->divisors[div]; if (rate < characteristics->output.min) - pr_warn("master clk is underclocked"); + pr_warn("master clk div is underclocked"); else if (rate > characteristics->output.max) - pr_warn("master clk is overclocked"); + pr_warn("master clk div is overclocked"); return rate; } -static u8 clk_master_get_parent(struct clk_hw *hw) +static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); + const struct clk_master_characteristics *characteristics = + master->characteristics; + unsigned long flags; + int div, i; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) + return 0; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > ARRAY_SIZE(characteristics->divisors)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { + if (!characteristics->divisors[i]) + break; + + if (div == characteristics->divisors[i]) { + div = i; + break; + } + } + + if (i == ARRAY_SIZE(characteristics->divisors)) + return -EINVAL; + + spin_lock_irqsave(master->lock, flags); + regmap_update_bits(master->regmap, master->layout->offset, + (MASTER_DIV_MASK << MASTER_DIV_SHIFT), + (div << MASTER_DIV_SHIFT)); + while (!clk_master_ready(master)) + cpu_relax(); + spin_unlock_irqrestore(master->lock, flags); + + return 0; +} + +static int clk_master_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_master *master = to_clk_master(hw); + const struct clk_master_characteristics *characteristics = + master->characteristics; + struct clk_hw *parent; + unsigned long parent_rate, tmp_rate, best_rate = 0; + int i, best_diff = INT_MIN, tmp_diff; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) + return -EOPNOTSUPP; + + parent = clk_hw_get_parent(hw); + if (!parent) + return -EINVAL; + + parent_rate = clk_hw_get_rate(parent); + if (!parent_rate) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { + if (!characteristics->divisors[i]) + break; + + tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, + characteristics->divisors[i]); + tmp_diff = abs(tmp_rate - req->rate); + + if (!best_rate || best_diff > tmp_diff) { + best_diff = tmp_diff; + best_rate = tmp_rate; + } + + if (!best_diff) + break; + } + + req->best_parent_rate = best_rate; + req->best_parent_hw = parent; + req->rate = best_rate; + + return 0; +} + +static const struct clk_ops master_div_ops = { + .prepare = clk_master_prepare, + .is_prepared = clk_master_is_prepared, + .recalc_rate = clk_master_div_recalc_rate, + .determine_rate = clk_master_div_determine_rate, + .set_rate = clk_master_div_set_rate, +}; + +static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, + struct clk_hw *parent, + unsigned long parent_rate, + long *best_rate, + long *best_diff, + u32 div) +{ + unsigned long tmp_rate, tmp_diff; + + if (div == MASTER_PRES_MAX) + tmp_rate = parent_rate / 3; + else + tmp_rate = parent_rate >> div; + + tmp_diff = abs(req->rate - tmp_rate); + + if (*best_diff < 0 || *best_diff >= tmp_diff) { + *best_rate = tmp_rate; + *best_diff = tmp_diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } +} + +static int clk_master_pres_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_master *master = to_clk_master(hw); + struct clk_rate_request req_parent = *req; + const struct clk_master_characteristics *characteristics = + master->characteristics; + struct clk_hw *parent; + long best_rate = LONG_MIN, best_diff = LONG_MIN; + u32 pres; + int i; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) + return 0; + + if (master->chg_pid < 0) + return -EOPNOTSUPP; + + parent = clk_hw_get_parent_by_index(hw, master->chg_pid); + if (!parent) + return -EOPNOTSUPP; + + for (i = 0; i <= MASTER_PRES_MAX; i++) { + if (characteristics->have_div3_pres && i == MASTER_PRES_MAX) + pres = 3; + else + pres = 1 << i; + + req_parent.rate = req->rate * pres; + if (__clk_determine_rate(parent, &req_parent)) + continue; + + clk_sama7g5_master_best_diff(req, parent, req_parent.rate, + &best_diff, &best_rate, pres); + if (!best_diff) + break; + } + + return 0; +} + +static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_master *master = to_clk_master(hw); + unsigned long flags; + unsigned int pres; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) + return 0; + + pres = DIV_ROUND_CLOSEST(parent_rate, rate); + if (pres > MASTER_PRES_MAX) + return -EINVAL; + + else if (pres == 3) + pres = MASTER_PRES_MAX; + else + pres = ffs(pres) - 1; + + spin_lock_irqsave(master->lock, flags); + regmap_update_bits(master->regmap, master->layout->offset, + (MASTER_PRES_MASK << master->layout->pres_shift), + (pres << master->layout->pres_shift)); + + while (!clk_master_ready(master)) + cpu_relax(); + spin_unlock_irqrestore(master->lock, flags); + + return 0; +} + +static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_master *master = to_clk_master(hw); + const struct clk_master_characteristics *characteristics = + master->characteristics; + unsigned long flags; + unsigned int val, pres; + + spin_lock_irqsave(master->lock, flags); + regmap_read(master->regmap, master->layout->offset, &val); + spin_unlock_irqrestore(master->lock, flags); + + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; + if (pres == 3 && characteristics->have_div3_pres) + pres = 3; + else + pres = (1 << pres); + + return DIV_ROUND_CLOSEST_ULL(parent_rate, pres); +} + +static u8 clk_master_pres_get_parent(struct clk_hw *hw) +{ + struct clk_master *master = to_clk_master(hw); + unsigned long flags; unsigned int mckr; + spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); + spin_unlock_irqrestore(master->lock, flags); return mckr & AT91_PMC_CSS; } -static const struct clk_ops master_ops = { +static const struct clk_ops master_pres_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, - .recalc_rate = clk_master_recalc_rate, - .get_parent = clk_master_get_parent, + .determine_rate = clk_master_pres_determine_rate, + .recalc_rate = clk_master_pres_recalc_rate, + .get_parent = clk_master_pres_get_parent, + .set_rate = clk_master_pres_set_rate, }; -struct clk_hw * __init -at91_clk_register_master(struct regmap *regmap, +static struct clk_hw * __init +at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, const struct clk_master_layout *layout, - const struct clk_master_characteristics *characteristics) + const struct clk_master_characteristics *characteristics, + const struct clk_ops *ops, spinlock_t *lock, u32 flags, + int chg_pid) { struct clk_master *master; struct clk_init_data init; struct clk_hw *hw; int ret; - if (!name || !num_parents || !parent_names) + if (!name || !num_parents || !parent_names || !lock) return ERR_PTR(-EINVAL); master = kzalloc(sizeof(*master), GFP_KERNEL); @@ -142,15 +367,17 @@ at91_clk_register_master(struct regmap *regmap, return ERR_PTR(-ENOMEM); init.name = name; - init.ops = &master_ops; + init.ops = ops; init.parent_names = parent_names; init.num_parents = num_parents; - init.flags = 0; + init.flags = flags; master->hw.init = &init; master->layout = layout; master->characteristics = characteristics; master->regmap = regmap; + master->chg_pid = chg_pid; + master->lock = lock; hw = &master->hw; ret = clk_hw_register(NULL, &master->hw); @@ -162,6 +389,35 @@ at91_clk_register_master(struct regmap *regmap, return hw; } +struct clk_hw * __init +at91_clk_register_master_pres(struct regmap *regmap, + const char *name, int num_parents, + const char **parent_names, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, + spinlock_t *lock, u32 flags, int chg_pid) +{ + return at91_clk_register_master_internal(regmap, name, num_parents, + parent_names, layout, + characteristics, + &master_pres_ops, + lock, flags, chg_pid); +} + +struct clk_hw * __init +at91_clk_register_master_div(struct regmap *regmap, + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, + spinlock_t *lock, u32 flags) +{ + return at91_clk_register_master_internal(regmap, name, 1, + &parent_name, layout, + characteristics, + &master_div_ops, + lock, flags, -EINVAL); +} + static unsigned long clk_sama7g5_master_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -171,30 +427,6 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); } -static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, - struct clk_hw *parent, - unsigned long parent_rate, - long *best_rate, - long *best_diff, - u32 div) -{ - unsigned long tmp_rate, tmp_diff; - - if (div == MASTER_PRES_MAX) - tmp_rate = parent_rate / 3; - else - tmp_rate = parent_rate >> div; - - tmp_diff = abs(req->rate - tmp_rate); - - if (*best_diff < 0 || *best_diff >= tmp_diff) { - *best_rate = tmp_rate; - *best_diff = tmp_diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } -} - static int clk_sama7g5_master_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index a50084de97d4..a97b99c2dc12 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -24,6 +24,8 @@ #define GCK_INDEX_DT_AUDIO_PLL 5 +static DEFINE_SPINLOCK(mck_lock); + #ifdef CONFIG_HAVE_AT91_AUDIO_PLL static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) { @@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_node *np, if (IS_ERR(regmap)) return; - hw = at91_clk_register_master(regmap, name, num_parents, - parent_names, layout, - characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, + parent_names, layout, + characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto out_free_characteristics; + + hw = at91_clk_register_master_div(regmap, name, "masterck_pres", + layout, characteristics, + &mck_lock, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index bedcd85ad750..a49076c804a9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, int num_parents); struct clk_hw * __init -at91_clk_register_master(struct regmap *regmap, const char *name, - int num_parents, const char **parent_names, - const struct clk_master_layout *layout, - const struct clk_master_characteristics *characteristics); +at91_clk_register_master_pres(struct regmap *regmap, const char *name, + int num_parents, const char **parent_names, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, + spinlock_t *lock, u32 flags, int chg_pid); + +struct clk_hw * __init +at91_clk_register_master_div(struct regmap *regmap, const char *name, + const char *parent_names, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics, + spinlock_t *lock, u32 flags); struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e5094c69e606..dc88b752530b 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -8,6 +8,7 @@ #include "pmc.h" static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 140000000, .max = 200000000 }, @@ -76,11 +77,11 @@ static const struct { char *p; u8 id; } sam9x60_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "qspick", .p = "masterck", .id = 19 }, + { .n = "qspick", .p = "masterck_div", .id = 19 }, }; static const struct { @@ -263,9 +264,17 @@ static void __init sam9x60_pmc_setup(struct device_node *np) parent_names[0] = md_slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack_divck"; - hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, - &sam9x60_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, + parent_names, &sam9x60_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", &sam9x60_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -281,7 +290,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) parent_names[0] = md_slck_name; parent_names[1] = td_slck_name; parent_names[2] = "mainck"; - parent_names[3] = "masterck"; + parent_names[3] = "masterck_div"; parent_names[4] = "pllack_divck"; parent_names[5] = "upllck_divck"; for (i = 0; i < 2; i++) { @@ -313,7 +322,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_periphck[i].n, - "masterck", + "masterck_div", sam9x60_periphck[i].id, &range, INT_MIN); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 8b220762941a..9a5cbc7cd55a 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 124000000, .max = 166000000 }, .divisors = { 1, 2, 4, 3 }, @@ -40,14 +42,14 @@ static const struct { char *p; u8 id; } sama5d2_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, - { .n = "lcdck", .p = "masterck", .id = 3 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, - { .n = "iscck", .p = "masterck", .id = 18 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "lcdck", .p = "masterck_div", .id = 3 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "iscck", .p = "masterck_div", .id = 18 }, }; static const struct { @@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91sam9x5_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_MCK] = hw; - hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); + hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); if (IS_ERR(hw)) goto err_free; @@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; parent_names[5] = "audiopll_pmcck"; for (i = 0; i < 3; i++) { char name[6]; @@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, - "masterck", + "masterck_div", sama5d2_periphck[i].id, &range, INT_MIN); if (IS_ERR(hw)) @@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; parent_names[5] = "audiopll_pmcck"; for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 7c6e0a5b9dc8..87009ee8effc 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 166000000 }, .divisors = { 1, 2, 4, 3 }, @@ -40,14 +42,14 @@ static const struct { char *p; u8 id; } sama5d3_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, - { .n = "lcdck", .p = "masterck", .id = 3 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "lcdck", .p = "masterck_div", .id = 3 }, + { .n = "smdck", .p = "smdclk", .id = 4 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, }; static const struct { @@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91sam9x5_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; @@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 3; i++) { char name[6]; @@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, - "masterck", + "masterck_div", sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN); diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 92d8d4141b43..57fff790188b 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -7,6 +7,8 @@ #include "pmc.h" +static DEFINE_SPINLOCK(mck_lock); + static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 125000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3 }, @@ -39,14 +41,14 @@ static const struct { char *p; u8 id; } sama5d4_systemck[] = { - { .n = "ddrck", .p = "masterck", .id = 2 }, - { .n = "lcdck", .p = "masterck", .id = 3 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "ddrck", .p = "masterck_div", .id = 2 }, + { .n = "lcdck", .p = "masterck_div", .id = 3 }, + { .n = "smdck", .p = "smdclk", .id = 4 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, }; static const struct { @@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, - &at91sam9x5_master_layout, - &mck_characteristics); + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, INT_MIN); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", + &at91sam9x5_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->chws[PMC_MCK] = hw; - hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); + hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); if (IS_ERR(hw)) goto err_free; @@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "masterck"; + parent_names[4] = "masterck_div"; for (i = 0; i < 3; i++) { char name[6]; @@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periphck[i].n, - "masterck", + "masterck_div", sama5d4_periphck[i].id, &range, INT_MIN); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 3924f256da67..be32d9b88d89 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -32,6 +32,7 @@ } while (0) static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); /** @@ -965,8 +966,16 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "cpupll_divpmcck"; parent_names[3] = "syspll_divpmcck"; - hw = at91_clk_register_master(regmap, "mck0", 4, parent_names, - &mck0_layout, &mck0_characteristics); + hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, + CLK_SET_RATE_PARENT, 0); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, 0); if (IS_ERR(hw)) goto err_free; From patchwork Fri Nov 6 09:28:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11886543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F73BC388F2 for ; Fri, 6 Nov 2020 09:32:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86149208FE for ; Fri, 6 Nov 2020 09:32:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oPShx4uM"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aRRVyXtU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 86149208FE Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MYTJIEGMDKTl9DWkVFGkwKfi0roRl20vRJuviPPkLoI=; b=oPShx4uMfSAJvBSDmqV+Yb3O0 mpROYYyo6HOfjNHm4i1/XB71WErc2njTRRTIYepEwwYdzlXm6UP22PvwC7Kh+T3CXX5Xu16sc1OzR 4EO3s6nJ4POlwSyY5Zabp7SPd7iYQVS3dDqNFXYIdfNCy0Cg9Zwoqd7oTBE8SDhTVDRUhlPo3jHgH +L1hKUGA9ndm6QzvrJaHsr7Q2/u5KPe2Ko6ERI/WnncPO4K/heU54d6y/1wnJafMAugqBy39q3a7D GdhwqraZBbvlSefL4F1YTB9ktSlPp988RTcyfR69WwpbnZpRWiLuNg9DUirGptwjRMQRCCIpv3Wze mUmHWmuXw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay4b-0001eR-FX; Fri, 06 Nov 2020 09:30:22 +0000 Received: from esa6.microchip.iphmx.com ([216.71.154.253]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kay3X-00016c-3p for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 09:29:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604654955; x=1636190955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=gVkb/HduIodWBWgTTPTKx7ktzM9BdW4BzHHiUogCOBA=; b=aRRVyXtUhXR9nPLYByCu9uv2p3ZoXl16TEYLAXm40LwMG4W8Muu6giES ui0Bfm28tNIUUrYxAbJqeDzyAO29grjw0GysA5YpcMpMcGL2rVzW/dHQB u+eoe34K6rkSuXvMy2nehLKT9kyX3ClFf1sR1z0V0ryrO8mntqGLzP0yW b3F6sMDuKs/ozWTwQAcg84AIGdD3nQMkryBDepZfanWVHrFCQcyUIHLfR qzwz1ThOaxxDKukBk9FtfjnMzzqDa/pn7fmb88zaNLGv4h1nOalN7Ambn KkRQd/0i81hcyHnT8f2yixXzBXFHDCGK6ZeZeCJCy4ajk/u00R1lJBiSp w==; IronPort-SDR: brLV06t69z/RE5qkkjWcLaugPFrSLPf8vJKxAkexZDRP3U/bxqRbNv1ga8FZRPWgSQNsD14qrP B5Bym63fGrYRfNlbtDneQ2oOQq2rLNCy7g5ZSd8inOWibWlSr1LqyXprl1yaTjHVUgP+f7z5Ez E/CkyeGBe5mLZTQws0x03maNY/LHj6tTutkg1YeqrzNTRo+/+6FCvca8rshGZjDybrrpEQfbjk sHGJr4Dnn6PyilOQhJ/V7YigCcGynvW1II8OWEq0HWgMUVE3mpFI1K2oqEWg8Tlc24BNfVVsNg szg= X-IronPort-AV: E=Sophos;i="5.77,456,1596524400"; d="scan'208";a="32677829" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Nov 2020 02:29:11 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 6 Nov 2020 02:29:11 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 6 Nov 2020 02:29:06 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 11/11] clk: at91: sama7g5: register cpu clock Date: Fri, 6 Nov 2020 11:28:04 +0200 Message-ID: <1604654884-30339-12-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> References: <1604654884-30339-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_042915_327851_78D6354C X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, eugen.hristev@microchip.com, Claudiu Beznea , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Register CPU clock as being the master clock prescaler. This would be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the frequencies supported by SAMA7G5 could be directly received from CPUPLL + master clock prescaler and the extra divider would do no work in case it would be enabled. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 13 ++++++------- include/dt-bindings/clock/at91.h | 1 + 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index be32d9b88d89..40fceb7595d4 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -885,7 +885,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, + sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); @@ -962,18 +962,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np) } } - parent_names[0] = md_slck_name; - parent_names[1] = "mainck"; - parent_names[2] = "cpupll_divpmcck"; - parent_names[3] = "syspll_divpmcck"; - hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, + parent_names[0] = "cpupll_divpmcck"; + hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_SET_RATE_PARENT, 0); if (IS_ERR(hw)) goto err_free; - hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", + sama7g5_pmc->chws[PMC_CPU] = hw; + + hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, 0); if (IS_ERR(hw)) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index fab313f62e8f..98e1b2ab6403 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -34,6 +34,7 @@ #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) #define PMC_AUDIOIOPLL (PMC_MAIN + 7) #define PMC_ETHPLL (PMC_MAIN + 8) +#define PMC_CPU (PMC_MAIN + 9) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */