From patchwork Fri Nov 2 22:26:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10666253 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94BD4157A for ; Fri, 2 Nov 2018 22:26:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84E872C408 for ; Fri, 2 Nov 2018 22:26:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78BC62C621; Fri, 2 Nov 2018 22:26:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA0192C408 for ; Fri, 2 Nov 2018 22:26:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728221AbeKCHfW (ORCPT ); Sat, 3 Nov 2018 03:35:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36000 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726586AbeKCHfW (ORCPT ); Sat, 3 Nov 2018 03:35:22 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C30146086A; Fri, 2 Nov 2018 22:26:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1541197584; bh=REAteb1Lj7Jv47uJgprba/3u+HoqHfvj4pB94n/PNu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f8TDFm9ad/kvzJi5/d0MBMhdOR115xBQGJXFtx7Xiib3tebtr2EioJR3R3FzK+n2p e4HPu4rMwvZtBblzjkfgHZKaiiCR6RPjvx8mHrcVFeNQQGDY8zEk5JgStUY5ErDwYG 9nVI7zofcH1ZC81IyEuEZrZ/fHcGHk/HsmqIZC4k= Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5BECC606AC; Fri, 2 Nov 2018 22:26:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1541197582; bh=REAteb1Lj7Jv47uJgprba/3u+HoqHfvj4pB94n/PNu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f76CRmm0sEsmMYUhfqfnFNC/eUO5ghUFAwP7W+keivrUUuIxNegZhUdV3JNndWQTx ItUNjfi1hz2g6MXrxzw4VzmLyYjpayLA6N5Zhpab9I5sTHUuUrItsFq56pWzg97rsM CuBNQcQKoXBIRrsQEEyGUP4ilDaxHiHdYJ4iKK7M= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5BECC606AC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jsanka@codeaurora.org From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Jeykumar Sankaran , seanpaul@chromium.org, robdclark@gmail.com, hoegsberg@google.com, robh@kernel.org, mka@chromium.org, dianders@chromium.org Subject: [PATCH v4 1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file Date: Fri, 2 Nov 2018 15:26:14 -0700 Message-Id: <1541197576-19730-2-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> References: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. This change adds MDSS and DSI nodes to enable display on the target device. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu (Rob H) - Use assigned-clocks to set initial clock frequency(Rob H) Changes in v3: - added IOMMU node - Fix device naming (remove _phys) - Use correct IRQ_TYPE in interrupt specifiers Changes in v4: - move mdss node to preserve the unit address sort order - remove _clk suffix from dsi clocks (both the comments are from Doug Anderson) Signed-off-by: Jeykumar Sankaran Signed-off-by: Sean Paul Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 191 +++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b72bdb0..5728b4c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1248,6 +1248,197 @@ }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc 0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi-phy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae94400 0x200>, + <0xae94a00 0x1e0>, + <0xae94600 0x280>; + reg-names = "dsi_phy", + "dsi_pll", + "dsi_phy_lane"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi1_phy>; + phy-names = "dsi-phy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae96400 0x200>, + <0xae96a00 0x10e>, + <0xae96600 0x280>; + reg-names = "dsi_phy", + "dsi_pll", + "dsi_phy_lane"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0xaf00000 0x10000>; From patchwork Fri Nov 2 22:26:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10666257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EDAD17DB for ; Fri, 2 Nov 2018 22:26:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60F2A2C408 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jsanka@codeaurora.org From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Jeykumar Sankaran , seanpaul@chromium.org, robdclark@gmail.com, hoegsberg@google.com, robh@kernel.org, mka@chromium.org, dianders@chromium.org Subject: [PATCH v4 2/3] arm64: dts: sdm845: Add dsi pinctrl nodes Date: Fri, 2 Nov 2018 15:26:15 -0700 Message-Id: <1541197576-19730-3-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> References: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add dsi active/suspend pinctrl nodes to sdm845 SoC dts. Changes in v4: - patch introduced in the series Signed-off-by: Jeykumar Sankaran --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5728b4c..35df5d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -822,6 +822,20 @@ interrupt-controller; #interrupt-cells = <2>; + dpu_dsi_active: dpu-dsi-active { + pinmux { + pins = "gpio6", "gpio52"; + function = "gpio"; + }; + }; + + dpu_dsi_suspend: dpu-dsi-suspend { + pinmux { + pins = "gpio6", "gpio52"; + function = "gpio"; + }; + }; + qup_i2c0_default: qup-i2c0-default { pinmux { pins = "gpio0", "gpio1"; From patchwork Fri Nov 2 22:26:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10666259 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 065BE15E9 for ; Fri, 2 Nov 2018 22:26:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E924B2C408 for ; Fri, 2 Nov 2018 22:26:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA0922C621; Fri, 2 Nov 2018 22:26:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 701002C5F8 for ; Fri, 2 Nov 2018 22:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728318AbeKCHfY (ORCPT ); Sat, 3 Nov 2018 03:35:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36280 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727966AbeKCHfX (ORCPT ); Sat, 3 Nov 2018 03:35:23 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 233F660CEB; Fri, 2 Nov 2018 22:26:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1541197586; bh=423msJ7LRA4iODaPYSmrGzQ4bTn1+4LmdzafYENH0wI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nsACczyPU6sxtF8rsCXibm1+oFl/hyICGKBZ5HkFNWXPDC9g6Yca5LlLvi2cFyLe/ f6vCI0XBgrgxSYhr7WH6g4na/GFoIYvWLavCiSqruEcO9uNkS5sGpU291wfRtp5VSR a19KlBkX/CYoTnY5RQHKuBZ7stgDEokdkYn/WoBA= Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C544660C54; Fri, 2 Nov 2018 22:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1541197585; bh=423msJ7LRA4iODaPYSmrGzQ4bTn1+4LmdzafYENH0wI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TIpyuflYks+WqdCHcvX0aV3aagvA92mzSaikddHY/9jYoH91LLqgo/OFePG42VQYJ bWd1aBMaJypcio6GJLDBvc5sta/X1chNnkIjyvGNPhrweduu0gLlqAFVFsPejT85MV ucYmn9tP2Q7JthTxdxYCZftELgkj5UeciogpFQCQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C544660C54 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jsanka@codeaurora.org From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Jeykumar Sankaran , seanpaul@chromium.org, robdclark@gmail.com, hoegsberg@google.com, robh@kernel.org, mka@chromium.org, dianders@chromium.org Subject: [PATCH v4 3/3] arm64: dts: sdm845: Add display nodes to MTP dts Date: Fri, 2 Nov 2018 15:26:16 -0700 Message-Id: <1541197576-19730-4-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> References: <1541197576-19730-1-git-send-email-jsanka@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add mdss, dsi, dsi_phy, dsi pinctrl and truly nt35597 panel nodes to sdm845 MTP board dtsi. Changes in v4: - patch introduced in the series - move around added nodes to preserve alphabetical order (Doug Anderson) Signed-off-by: Jeykumar Sankaran --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 124 ++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index eedfaf8..eb2a05b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include "sdm845.dtsi" @@ -343,11 +344,118 @@ }; }; +&dsi0 { + status = "okay"; + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + panel@0 { + compatible = "truly,nt35597-2K-display"; + reg = <0>; + + vdda-supply = <&vreg_l14a_1p88>; + vdispp-supply = <&lab_regulator>; + vdispn-supply = <&ibb_regulator>; + + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&dpu_dsi_active>; + pinctrl-1 = <&dpu_dsi_suspend>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + display-timings { + timing0: timing-0 { + /* originally + * 268316160 Mhz, + * but value below fits + * better w/ downstream + */ + clock-frequency = <268316138>; + hactive = <1440>; + vactive = <2560>; + hfront-porch = <200>; + hback-porch = <64>; + hsync-len = <32>; + vfront-porch = <8>; + vback-porch = <7>; + vsync-len = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel1_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&dsi1 { + status = "okay"; + + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + + vdda-supply = <&vdda_mipi_dsi1_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel1_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi1_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi1_pll>; +}; + &i2c10 { status = "okay"; clock-frequency = <400000>; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -419,6 +527,22 @@ /* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&dpu_dsi_active { + pinconf { + pins = "gpio6", "gpio52"; + drive-strength = <8>; + bias-disable; + }; +}; + +&dpu_dsi_suspend { + pinconf { + pins = "gpio6", "gpio52"; + drive-strength = <2>; + bias-pull-down; + }; +}; + &qup_i2c10_default { pinconf { pins = "gpio55", "gpio56";