From patchwork Mon Nov 9 05:33:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 11890479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 460F2C2D0A3 for ; Mon, 9 Nov 2020 05:34:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9CB620897 for ; Mon, 9 Nov 2020 05:34:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mymailcheap.com header.i=@mymailcheap.com header.b="qXiHMHWe"; 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Mon, 9 Nov 2020 05:34:33 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=aosc.io header.i=@aosc.io header.b="xNsQjkv6"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from ice-e5v2.lan (unknown [59.41.163.164]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id CDDDE41E32; Mon, 9 Nov 2020 05:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1604900065; bh=SwvQnJtqUgOiKdb4MC207JwiS1YKn0JykmKbXGcSsCE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xNsQjkv6u2WGKbu7wGyhNi77itJ4KVRL59E/R693qWX29uQMzGoPFsui69w4GgoJn CtuUpMMSBvPaIWY4JANUYaJ3+lGo/NRUTklnwHxPyACX5Obj2Ui/YC8oNlxTzPDIo/ SZxvItj+UKR2i43UCffRsY+l/DXguyFaEvYFY08I= From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ondrej Jirman Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 1/2] clk: sunxi-ng: a64: disable dividers in PLL-CPUX Date: Mon, 9 Nov 2020 13:33:57 +0800 Message-Id: <20201109053358.54220-2-icenowy@aosc.io> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201109053358.54220-1-icenowy@aosc.io> References: <20201109053358.54220-1-icenowy@aosc.io> MIME-Version: 1.0 X-Rspamd-Queue-Id: 80CD641E32 X-Spamd-Result: default: False [4.90 / 20.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; RECEIVED_SPAMHAUS_PBL(0.00)[59.41.163.164:received]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; DMARC_NA(0.00)[aosc.io]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; ML_SERVERS(-3.10)[148.251.23.173]; DKIM_TRACE(0.00)[aosc.io:+]; RCPT_COUNT_SEVEN(0.00)[9]; MID_CONTAINS_FROM(1.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:148.251.0.0/16, country:DE]; RCVD_COUNT_TWO(0.00)[2]; HFILTER_HELO_BAREIP(3.00)[148.251.23.173,1] X-Rspamd-Server: mail20.mymailcheap.com Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org According to the user manual, PLL-CPUX have two dividers, in which P is only allowed when the desired rate is less than 240MHz. As the CCU framework have no such feature yet and the clock rate that allows P is much lower than where we normally operate, disallow the usage of P factor now. M is not restricted in the user manual, however according to the BSP PLL setup table (see [1]), it's not used at all. To follow what the BSP does, disable this factor too. Disabling the dividers will make it possible to remove the need to switch to osc24M when doing frequency scaling on PLL-CPUX. In order to prevent boot-time usage of dividers (current known mainline U-Boot implementation use m = 2), tweaking of the factors are done when probing CCU driver. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 79 ++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 5f66bf879772..6108d150a0e3 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -23,13 +24,14 @@ #include "ccu-sun50i-a64.h" +#define SUN50I_A64_PLL_CPUX_REG 0x000 static struct ccu_nkmp pll_cpux_clk = { .enable = BIT(31), .lock = BIT(28), .n = _SUNXI_CCU_MULT(8, 5), .k = _SUNXI_CCU_MULT(4, 2), - .m = _SUNXI_CCU_DIV(0, 2), - .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + .m = _SUNXI_CCU_DIV_MAX(16, 2, 1), + .p = _SUNXI_CCU_DIV_MAX(0, 2, 1), .common = { .reg = 0x000, .hw.init = CLK_HW_INIT("pll-cpux", @@ -215,6 +217,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", BIT(28), /* lock */ CLK_SET_RATE_UNGATE); +#define SUN50I_A64_CPUX_AXI_REG 0x050 static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux", "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, @@ -954,6 +957,78 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); + /* Disable any possible dividers on PLL-CPUX */ + val = readl(reg + SUN50I_A64_PLL_CPUX_REG); + if (val & (GENMASK(17, 16) | GENMASK(1, 0))) { + unsigned int n, k, m, p; + + n = ((val & GENMASK(12, 8)) >> 8) + 1; + k = ((val & GENMASK(5, 4)) >> 4) + 1; + m = (val & GENMASK(1, 0)) + 1; + p = 1 << ((val & GENMASK(17, 16)) >> 16); + + /* + * Known mainline U-Boot revisions never uses + * divider p, and it will only use m when k = 3 or 4. + * Specially judge for these cases, to satisfy + * what will most possibly happen. + * For m = 2 and k = 3, fractional change will be + * applied to n, to mostly keep the clock rate. + * For m = 2 and k = 4, just change to m = 1 and k = 2. + * For other cases, just try to divide it from N. + */ + if (p >= 2) { + n /= p; + p = 1; + } + + if (m == 2) { + if (k == 3) { + k = 2; + n = n * 3 / 4; + m = 1; + } + if (k == 4) { + k = 2; + m = 1; + } + } + + if (m >= 2) { + n /= m; + m = 1; + } + + /* The user manual constrains n*k >= 10 */ + if (n * k < 10) { + n = 10; + k = 1; + } + + /* Switch CPUX clock to osc24M temporarily */ + val = readl(reg + SUN50I_A64_CPUX_AXI_REG); + val &= ~GENMASK(17, 16); + val |= (1 << 16); + writel(val, reg + SUN50I_A64_CPUX_AXI_REG); + udelay(1); + + /* Setup PLL-CPUX with new factors */ + val = ((n - 1) << 8) | ((k - 1) << 4); + writel(val, reg + SUN50I_A64_PLL_CPUX_REG); + val |= BIT(31); + writel(val, reg + SUN50I_A64_PLL_CPUX_REG); + do { + /* Wait the PLL to lock */ + val = readl(reg + SUN50I_A64_PLL_CPUX_REG); + } while (!(val & BIT(28))); + + /* Switch CPUX clock back to PLL-CPUX */ + val = readl(reg + SUN50I_A64_CPUX_AXI_REG); + val &= ~GENMASK(17, 16); + val |= (2 << 16); + writel(val, reg + SUN50I_A64_CPUX_AXI_REG); + } + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); if (ret) return ret; From patchwork Mon Nov 9 05:35:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 11890487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D89A0C5517A for ; Mon, 9 Nov 2020 05:36:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96EF620E65 for ; Mon, 9 Nov 2020 05:36:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mymailcheap.com header.i=@mymailcheap.com header.b="doPNJ93G"; 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Mon, 9 Nov 2020 05:35:56 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=aosc.io header.i=@aosc.io header.b="GoZvr8ns"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from ice-e5v2.lan (unknown [59.41.163.164]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 0B91C41E32; Mon, 9 Nov 2020 05:35:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1604900151; bh=tQSP6jEb+nlCIph8viKb/ttszWBAoq6XZvKRuUKb5CA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GoZvr8nsejd+rcofAvapYEAmgKRr/rarnr76ZgkcGjmNMEPXTjZMFQmmiWo7i6zxQ ghLCsJS4s65tZ84txvnkmjsIq2ZzakjTYTPf1NDFrDBTv6bcrw8yVOc9bCY02d1z2R DUrLP1pIP25Ld+9StZ2CfUQkHTfKRR9gXJvzK5O8= From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ondrej Jirman Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [RFC PATCH 2/2] clk: sunxi-ng: a64: disable mux and pll notifiers for CPUX reclocking Date: Mon, 9 Nov 2020 13:35:37 +0800 Message-Id: <20201109053537.54450-1-icenowy@aosc.io> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201109053358.54220-1-icenowy@aosc.io> References: <20201109053358.54220-1-icenowy@aosc.io> MIME-Version: 1.0 X-Rspamd-Queue-Id: D7A9A41E32 X-Spamd-Result: default: False [4.90 / 20.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; RECEIVED_SPAMHAUS_PBL(0.00)[59.41.163.164:received]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; DMARC_NA(0.00)[aosc.io]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; ML_SERVERS(-3.10)[148.251.23.173]; DKIM_TRACE(0.00)[aosc.io:+]; RCPT_COUNT_SEVEN(0.00)[9]; MID_CONTAINS_FROM(1.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:148.251.0.0/16, country:DE]; RCVD_COUNT_TWO(0.00)[2]; HFILTER_HELO_BAREIP(3.00)[148.251.23.173,1] X-Rspamd-Server: mail20.mymailcheap.com Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org After the dividers of PLL-CPUX disabled, there's no need for PLL-CPUX to be gated when tweaking the clock of CPUX, thus reparenting CPUX to osc24M is also now not needed. Remove these notifiers. Preventing reparenting CPUX is said to be able to help solving the issue that the timer jumps backward according to Ondrej Jirman. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 6108d150a0e3..67d570efe5bd 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -943,7 +943,6 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) struct resource *res; void __iomem *reg; u32 val; - int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg = devm_ioremap_resource(&pdev->dev, res); @@ -1029,18 +1028,7 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) writel(val, reg + SUN50I_A64_CPUX_AXI_REG); } - ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); - if (ret) - return ret; - - /* Gate then ungate PLL CPU after any rate changes */ - ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb); - - /* Reparent CPU during PLL CPU rate changes */ - ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, - &sun50i_a64_cpu_nb); - - return 0; + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); } static const struct of_device_id sun50i_a64_ccu_ids[] = {