From patchwork Wed Nov 11 16:30:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10369921 for ; Wed, 11 Nov 2020 16:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD9FD2074B for ; Wed, 11 Nov 2020 16:30:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TcGg7wZo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727297AbgKKQaY (ORCPT ); Wed, 11 Nov 2020 11:30:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725867AbgKKQaT (ORCPT ); Wed, 11 Nov 2020 11:30:19 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FB1EC0613D1; Wed, 11 Nov 2020 08:30:19 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id p22so2803520wmg.3; Wed, 11 Nov 2020 08:30:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B4Z4TGbujRr8lzA8mvSLe6pQfLuePfjA32xx1R5acwU=; b=TcGg7wZoHU3Mz7quoPpRmbrozU3kYjLYJ9tPVBCl/RJUKI9kZhR9/kL7Xau+5B1y6b FVEpa5PoQDOh55hABpqUCE0WVEcSCv1+dZzvYoRkYb5CcndMpJPrC4m2xzkwvOwsKPUV mhROj2Hwe3soJU5/lTiaqisvqXuH8zFaWZa+Ni17Ag80cg3iV9+fG0ZbFgYTcQvNC3DF TFJILtlF/AsyBSNeQQsAt7OWYsYWGXHUUEOwEG/TkvBrynPMq04C80f+D2Iwui/BhlTN 2Bjq/xk91LCSHEcrA+JY2v9kfVD1sdpOSGAKvACFdRJuRz6MyPK3hhNrrT4LExn9aK3W BO3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B4Z4TGbujRr8lzA8mvSLe6pQfLuePfjA32xx1R5acwU=; b=sFVAaVtmca4VvvkDj9X4C8ePEEYSeD9mjP/xOVeL3T5RToTOBzAy7wxppD/foPDsKy BvOJZavDP6ebwrOFKLIr1/6qmsl7LWqMaLkwhilDes6pljSdlctNbPG5+4X7LRaUP9Uy bDH0FPD6h0VS3PHeh4W1zhKMEuzzGTKb+gBeU8bM95SohlgkJn4cXOs/h/V18SS1vme3 /YzuQUmU62VvROopsFY0/EnwAT4ImEvkzC55aXhxe+NvaN8xvN9YPwJ+Ivt0KmQibTvW 9hRuIeenUkkNFcbAVfPQ/33oRb6Y/dxtbK96+hBlh+e2DDfdU0+neEsxBk0jB9DNdK62 M20w== X-Gm-Message-State: AOAM531P6yoW+lapEHWlTaypnoVPmKBFtsTrb5OdMWFpKQGcTyNjViFp iEpkZ1ajVeo2Ra7UmIfhe0A= X-Google-Smtp-Source: ABdhPJxYUhF2Px9RpGRLF5QdVMttBLrphbFvtCG8DbH3ut8bbRrCWzIayYGZZ9Qpq35eFuVtX2Vn4w== X-Received: by 2002:a1c:9a12:: with SMTP id c18mr4962941wme.22.1605112217753; Wed, 11 Nov 2020 08:30:17 -0800 (PST) Received: from localhost.localdomain (245.red-79-158-78.dynamicip.rima-tde.net. [79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:17 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 1/7] dt-bindings: clock: add dt binding header for mt7621 clocks Date: Wed, 11 Nov 2020 17:30:07 +0100 Message-Id: <20201111163013.29412-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adds dt binding header for 'mediatek,mt7621-pll' PLL controller and for 'mediatek,mt7621-clk' clock gates. Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..8fccfa514185 --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +/* SYS CLOCKS */ +#define MT7621_CLK_CPU 0 +#define MT7621_CLK_AHB 1 +#define MT7621_CLK_APB 2 +#define MT7621_CLK_MAX 3 + +/* CLOCK GATES */ +#define MT7621_CLK_HSDMA 0 +#define MT7621_CLK_FE 1 +#define MT7621_CLK_SP_DIVTX 2 +#define MT7621_CLK_TIMER 3 +#define MT7621_CLK_INT 4 +#define MT7621_CLK_MC 5 +#define MT7621_CLK_PCM 6 +#define MT7621_CLK_PIO 7 +#define MT7621_CLK_GDMA 8 +#define MT7621_CLK_NAND 9 +#define MT7621_CLK_I2C 10 +#define MT7621_CLK_I2S 11 +#define MT7621_CLK_SPI 12 +#define MT7621_CLK_UART1 13 +#define MT7621_CLK_UART2 14 +#define MT7621_CLK_UART3 15 +#define MT7621_CLK_ETH 16 +#define MT7621_CLK_PCIE0 17 +#define MT7621_CLK_PCIE1 18 +#define MT7621_CLK_PCIE2 19 +#define MT7621_CLK_CRYPTO 20 +#define MT7621_CLK_SHXC 21 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ From patchwork Wed Nov 11 16:30:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5B45921 for ; Wed, 11 Nov 2020 16:30:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D3682074B for ; Wed, 11 Nov 2020 16:30:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HrfamzIN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727656AbgKKQaZ (ORCPT ); Wed, 11 Nov 2020 11:30:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726903AbgKKQaU (ORCPT ); Wed, 11 Nov 2020 11:30:20 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DB9EC0613D4; Wed, 11 Nov 2020 08:30:20 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id 23so3106584wrc.8; Wed, 11 Nov 2020 08:30:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s54TsY1LaGkKl+iAkFm8rVjUJWbXIQClRD94uBdawis=; b=HrfamzINIDhydwxTILAVucMQTnrMpO95GK+SRfXRXl7RxY4tblv7s0KdRJ5f09CBZf vROi1bBPnGzDU8K95jh5ZwsHI0WtFw9S1RyWhe6z+bGeFe/w0TL29JtMu4eBb3c8vkZn YwVBVBbpcmeRgfPra0BM+uwuGFMGgrRdkwfiOdsCa6ZlQ+E4LQ32Kw/3yjbAkmS1b7N6 3EhvJlbL2jlg4SkyeY0LRBHD1vKoP9K6DBSlulOSqaZ4HfNJ2FihwLLtHMzposNebmCk v5yP2/YDUNBG8Nn+kPiKFydTPLsZ6ncdPq+NeC6dQQ5WWeGDR/s7JLXtCf8+9LpsOGCY 6QVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s54TsY1LaGkKl+iAkFm8rVjUJWbXIQClRD94uBdawis=; b=qysX6liX0tNbecpRp/D/xABygFDSp8+rdZhvfR3kvHkQvSKwkYBTtZAsKr8yKVsBNa 4dqejv2rcoVVuGxAEMaO3Q4htzvpBkFY0aO3ywJHHbyH63HIkX080QUW6Mom1sqotzPl EaBL7RL1tumiZwJ5L5zJMDSMN/gJZzNHAM68Ztls7ODBfMPNi3PftUY01QnkRx6VZlOJ 1v85RkE+mXfKPuDj2Qj2SzegpEhZOrHW/QjZ6he/ou06I345UMNXqLXkuElfMjroheWE levxeHgsKImMjR3JD10Oka026L3pYcFMVmY0Gs3lVAVBk5bcF4OZhJjcZNl3UmUaAFLL Bc6Q== X-Gm-Message-State: AOAM533N/ksvNHXt3y4A/SrNoy86zah3BoNi95/kuQWVXAmJTi8aGycF thLtBBFroxTrUJF98uHhbiBZySKhrT2f1gPi X-Google-Smtp-Source: ABdhPJxEcRMWJCADMRQEBlXjs4QVD7mwmyZ3wUn94hAGyBlW/rEl7Ua/wu3z47I2GwcvL0pBVUkmDA== X-Received: by 2002:adf:cd8d:: with SMTP id q13mr18630041wrj.61.1605112219106; Wed, 11 Nov 2020 08:30:19 -0800 (PST) Received: from localhost.localdomain (245.red-79-158-78.dynamicip.rima-tde.net. [79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:18 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 2/7] dt: bindings: add mt7621-pll device tree binding documentation Date: Wed, 11 Nov 2020 17:30:08 +0100 Message-Id: <20201111163013.29412-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adds device tree binding documentation for PLL controller in the MT7621 SOC. Signed-off-by: Sergio Paracuellos Reviewed-by: Rob Herring --- .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml new file mode 100644 index 000000000000..ef58411065e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 PLL Controller Device Tree Bindings + +maintainers: + - Sergio Paracuellos + + +description: | + The PLL Controller provides the cpu clock as well as derived + clock for the bus and the peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + +properties: + compatible: + const: mediatek,mt7621-pll + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + clock-output-names: + maxItems: 3 + +required: + - compatible + - '#clock-cells' + - clock-output-names + +additionalProperties: false + +examples: + - | + #include + + pll { + compatible = "mediatek,mt7621-pll"; + #clock-cells = <1>; + clock-output-names = "cpu", "ahb", "apb"; + }; From patchwork Wed Nov 11 16:30:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6C6015E6 for ; Wed, 11 Nov 2020 16:30:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 97D3620791 for ; Wed, 11 Nov 2020 16:30:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pn3kYXiF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727624AbgKKQaZ (ORCPT ); Wed, 11 Nov 2020 11:30:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727042AbgKKQaW (ORCPT ); Wed, 11 Nov 2020 11:30:22 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B785DC0613D6; Wed, 11 Nov 2020 08:30:21 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id s13so2879816wmh.4; Wed, 11 Nov 2020 08:30:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=++PfnbZC3vsOjTMV4/QIsVDyqBcSjzMP5CR2moKEFno=; b=Pn3kYXiFRIsNDIc0VoRvWLQ213hh86evtZHmnOVhVlO7nm+VgjXp/5/s84XQYX1gjS YWjoheX+AzClRJFy0JKCxDOctMB6nJQg//fxWWowCETxgjTZyLvNJGcMTWgBUxjOWsmP yzSSK8n8wr2ybFbnFcTwdO6n9WVPi59BuoLiU4vstuopoQUhGELzxl+zdvUFe+ofobIJ 5NYYUVPxk55kl2z1ecOyqOwbTB81tVE6PSMIRWafjdhOCfE4xDtAy73TXvlKY+ybp0k7 7kT526hF5bNdxhbMVapHeRGAaDze8YoO1KUW1vaikc/AK5Uurcvh3fmE/x0nZVMEdQGi ddxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=++PfnbZC3vsOjTMV4/QIsVDyqBcSjzMP5CR2moKEFno=; b=TL42/WgScOw/uFoVZ3MoOspVgDY5lhv2PKmx2f/Q5qtxnzmZ0vaZbRsX+pv2RdsMAy mTw3gQXg+e9W6X+zKsfX8dVsB6OJkocXc3nti2OdBmyCxQLyFaTTT+5gbMahymd4Y5N5 Dq6bxC4Ca7zeL3YWZwHTESRYqo4BtU67i7dBxqxTWFc8Thg3SW7G6mSuMs1mJR7b4wxB JWSJB8Yq8H0SZZucYI7e5AWqh/cKXZ2uo4WLAni5i4TS0p7y2UZ/iQEAwIwAmBufXuCH HUPOs3ix71HuqVODGwc7oJdcPoOGz6fJUDAublW9G6Xc8t3YuvdATNIq+i+mBggDqG15 ZsSg== X-Gm-Message-State: AOAM533tUw/GRwjEn/Qyz7PeVQ3RwW7dA81A/8DTEyKijcTeqh7CnF6N 5AGiwn0SbHenWLFJR/SamV0= X-Google-Smtp-Source: ABdhPJxRfdS1AHwmhYY7YyRU4ikpEOWoZLDu8QJOrgwRtShVfT2pkZcR2Cg4yJ5jy47XoPkgTYQvgA== X-Received: by 2002:a1c:1982:: with SMTP id 124mr4970564wmz.74.1605112220494; Wed, 11 Nov 2020 08:30:20 -0800 (PST) Received: from localhost.localdomain (245.red-79-158-78.dynamicip.rima-tde.net. [79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:19 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 3/7] dt: bindings: add mt7621-clk device tree binding documentation Date: Wed, 11 Nov 2020 17:30:09 +0100 Message-Id: <20201111163013.29412-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adds device tree binding documentation for clock gates in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml new file mode 100644 index 000000000000..89886b066849 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Bus Gates Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The MT7621 can gate SoC device clocks. + + Each clock gate is assigned an identifier and client nodes use this identifier + to specify the clock gate which they consume. + + All these identifiers could be found in: + [1]: . + +properties: + compatible: + const: mediatek,mt7621-clk + + "#clock-cells": + description: + The first cell indicates the clock gate number, see [1] for available + clocks. + const: 1 + + ralink,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the syscon which is in the same address area with syscon + device. + +required: + - compatible + - '#clock-cells' + - ralink,sysctl + +additionalProperties: false + +examples: + - | + #include + + clkctrl { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + }; From patchwork Wed Nov 11 16:30:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898147 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 52A63921 for ; Wed, 11 Nov 2020 16:30:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A12020756 for ; Wed, 11 Nov 2020 16:30:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SLqzJtlP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727754AbgKKQa6 (ORCPT ); Wed, 11 Nov 2020 11:30:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726516AbgKKQaX (ORCPT ); Wed, 11 Nov 2020 11:30:23 -0500 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BF91C0617A6; Wed, 11 Nov 2020 08:30:23 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id j7so3137122wrp.3; Wed, 11 Nov 2020 08:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sfgoBgMx0ukozmryc90T0ctPtHbxEn0KGh5GLQjBiSQ=; b=SLqzJtlPq65hn058cZYx4fvQ7ZlvtVirTUIw7FR+nbwrhzuli1lOglLVBPtBP8PoAU p+H3PgqxU5KpDJgCZfB3HJUBg0T40E/sX3H6lkViJ6qgp1lcmcL21JW7gxnetJYmrxX/ u35smbmQlYAgBwLhe7bTbxpcjGHrLWoi6rffWerkyxPXFcMImkpX4dX8xNTLD00q3GLX iUNB7K9vVVQiOqARk794vPBAOdKp2QWSdX/Zxq9meIdT11PXTakzsM7sVMvdy11TBlF0 A8EKFTAaAHVdI66tBD+cVRmfX98KD43wEhrA9Mgf1yw+uKssNnxj3/In51pwKYUvx7GO pqHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfgoBgMx0ukozmryc90T0ctPtHbxEn0KGh5GLQjBiSQ=; b=Rq6qBol3Ys2FOIQ3mV5Rdl4KL9Lw1zbedx5zl4Wuz57cec+EoUo6NhInOGPy8kO3P0 BlOLtd74ud9HzlfsRfGPbltjCROhoR99iqGoXIEHl/jB684a94KzyEx58cMwzFC9KANa eYr7W6qiiy/t98LU5BzGJHci1OVcYUiSaIf+4WgLJ+jnnbeINMI/qHqMpj/LXJDP9LG5 yUQXqm+YpohdZctDpnHXu5jBX5dNMEcRPM2of4FrlpjGRYSLGGl9c9q6OMl0m14lYiu+ 2/XDTuRcsX873FyBLi17KkU/piOZkKq4TEb/kgh9pUx7aO+94clmjPL2A4XLTKZmPxQZ uycg== X-Gm-Message-State: AOAM530fPQQ/hs1r/1xC24/5aTuOjIBsIy0sv5f1ZqXJXSBK6tkKqOxf ZpnV/uC92rhxJ9716wH9pVo= X-Google-Smtp-Source: ABdhPJyo7oK7tVGbMbVwKN3loD2BtC5vy4H7GCmbgUztrZGgPWh/DuCwlxvd1xSzHU1ZYwCHk7E1IQ== X-Received: by 2002:a5d:6506:: with SMTP id x6mr32467046wru.71.1605112221795; Wed, 11 Nov 2020 08:30:21 -0800 (PST) Received: from localhost.localdomain (245.red-79-158-78.dynamicip.rima-tde.net. [79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:21 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 4/7] MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621 Date: Wed, 11 Nov 2020 17:30:10 +0100 Message-Id: <20201111163013.29412-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org For a long time the mt7621 uses a fixed cpu clock which causes a problem if the cpu frequency is not 880MHz. This patch adds cpu/ahb/apb clock calculation code and binds clocks to mt7621-pll node. Adapted from OpenWrt: c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices Signed-off-by: Weijie Gao Signed-off-by: Chuanhong Guo Signed-off-by: Sergio Paracuellos --- arch/mips/include/asm/mach-ralink/mt7621.h | 20 +++++ arch/mips/ralink/mt7621.c | 87 ++++++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h index e1af1ba50bd8..a9f3febddf1c 100644 --- a/arch/mips/include/asm/mach-ralink/mt7621.h +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -17,6 +17,10 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CUR_CLK_STS 0x44 + +#define MEMC_REG_CPU_PLL 0x648 #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 @@ -24,6 +28,22 @@ #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf +#define XTAL_MODE_SEL_MASK 0x7 +#define XTAL_MODE_SEL_SHIFT 6 + +#define CPU_CLK_SEL_MASK 0x3 +#define CPU_CLK_SEL_SHIFT 30 + +#define CUR_CPU_FDIV_MASK 0x1f +#define CUR_CPU_FDIV_SHIFT 8 +#define CUR_CPU_FFRAC_MASK 0x1f +#define CUR_CPU_FFRAC_SHIFT 0 + +#define CPU_PLL_PREDIV_MASK 0x3 +#define CPU_PLL_PREDIV_SHIFT 12 +#define CPU_PLL_FBDIV_MASK 0x7f +#define CPU_PLL_FBDIV_SHIFT 4 + #define MT7621_DRAM_BASE 0x0 #define MT7621_DDR2_SIZE_MIN 32 #define MT7621_DDR2_SIZE_MAX 256 diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ca0ac607b0f3..4fce37e5ea7a 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -9,12 +9,17 @@ #include #include #include +#include +#include +#include +#include #include #include #include #include #include +#include #include @@ -105,11 +110,93 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = { { 0 } }; +static struct clk *clks[MT7621_CLK_MAX]; +static struct clk_onecell_data clk_data = { + .clks = clks, + .clk_num = ARRAY_SIZE(clks), +}; + phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); } +static struct clk *__init mt7621_add_sys_clkdev( + const char *id, const char *parent_id, unsigned long rate) +{ + struct clk *clk; + int err; + + clk = clk_register_fixed_rate(NULL, id, parent_id, 0, rate); + if (IS_ERR(clk)) + panic("failed to allocate %s clock structure", id); + + err = clk_register_clkdev(clk, id, NULL); + if (err) + panic("unable to register %s clock device", id); + + return clk; +} + +#define MHZ(x) ((x) * 1000 * 1000) + +void __init ralink_clk_init(void) +{ + u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; + u32 pll, prediv, fbdiv; + u32 xtal_clk, cpu_clk, ahb_clk, apb_clk; + static const u32 prediv_tbl[] = { 0, 1, 2, 2 }; + + syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; + + clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; + + curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; + + if (xtal_sel <= 2) + xtal_clk = MHZ(20); + else if (xtal_sel <= 5) + xtal_clk = MHZ(40); + else + xtal_clk = MHZ(25); + + switch (clk_sel) { + case 0: + cpu_clk = MHZ(500); + break; + case 1: + pll = rt_memc_r32(MEMC_REG_CPU_PLL); + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; + break; + default: + cpu_clk = xtal_clk; + } + + cpu_clk = cpu_clk / ffiv * ffrac; + ahb_clk = cpu_clk / 4; + apb_clk = MHZ(50); + + clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", NULL, cpu_clk); + clks[MT7621_CLK_AHB] = mt7621_add_sys_clkdev("ahb", NULL, ahb_clk); + clks[MT7621_CLK_APB] = mt7621_add_sys_clkdev("apb", NULL, apb_clk); + + pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); + mips_hpt_frequency = cpu_clk / 2; +} + +static void __init mt7621_clocks_init_dt(struct device_node *np) +{ + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt); + void __init ralink_of_remap(void) { rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); From patchwork Wed Nov 11 16:30:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E1C714C0 for ; Wed, 11 Nov 2020 16:30:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 31C7F20795 for ; Wed, 11 Nov 2020 16:30:56 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:22 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 5/7] clk: ralink: add clock gate driver for mt7621 SoC Date: Wed, 11 Nov 2020 17:30:11 +0100 Message-Id: <20201111163013.29412-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org In mt7621 SoC register 'SYSC_REG_CPLL_CLKCFG1' allows to handle a bunch of gates to enable/disable clocks for all or some ip cores. Add a driver to properly handle them. Parent clocks for this gates are not documented at all in the SoC documentation so all of them have been assumed looking into the clock frequencies used in its related driver code. There are three main clocks which are "cpu", "ahb" and "apb" from the 'mt7621-pll'. The following parents are set to each GATE: * "hsdma": "ahb" * "fe": "ahb" * "sp_divtx": "ahb" * "timer": "cpu" * "int": "cpu" * "mc": "ahb" * "pcm": "ahb" * "pio": "ahb" * "gdma": "ahb" * "nand": "ahb" * "i2c": "ahb" * "i2s": "ahb" * "spi": "ahb" * "uart1": "apb" * "uart2": "apb" * "uart3": "apb" * "eth": "ahb" * "pcie0": "ahb" * "pcie1": "ahb" * "pcie2": "ahb" * "crypto": "ahb" * "shxc": "ahb" With this information the clk driver will provide gate functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: Sergio Paracuellos --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ralink/Kconfig | 14 ++ drivers/clk/ralink/Makefile | 2 + drivers/clk/ralink/clk-mt7621.c | 258 ++++++++++++++++++++++++++++++++ 5 files changed, 276 insertions(+) create mode 100644 drivers/clk/ralink/Kconfig create mode 100644 drivers/clk/ralink/Makefile create mode 100644 drivers/clk/ralink/clk-mt7621.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c715d4681a0b..5f94c4329033 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" +source "drivers/clk/ralink/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index da8fcf147eb1..6578e167b047 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ +obj-y += ralink/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig new file mode 100644 index 000000000000..7e8697327e0c --- /dev/null +++ b/drivers/clk/ralink/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# MediaTek Mt7621 Clock Driver +# +menu "Clock driver for mediatek mt7621 SoC" + depends on SOC_MT7621 || COMPILE_TEST + +config CLK_MT7621 + bool "Clock driver for MediaTek MT7621" + depends on SOC_MT7621 || COMPILE_TEST + default SOC_MT7621 + help + This driver supports MediaTek MT7621 basic clocks. +endmenu diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile new file mode 100644 index 000000000000..cf6f9216379d --- /dev/null +++ b/drivers/clk/ralink/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c new file mode 100644 index 000000000000..f7279d784a36 --- /dev/null +++ b/drivers/clk/ralink/clk-mt7621.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek MT7621 Clock gate Driver + * Author: Sergio Paracuellos + */ + +#include +#include +#include +#include +#include +#include +#include + +/* clock gate configuration register */ +#define SYSC_REG_CLKCFG1 0x30 + +/* Gate register enable bits */ +#define MT7621_HSDMA_CLK_EN BIT(5) +#define MT7621_FE_CLK_EN BIT(6) +#define MT7621_SP_DIVTX_CLK_EN BIT(7) +#define MT7621_TIMER_CLK_EN BIT(8) +#define MT7621_INT_CLK_EN BIT(9) +#define MT7621_MC_CLK_EN BIT(10) +#define MT7621_PCM_CLK_EN BIT(11) +#define MT7621_PIO_CLK_EN BIT(13) +#define MT7621_GDMA_CLK_EN BIT(14) +#define MT7621_NAND_CLK_EN BIT(15) +#define MT7621_I2C_CLK_EN BIT(16) +#define MT7621_I2S_CLK_EN BIT(17) +#define MT7621_SPI_CLK_EN BIT(18) +#define MT7621_UART1_CLK_EN BIT(19) +#define MT7621_UART2_CLK_EN BIT(20) +#define MT7621_UART3_CLK_EN BIT(21) +#define MT7621_ETH_CLK_EN BIT(23) +#define MT7621_PCIE0_CLK_EN BIT(24) +#define MT7621_PCIE1_CLK_EN BIT(25) +#define MT7621_PCIE2_CLK_EN BIT(26) +#define MT7621_CRYPTO_CLK_EN BIT(29) +#define MT7621_SHXC_CLK_EN BIT(30) + +struct mt7621_clk_provider { + struct device_node *node; + struct device *dev; + struct regmap *syscon_regmap; + struct clk_hw_onecell_data *clk_data; +}; + +struct mt7621_gate { + u8 idx; + const char *name; + const char *parent_name; + struct mt7621_clk_provider *clk_prov; + struct clk_hw hw; + u32 bit_idx; +}; + +struct mt7621_gate_data { + u8 idx; + const char *name; + const char *parent_name; + u32 bit_idx; +}; + +#define GATE(_id, _name, _pname, _shift) \ + { \ + .idx = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .bit_idx = _shift \ + } + +static const struct mt7621_gate mt7621_gates[] = { + GATE(MT7621_CLK_HSDMA, "hsdma", "ahb", MT7621_HSDMA_CLK_EN), + GATE(MT7621_CLK_FE, "fe", "ahb", MT7621_FE_CLK_EN), + GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "ahb", MT7621_SP_DIVTX_CLK_EN), + GATE(MT7621_CLK_TIMER, "timer", "cpu", MT7621_TIMER_CLK_EN), + GATE(MT7621_CLK_INT, "int", "cpu", MT7621_INT_CLK_EN), + GATE(MT7621_CLK_MC, "mc", "ahb", MT7621_MC_CLK_EN), + GATE(MT7621_CLK_PCM, "pcm", "ahb", MT7621_PCM_CLK_EN), + GATE(MT7621_CLK_PIO, "pio", "ahb", MT7621_PIO_CLK_EN), + GATE(MT7621_CLK_GDMA, "gdma", "ahb", MT7621_GDMA_CLK_EN), + GATE(MT7621_CLK_NAND, "nand", "ahb", MT7621_NAND_CLK_EN), + GATE(MT7621_CLK_I2C, "i2c", "ahb", MT7621_I2C_CLK_EN), + GATE(MT7621_CLK_I2S, "i2s", "ahb", MT7621_I2S_CLK_EN), + GATE(MT7621_CLK_SPI, "spi", "ahb", MT7621_SPI_CLK_EN), + GATE(MT7621_CLK_UART1, "uart1", "apb", MT7621_UART1_CLK_EN), + GATE(MT7621_CLK_UART2, "uart2", "apb", MT7621_UART2_CLK_EN), + GATE(MT7621_CLK_UART3, "uart3", "apb", MT7621_UART3_CLK_EN), + GATE(MT7621_CLK_ETH, "eth", "ahb", MT7621_ETH_CLK_EN), + GATE(MT7621_CLK_PCIE0, "pcie0", "ahb", MT7621_PCIE0_CLK_EN), + GATE(MT7621_CLK_PCIE1, "pcie1", "ahb", MT7621_PCIE1_CLK_EN), + GATE(MT7621_CLK_PCIE2, "pcie2", "ahb", MT7621_PCIE2_CLK_EN), + GATE(MT7621_CLK_CRYPTO, "crypto", "ahb", MT7621_CRYPTO_CLK_EN), + GATE(MT7621_CLK_SHXC, "shxc", "ahb", MT7621_SHXC_CLK_EN) +}; + +static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw) +{ + return container_of(hw, struct mt7621_gate, hw); +} + +static int mt7621_gate_enable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + + return regmap_update_bits(scon, SYSC_REG_CLKCFG1, + clk_gate->bit_idx, clk_gate->bit_idx); +} + +static void mt7621_gate_disable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + + regmap_update_bits(scon, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); +} + +static int mt7621_gate_is_enabled(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *scon = clk_gate->clk_prov->syscon_regmap; + unsigned int val; + + if (regmap_read(scon, SYSC_REG_CLKCFG1, &val)) + return 0; + + return val & clk_gate->bit_idx; +} + +static const struct clk_ops mt7621_gate_ops = { + .enable = mt7621_gate_enable, + .disable = mt7621_gate_disable, + .is_enabled = mt7621_gate_is_enabled, +}; + +static int mt7621_gate_ops_init(struct device *dev, struct mt7621_gate *sclk) +{ + struct clk_init_data init = { + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .num_parents = 1, + .parent_names = &sclk->parent_name, + .ops = &mt7621_gate_ops, + .name = sclk->name, + }; + + sclk->hw.init = &init; + return devm_clk_hw_register(dev, &sclk->hw); +} + +static int mt7621_register_gates(struct mt7621_clk_provider *clk_prov) +{ + struct clk_hw_onecell_data **clk_data = &clk_prov->clk_data; + struct device *dev = clk_prov->dev; + int idx, err, count; + struct clk_hw **hws; + + count = ARRAY_SIZE(mt7621_gates); + *clk_data = devm_kzalloc(dev, struct_size(*clk_data, hws, count), + GFP_KERNEL); + if (!*clk_data) + return -ENOMEM; + + (*clk_data)->num = count; + hws = (*clk_data)->hws; + + for (idx = 0; idx < ARRAY_SIZE(mt7621_gates); idx++) { + struct mt7621_gate *sclk; + + sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); + if (!sclk) + return -ENOMEM; + + sclk->idx = mt7621_gates[idx].idx; + sclk->name = mt7621_gates[idx].name; + sclk->parent_name = mt7621_gates[idx].parent_name; + sclk->bit_idx = mt7621_gates[idx].bit_idx; + sclk->clk_prov = clk_prov; + + err = mt7621_gate_ops_init(dev, sclk); + if (err) { + dev_err(dev, "failed to register clock %d\n", idx); + devm_kfree(dev, sclk); + hws[idx] = NULL; + } else { + dev_info(dev, "Registered clock gate: %s\n", + mt7621_gates[idx].name); + hws[idx] = &sclk->hw; + } + } + + return 0; +} + +static int mt7621_clk_init(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct mt7621_clk_provider *clk_provider; + int ret; + + clk_provider = devm_kzalloc(dev, sizeof(*clk_provider), GFP_KERNEL); + if (!clk_provider) + return -ENOMEM; + + platform_set_drvdata(pdev, clk_provider); + clk_provider->syscon_regmap = syscon_regmap_lookup_by_phandle(node, "ralink,sysctl"); + if (IS_ERR(clk_provider->syscon_regmap)) { + dev_err(dev, "Could not get syscon regmap\n"); + return -EINVAL; + } + + clk_provider->node = node; + clk_provider->dev = dev; + + ret = mt7621_register_gates(clk_provider); + if (ret) { + dev_err(dev, "Error registering gates\n"); + return ret; + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_provider->clk_data); +} + +static int clk_mt7621_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + + ret = mt7621_clk_init(pdev); + if (ret) { + dev_err(dev, "Could not register clock provider: %s: %d\n", + pdev->name, ret); + return ret; + } + + return 0; +} + +static const struct of_device_id of_match_clk_mt7621[] = { + { .compatible = "mediatek,mt7621-clk", .data = mt7621_clk_init }, + {} +}; + +static struct platform_driver clk_mt7621_drv = { + .probe = clk_mt7621_probe, + .driver = { + .name = "clk-mt7621", + .of_match_table = of_match_clk_mt7621, + }, +}; +builtin_platform_driver(clk_mt7621_drv); + +MODULE_AUTHOR("Sergio Paracuellos "); +MODULE_DESCRIPTION("Mediatek Mt7621 clock gate driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Nov 11 16:30:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 11898137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3941A921 for ; Wed, 11 Nov 2020 16:30:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03AC820756 for ; Wed, 11 Nov 2020 16:30:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L8SwnQiC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727719AbgKKQaj (ORCPT ); Wed, 11 Nov 2020 11:30:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727672AbgKKQa0 (ORCPT ); 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[79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.23 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:24 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 6/7] staging: mt7621-dts: make use of new 'mt7621-pll' and 'mt7621-clk' Date: Wed, 11 Nov 2020 17:30:12 +0100 Message-Id: <20201111163013.29412-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for new mt7621-pll and mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/gbpc1.dts | 11 ---- drivers/staging/mt7621-dts/mt7621.dtsi | 71 ++++++++++++-------------- 2 files changed, 34 insertions(+), 48 deletions(-) diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts index a7c0d3115d72..7716d0efe524 100644 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ b/drivers/staging/mt7621-dts/gbpc1.dts @@ -100,17 +100,6 @@ partition@50000 { }; }; -&sysclock { - compatible = "fixed-clock"; - /* This is normally 1/4 of cpuclock */ - clock-frequency = <225000000>; -}; - -&cpuclock { - compatible = "fixed-clock"; - clock-frequency = <900000000>; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 82aa93634eda..e615139d2ccb 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { #address-cells = <1>; @@ -27,26 +28,16 @@ aliases { serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* This is normally 1/4 of cpuclock */ - clock-frequency = <220000000>; + pll: pll { + compatible = "mediatek,mt7621-pll"; + #clock-cells = <1>; + clock-output-names = "cpu", "ahb", "apb"; }; - mmc_clock: mmc_clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; + clkctrl: clkctrl { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; }; mmc_fixed_3v3: fixedregulator@0 { @@ -76,7 +67,7 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + compatible = "mtk,mt7621-sysc", "syscon"; reg = <0x0 0x100>; }; @@ -100,8 +91,8 @@ i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; - + clocks = <&clkctrl MT7621_CLK_I2C>; + clock-names = "i2c"; resets = <&rstctrl 16>; reset-names = "i2c"; @@ -118,8 +109,8 @@ i2s: i2s@a00 { compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; - + clocks = <&clkctrl MT7621_CLK_I2S>; + clock-names = "i2s"; resets = <&rstctrl 17>; reset-names = "i2s"; @@ -155,8 +146,8 @@ uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + clocks = <&clkctrl MT7621_CLK_UART1>; + clock-names = "uart1"; interrupt-parent = <&gic>; interrupts = ; @@ -172,7 +163,7 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_AHB>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -188,6 +179,8 @@ gdma: gdma@2800 { compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; + clocks = <&clkctrl MT7621_CLK_GDMA>; + clock-names = "gdma"; resets = <&rstctrl 14>; reset-names = "dma"; @@ -205,6 +198,8 @@ hsdma: hsdma@7000 { compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; + clocks = <&clkctrl MT7621_CLK_HSDMA>; + clock-names = "hsdma"; resets = <&rstctrl 5>; reset-names = "hsdma"; @@ -315,11 +310,6 @@ rstctrl: rstctrl { #reset-cells = <1>; }; - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -338,7 +328,8 @@ sdhci: sdhci@1E130000 { pinctrl-0 = <&sdhci_pins>; pinctrl-1 = <&sdhci_pins>; - clocks = <&mmc_clock &mmc_clock>; + clocks = <&pll MT7621_CLK_APB>, + <&pll MT7621_CLK_APB>; clock-names = "source", "hclk"; interrupt-parent = <&gic>; @@ -353,7 +344,7 @@ xhci: xhci@1E1C0000 { 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_AHB>; clock-names = "sys_ck"; interrupt-parent = <&gic>; @@ -372,7 +363,7 @@ gic: interrupt-controller@1fbc0000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; @@ -385,6 +376,9 @@ nand: nand@1e003000 { 0x1e003800 0x800>; #address-cells = <1>; #size-cells = <1>; + + clocks = <&clkctrl MT7621_CLK_NAND>; + clock-names = "nand"; }; ethsys: syscon@1e000000 { @@ -398,8 +392,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysclock>; - clock-names = "ethif"; + clocks = <&pll MT7621_CLK_AHB>, + <&clkctrl MT7621_CLK_ETH>; + clock-names = "ethif", "eth"; #address-cells = <1>; #size-cells = <0>; @@ -532,7 +527,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&clkctrl MT7621_CLK_PCIE0>, + <&clkctrl MT7621_CLK_PCIE1>, + <&clkctrl MT7621_CLK_PCIE2>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; From patchwork Wed Nov 11 16:30:13 2020 Content-Type: text/plain; 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[79.158.78.245]) by smtp.gmail.com with ESMTPSA id w186sm3196753wmb.26.2020.11.11.08.30.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 08:30:25 -0800 (PST) From: Sergio Paracuellos To: mturquette@baylibre.com Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, gregkh@linuxfoundation.org, gch981213@gmail.com, hackpascal@gmail.com, jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org Subject: [PATCH 7/7] MAINTAINERS: add MT7621 CLOCK maintainer Date: Wed, 11 Nov 2020 17:30:13 +0100 Message-Id: <20201111163013.29412-8-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201111163013.29412-1-sergio.paracuellos@gmail.com> References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f1f088a29bc2..c34c12d62355 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11142,6 +11142,14 @@ L: linux-wireless@vger.kernel.org S: Maintained F: drivers/net/wireless/mediatek/mt7601u/ +MEDIATEK MT7621 CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml +F: arch/mips/ralink/mt7621.c +F: drivers/clk/ralink/clk-mt7621.c + MEDIATEK MT7621/28/88 I2C DRIVER M: Stefan Roese L: linux-i2c@vger.kernel.org