From patchwork Mon Nov 5 10:36:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Bugalski X-Patchwork-Id: 10667727 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E09B313A4 for ; Mon, 5 Nov 2018 10:37:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF86429167 for ; Mon, 5 Nov 2018 10:37:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3EB72973A; Mon, 5 Nov 2018 10:37:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F3BA29167 for ; Mon, 5 Nov 2018 10:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729015AbeKET4K (ORCPT ); Mon, 5 Nov 2018 14:56:10 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:34686 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728961AbeKET4J (ORCPT ); Mon, 5 Nov 2018 14:56:09 -0500 Received: by mail-lj1-f193.google.com with SMTP id u6-v6so7551969ljd.1; Mon, 05 Nov 2018 02:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qaZQEoMW2c8ekIzYdfknMh8zhDWr1ixwxJ5V8tHMJDA=; b=CEa+lTEf69oXfbo/KY0Wi04vDhT/9bHb7gDs++7sRu3v9FlONhxL/LTDjwINgHfPs7 Oq/kWqUf53MW4Oe7JQqVtdvDF/ZnqOYryQwyOggdKVgQZ38ozAmu5Mt0FFtTrJ5p+034 sOiLsirqjZH7IHWV2VfEzVhhu9ZMNxVJzKeaEb7zkoK3PWDgVx9L2u+PtFG/vCXKtlt5 Qg1R/6/rRK33lea5EGwS81MXRjWN+cevxBXjqfnQl1Rej/Qmd6+FfhVbRvJed/StfzHS iQVB4MYctAuvz/7mlJY7CtqbpueV3djqbXBhDX0JsPEXx/ln4vGlOUsJ0tFi/aAfwNEw E+hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qaZQEoMW2c8ekIzYdfknMh8zhDWr1ixwxJ5V8tHMJDA=; b=CMgxjiIQZHuy47/S7ohJDXTmXCpGhwMyAml7Sb1uPGR0bXCeTodL7YUkb0nGbFYCVg YUese3XGwcTUAfdRS5P0uQoQxHr2Iul8SD8d0tWgNN4ILlO4vLJm9DMpfKYJsWvPD0t4 A2dH4GJ2tVP1WYd0GO2rc0XT+brq1HaCglilHGzNZVBJqCRyam51giZEWnr03fnwfUdc qRAah+SZQ3xEkVHOya12tlrw/ScfQ4Vvmzin5MLzzLEJUr0Fpflo3Dbz9+hoAIJVWpTJ z+sj80h871+MhUCwhoSZW1BVZnVAoeGp437QtNqUV6bwNQvEyyunpSmfxfhRmj6P7fo3 tdpw== X-Gm-Message-State: AGRZ1gJj9Nqi3JemqpZ9qTdsLdCgMVJF6WmXfemgYpQ1oPqjfVvIcw1F 3eG37Ty/npS91Ci+9tk9Ew== X-Google-Smtp-Source: AJdET5fg+jXX66gG0ldzsayPLBD4EkoOzUKW4Pk07QRA/qTAKRebqfnt3xdtlXsFPYjIi/nDRyZcFA== X-Received: by 2002:a2e:8546:: with SMTP id u6-v6mr1062576ljj.95.1541414224890; Mon, 05 Nov 2018 02:37:04 -0800 (PST) Received: from localhost.localdomain (89-64-7-227.dynamic.chello.pl. [89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:04 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 1/6] mtd: spi-nor: atmel-quaspi: Typo fix Date: Mon, 5 Nov 2018 11:36:20 +0100 Message-Id: <20181105103625.9644-2-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just minor typo fix. Fixed in preparation of new driver. Signed-off: Piotr Bugalski --- drivers/mtd/spi-nor/atmel-quadspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/mtd/spi-nor/atmel-quadspi.c index 820048726b4f..1c5ba8feaa5e 100644 --- a/drivers/mtd/spi-nor/atmel-quadspi.c +++ b/drivers/mtd/spi-nor/atmel-quadspi.c @@ -67,7 +67,7 @@ #define QSPI_CR_LASTXFER BIT(24) /* Bitfields in QSPI_MR (Mode Register) */ -#define QSPI_MR_SSM BIT(0) +#define QSPI_MR_SMM BIT(0) #define QSPI_MR_LLB BIT(1) #define QSPI_MR_WDRBT BIT(2) #define QSPI_MR_SMRM BIT(3) @@ -563,7 +563,7 @@ static int atmel_qspi_init(struct atmel_qspi *aq) qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); /* Set the QSPI controller in Serial Memory Mode */ - mr = QSPI_MR_NBBITS(8) | QSPI_MR_SSM; + mr = QSPI_MR_NBBITS(8) | QSPI_MR_SMM; qspi_writel(aq, QSPI_MR, mr); src_rate = clk_get_rate(aq->clk); From patchwork Mon Nov 5 10:36:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Bugalski X-Patchwork-Id: 10667725 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0341813A4 for ; Mon, 5 Nov 2018 10:37:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E57CF29167 for ; Mon, 5 Nov 2018 10:37:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D8F942973A; Mon, 5 Nov 2018 10:37:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30DFA29167 for ; Mon, 5 Nov 2018 10:37:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727563AbeKET4N (ORCPT ); Mon, 5 Nov 2018 14:56:13 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:37056 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728961AbeKET4M (ORCPT ); Mon, 5 Nov 2018 14:56:12 -0500 Received: by mail-lf1-f68.google.com with SMTP id p17so5743622lfh.4; Mon, 05 Nov 2018 02:37:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tiDzWNyqllEo7nRvS8Rfcn1VaN082+HLeSM3u8Z9BSI=; b=mUsugvxr1iEQp6gEMT8KMtIiG7NHGmGkjfKQyL65K8OT6fp0vxxn1cWk3u/IavqASY HQQqPEIuISQoybHSyL6VNy7Cn1QRpj+936LTeMAAX7lIMa9HE4/mLPKCkdUw2v1omyQx ct7ab/7WCErEMIqsJKxESm38bIqESb80z7oo2qNdg+G8ZfsscGr5qGu8UQ+otREIbzJE +2X/VEAOUvGBzoUiBSU3CRqhE9/LXVIgXFHj5UsTYbGR7GUXhGlI8fetPIDvx7z3ItUg ggP0BCwr4LCESm6ONA4hjrnajLKbPBDqnXeZsiFbifMvfu92FsJ4h2fS5gk6OTPdJXBW Yzjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tiDzWNyqllEo7nRvS8Rfcn1VaN082+HLeSM3u8Z9BSI=; b=cruTsz32Q+el5ujlUWMRpb4FcMFVKYxGjhNCWAtJb4FkwOgQRytTn+y798sxu8GbCp TP4RK7GuwTGu4mE+N6/rg/p+k2wTI6DqnNK2PRD4LeUTek6gDmQTAhf6Y0squ9a33WVl HMJcyDZ090eHASFz9gItu3e/KwDRiABUUrzL1vb9fsR+EM8Q5o26Yd+x53nY9d0nzmDQ 4hO3L8qYBoQAvElIDcd7t4nt1tAivRVAOjzCV/OIHS/N39lM48vF1QNwd4aE2HmuxqqK bR/7xaIY4BUY+K/0NJUmPJfSODaAsMoapHMVbYEWj9Ybz+z1La9+LBOurk1PN1jkkBK6 0UOw== X-Gm-Message-State: AGRZ1gLeJr/oVqCTc5/tsXSAKrn0NqVCW7zG41TADUX6OZ0FUCwC/s/i lt2j/wUI9htE1GWto6y3ew== X-Google-Smtp-Source: AJdET5eWos2yLSuc3zE+s9St2Kxfho2vptphnYE190eD75e3ccacuUNTF+6ab4rPnIlKZycHRFs7tQ== X-Received: by 2002:a19:5a84:: with SMTP id y4mr12689157lfk.156.1541414227357; Mon, 05 Nov 2018 02:37:07 -0800 (PST) Received: from localhost.localdomain (89-64-7-227.dynamic.chello.pl. [89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:06 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 2/6] mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspi Date: Mon, 5 Nov 2018 11:36:21 +0100 Message-Id: <20181105103625.9644-3-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds new interface to existing driver. New code is not used yet, it will be enabled later. Changes are prepared in small steps to keep patches readable. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski --- drivers/mtd/spi-nor/atmel-quadspi.c | 211 ++++++++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/mtd/spi-nor/atmel-quadspi.c index 1c5ba8feaa5e..896478a290ec 100644 --- a/drivers/mtd/spi-nor/atmel-quadspi.c +++ b/drivers/mtd/spi-nor/atmel-quadspi.c @@ -2,8 +2,10 @@ * Driver for Atmel QSPI Controller * * Copyright (C) 2015 Atmel Corporation + * Copyright (C) 2018 Cryptera A/S * * Author: Cyrille Pitchen + * Author: Piotr Bugalski * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -35,6 +37,7 @@ #include #include +#include /* QSPI register offsets */ #define QSPI_CR 0x0000 /* Control Register */ @@ -186,6 +189,23 @@ struct atmel_qspi_command { void *rx_buf; }; +struct qspi_mode { + u8 cmd_buswidth; + u8 addr_buswidth; + u8 data_buswidth; + u32 config; +}; + +static const struct qspi_mode sama5d2_qspi_modes[] = { + { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, + { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, + { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, + { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, + { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, + { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, + { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, +}; + /* Register access functions */ static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg) { @@ -197,6 +217,196 @@ static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value) writel_relaxed(value, aq->regs + reg); } +static inline bool is_compatible(const struct spi_mem_op *op, + const struct qspi_mode *mode) +{ + if (op->cmd.buswidth != mode->cmd_buswidth) + return false; + + if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) + return false; + + if (op->data.nbytes && op->data.buswidth != mode->data_buswidth) + return false; + + return true; +} + +static int find_mode(const struct spi_mem_op *op) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++) + if (is_compatible(op, &sama5d2_qspi_modes[i])) + return i; + + return -1; +} + +static bool atmel_qspi_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (find_mode(op) < 0) + return false; + + /* special case not supported by hardware */ + if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth && + op->dummy.nbytes == 0) + return false; + + return true; +} + +static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); + int mode; + u32 dummy_cycles = 0; + u32 iar, icr, ifr, sr; + int err = 0; + + iar = 0; + icr = QSPI_ICR_INST(op->cmd.opcode); + ifr = QSPI_IFR_INSTEN; + + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); + + mode = find_mode(op); + if (mode < 0) + return -ENOTSUPP; + + ifr |= sama5d2_qspi_modes[mode].config; + + if (op->dummy.buswidth && op->dummy.nbytes) + dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; + + if (op->addr.buswidth) { + switch (op->addr.nbytes) { + case 0: + break; + case 1: + ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; + icr |= QSPI_ICR_OPT(op->addr.val & 0xff); + break; + case 2: + if (dummy_cycles < 8 / op->addr.buswidth) { + ifr &= ~QSPI_IFR_INSTEN; + ifr |= QSPI_IFR_ADDREN; + iar = (op->cmd.opcode << 16) | + (op->addr.val & 0xffff); + } else { + ifr |= QSPI_IFR_ADDREN; + iar = (op->addr.val << 8) & 0xffffff; + dummy_cycles -= 8 / op->addr.buswidth; + } + break; + case 3: + ifr |= QSPI_IFR_ADDREN; + iar = op->addr.val & 0xffffff; + break; + case 4: + ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; + iar = op->addr.val & 0x7ffffff; + break; + default: + return -ENOTSUPP; + } + } + + /* Set number of dummy cycles */ + if (dummy_cycles) + ifr |= QSPI_IFR_NBDUM(dummy_cycles); + + /* Set data enable */ + if (op->data.nbytes) + ifr |= QSPI_IFR_DATAEN; + + if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) + ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; + else + ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; + + /* Clear pending interrupts */ + (void)qspi_readl(aq, QSPI_SR); + + /* Set QSPI Instruction Frame registers */ + qspi_writel(aq, QSPI_IAR, iar); + qspi_writel(aq, QSPI_ICR, icr); + qspi_writel(aq, QSPI_IFR, ifr); + + /* Skip to the final steps if there is no data */ + if (op->data.nbytes) { + /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ + (void)qspi_readl(aq, QSPI_IFR); + + /* Send/Receive data */ + if (op->data.dir == SPI_MEM_DATA_IN) + _memcpy_fromio(op->data.buf.in, + aq->mem + iar, op->data.nbytes); + else + _memcpy_toio(aq->mem + iar, + op->data.buf.out, op->data.nbytes); + + /* Release the chip-select */ + qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); + } + + /* Poll INSTRuction End status */ + sr = qspi_readl(aq, QSPI_SR); + if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) + return err; + + /* Wait for INSTRuction End interrupt */ + reinit_completion(&aq->cmd_completion); + aq->pending = sr & QSPI_SR_CMD_COMPLETED; + qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED); + if (!wait_for_completion_timeout(&aq->cmd_completion, + msecs_to_jiffies(1000))) + err = -ETIMEDOUT; + qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED); + + return err; +} + +const char *atmel_qspi_get_name(struct spi_mem *spimem) +{ + return dev_name(spimem->spi->dev.parent); +} + +static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { + .supports_op = atmel_qspi_supports_op, + .exec_op = atmel_qspi_exec_op, + .get_name = atmel_qspi_get_name +}; + +static int atmel_qspi_setup(struct spi_device *spi) +{ + struct spi_controller *ctrl = spi->master; + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + unsigned long src_rate; + u32 scr, scbr; + + if (ctrl->busy) + return -EBUSY; + + if (!spi->max_speed_hz) + return -EINVAL; + + src_rate = clk_get_rate(aq->clk); + if (!src_rate) + return -EINVAL; + + /* Compute the QSPI baudrate */ + scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz); + if (scbr > 0) + scbr--; + + scr = QSPI_SCR_SCBR(scbr); + qspi_writel(aq, QSPI_SCR, scr); + + return 0; +} + static int atmel_qspi_run_transfer(struct atmel_qspi *aq, const struct atmel_qspi_command *cmd) { @@ -777,5 +987,6 @@ static struct platform_driver atmel_qspi_driver = { module_platform_driver(atmel_qspi_driver); MODULE_AUTHOR("Cyrille Pitchen "); +MODULE_AUTHOR("Piotr Bugalski X-Patchwork-Id: 10667713 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9FCE513A4 for ; Mon, 5 Nov 2018 10:37:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E54D29167 for ; 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[89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:09 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 3/6] mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver Date: Mon, 5 Nov 2018 11:36:22 +0100 Message-Id: <20181105103625.9644-4-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previously added spi-mem interface is now used instead of older approach. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski --- drivers/mtd/spi-nor/atmel-quadspi.c | 91 ++++++++----------------------------- 1 file changed, 18 insertions(+), 73 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/mtd/spi-nor/atmel-quadspi.c index 896478a290ec..644e3f0c1558 100644 --- a/drivers/mtd/spi-nor/atmel-quadspi.c +++ b/drivers/mtd/spi-nor/atmel-quadspi.c @@ -766,27 +766,9 @@ static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len, static int atmel_qspi_init(struct atmel_qspi *aq) { - unsigned long src_rate; - u32 mr, scr, scbr; - /* Reset the QSPI controller */ qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); - /* Set the QSPI controller in Serial Memory Mode */ - mr = QSPI_MR_NBBITS(8) | QSPI_MR_SMM; - qspi_writel(aq, QSPI_MR, mr); - - src_rate = clk_get_rate(aq->clk); - if (!src_rate) - return -EINVAL; - - /* Compute the QSPI baudrate */ - scbr = DIV_ROUND_UP(src_rate, aq->clk_rate); - if (scbr > 0) - scbr--; - scr = QSPI_SCR_SCBR(scbr); - qspi_writel(aq, QSPI_SCR, scr); - /* Enable the QSPI controller */ qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); @@ -814,38 +796,25 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) static int atmel_qspi_probe(struct platform_device *pdev) { - const struct spi_nor_hwcaps hwcaps = { - .mask = SNOR_HWCAPS_READ | - SNOR_HWCAPS_READ_FAST | - SNOR_HWCAPS_READ_1_1_2 | - SNOR_HWCAPS_READ_1_2_2 | - SNOR_HWCAPS_READ_2_2_2 | - SNOR_HWCAPS_READ_1_1_4 | - SNOR_HWCAPS_READ_1_4_4 | - SNOR_HWCAPS_READ_4_4_4 | - SNOR_HWCAPS_PP | - SNOR_HWCAPS_PP_1_1_4 | - SNOR_HWCAPS_PP_1_4_4 | - SNOR_HWCAPS_PP_4_4_4, - }; - struct device_node *child, *np = pdev->dev.of_node; + struct spi_controller *ctrl; struct atmel_qspi *aq; struct resource *res; - struct spi_nor *nor; - struct mtd_info *mtd; int irq, err = 0; - if (of_get_child_count(np) != 1) - return -ENODEV; - child = of_get_next_child(np, NULL); + ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq)); + if (!ctrl) + return -ENOMEM; - aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL); - if (!aq) { - err = -ENOMEM; - goto exit; - } + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + ctrl->setup = atmel_qspi_setup; + ctrl->bus_num = -1; + ctrl->mem_ops = &atmel_qspi_mem_ops; + ctrl->num_chipselect = 1; + ctrl->dev.of_node = pdev->dev.of_node; + platform_set_drvdata(pdev, ctrl); + + aq = spi_controller_get_devdata(ctrl); - platform_set_drvdata(pdev, aq); init_completion(&aq->cmd_completion); aq->pdev = pdev; @@ -894,54 +863,30 @@ static int atmel_qspi_probe(struct platform_device *pdev) if (err) goto disable_clk; - /* Setup the spi-nor */ - nor = &aq->nor; - mtd = &nor->mtd; - - nor->dev = &pdev->dev; - spi_nor_set_flash_node(nor, child); - nor->priv = aq; - mtd->priv = nor; - - nor->read_reg = atmel_qspi_read_reg; - nor->write_reg = atmel_qspi_write_reg; - nor->read = atmel_qspi_read; - nor->write = atmel_qspi_write; - nor->erase = atmel_qspi_erase; - - err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate); - if (err < 0) - goto disable_clk; - err = atmel_qspi_init(aq); if (err) goto disable_clk; - err = spi_nor_scan(nor, NULL, &hwcaps); - if (err) - goto disable_clk; - - err = mtd_device_register(mtd, NULL, 0); + err = spi_register_controller(ctrl); if (err) goto disable_clk; - of_node_put(child); - return 0; disable_clk: clk_disable_unprepare(aq->clk); exit: - of_node_put(child); + spi_controller_put(ctrl); return err; } static int atmel_qspi_remove(struct platform_device *pdev) { - struct atmel_qspi *aq = platform_get_drvdata(pdev); + struct spi_controller *ctrl = platform_get_drvdata(pdev); + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); - mtd_device_unregister(&aq->nor.mtd); + spi_unregister_controller(ctrl); qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS); clk_disable_unprepare(aq->clk); return 0; From patchwork Mon Nov 5 10:36:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Bugalski X-Patchwork-Id: 10667721 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEDA713A4 for ; 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[89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:11 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 4/6] mtd: spi-nor: atmel-quadspi: Remove unused code from atmel-quadspi driver Date: Mon, 5 Nov 2018 11:36:23 +0100 Message-Id: <20181105103625.9644-5-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Code used for previous interface is no longer needed. This change just removes obsolete code. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski --- drivers/mtd/spi-nor/atmel-quadspi.c | 388 ------------------------------------ 1 file changed, 388 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/mtd/spi-nor/atmel-quadspi.c index 644e3f0c1558..ddc712410812 100644 --- a/drivers/mtd/spi-nor/atmel-quadspi.c +++ b/drivers/mtd/spi-nor/atmel-quadspi.c @@ -29,14 +29,9 @@ #include #include #include -#include -#include -#include -#include #include #include -#include #include /* QSPI register offsets */ @@ -160,35 +155,9 @@ struct atmel_qspi { struct clk *clk; struct platform_device *pdev; u32 pending; - - struct spi_nor nor; - u32 clk_rate; struct completion cmd_completion; }; -struct atmel_qspi_command { - union { - struct { - u32 instruction:1; - u32 address:3; - u32 mode:1; - u32 dummy:1; - u32 data:1; - u32 reserved:25; - } bits; - u32 word; - } enable; - u8 instruction; - u8 mode; - u8 num_mode_cycles; - u8 num_dummy_cycles; - u32 address; - - size_t buf_len; - const void *tx_buf; - void *rx_buf; -}; - struct qspi_mode { u8 cmd_buswidth; u8 addr_buswidth; @@ -407,363 +376,6 @@ static int atmel_qspi_setup(struct spi_device *spi) return 0; } -static int atmel_qspi_run_transfer(struct atmel_qspi *aq, - const struct atmel_qspi_command *cmd) -{ - void __iomem *ahb_mem; - - /* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */ - ahb_mem = aq->mem; - if (cmd->enable.bits.address) - ahb_mem += cmd->address; - if (cmd->tx_buf) - _memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len); - else - _memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len); - - return 0; -} - -#ifdef DEBUG -static void atmel_qspi_debug_command(struct atmel_qspi *aq, - const struct atmel_qspi_command *cmd, - u32 ifr) -{ - u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; - size_t len = 0; - int i; - - if (cmd->enable.bits.instruction) - cmd_buf[len++] = cmd->instruction; - - for (i = cmd->enable.bits.address-1; i >= 0; --i) - cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff; - - if (cmd->enable.bits.mode) - cmd_buf[len++] = cmd->mode; - - if (cmd->enable.bits.dummy) { - int num = cmd->num_dummy_cycles; - - switch (ifr & QSPI_IFR_WIDTH_MASK) { - case QSPI_IFR_WIDTH_SINGLE_BIT_SPI: - case QSPI_IFR_WIDTH_DUAL_OUTPUT: - case QSPI_IFR_WIDTH_QUAD_OUTPUT: - num >>= 3; - break; - case QSPI_IFR_WIDTH_DUAL_IO: - case QSPI_IFR_WIDTH_DUAL_CMD: - num >>= 2; - break; - case QSPI_IFR_WIDTH_QUAD_IO: - case QSPI_IFR_WIDTH_QUAD_CMD: - num >>= 1; - break; - default: - return; - } - - for (i = 0; i < num; ++i) - cmd_buf[len++] = 0; - } - - /* Dump the SPI command */ - print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE, - 32, 1, cmd_buf, len, false); - -#ifdef VERBOSE_DEBUG - /* If verbose debug is enabled, also dump the TX data */ - if (cmd->enable.bits.data && cmd->tx_buf) - print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE, - 32, 1, cmd->tx_buf, cmd->buf_len, false); -#endif -} -#else -#define atmel_qspi_debug_command(aq, cmd, ifr) -#endif - -static int atmel_qspi_run_command(struct atmel_qspi *aq, - const struct atmel_qspi_command *cmd, - u32 ifr_tfrtyp, enum spi_nor_protocol proto) -{ - u32 iar, icr, ifr, sr; - int err = 0; - - iar = 0; - icr = 0; - ifr = ifr_tfrtyp; - - /* Set the SPI protocol */ - switch (proto) { - case SNOR_PROTO_1_1_1: - ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI; - break; - - case SNOR_PROTO_1_1_2: - ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT; - break; - - case SNOR_PROTO_1_1_4: - ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT; - break; - - case SNOR_PROTO_1_2_2: - ifr |= QSPI_IFR_WIDTH_DUAL_IO; - break; - - case SNOR_PROTO_1_4_4: - ifr |= QSPI_IFR_WIDTH_QUAD_IO; - break; - - case SNOR_PROTO_2_2_2: - ifr |= QSPI_IFR_WIDTH_DUAL_CMD; - break; - - case SNOR_PROTO_4_4_4: - ifr |= QSPI_IFR_WIDTH_QUAD_CMD; - break; - - default: - return -EINVAL; - } - - /* Compute instruction parameters */ - if (cmd->enable.bits.instruction) { - icr |= QSPI_ICR_INST(cmd->instruction); - ifr |= QSPI_IFR_INSTEN; - } - - /* Compute address parameters */ - switch (cmd->enable.bits.address) { - case 4: - ifr |= QSPI_IFR_ADDRL; - /* fall through to the 24bit (3 byte) address case. */ - case 3: - iar = (cmd->enable.bits.data) ? 0 : cmd->address; - ifr |= QSPI_IFR_ADDREN; - break; - case 0: - break; - default: - return -EINVAL; - } - - /* Compute option parameters */ - if (cmd->enable.bits.mode && cmd->num_mode_cycles) { - u32 mode_cycle_bits, mode_bits; - - icr |= QSPI_ICR_OPT(cmd->mode); - ifr |= QSPI_IFR_OPTEN; - - switch (ifr & QSPI_IFR_WIDTH_MASK) { - case QSPI_IFR_WIDTH_SINGLE_BIT_SPI: - case QSPI_IFR_WIDTH_DUAL_OUTPUT: - case QSPI_IFR_WIDTH_QUAD_OUTPUT: - mode_cycle_bits = 1; - break; - case QSPI_IFR_WIDTH_DUAL_IO: - case QSPI_IFR_WIDTH_DUAL_CMD: - mode_cycle_bits = 2; - break; - case QSPI_IFR_WIDTH_QUAD_IO: - case QSPI_IFR_WIDTH_QUAD_CMD: - mode_cycle_bits = 4; - break; - default: - return -EINVAL; - } - - mode_bits = cmd->num_mode_cycles * mode_cycle_bits; - switch (mode_bits) { - case 1: - ifr |= QSPI_IFR_OPTL_1BIT; - break; - - case 2: - ifr |= QSPI_IFR_OPTL_2BIT; - break; - - case 4: - ifr |= QSPI_IFR_OPTL_4BIT; - break; - - case 8: - ifr |= QSPI_IFR_OPTL_8BIT; - break; - - default: - return -EINVAL; - } - } - - /* Set number of dummy cycles */ - if (cmd->enable.bits.dummy) - ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles); - - /* Set data enable */ - if (cmd->enable.bits.data) { - ifr |= QSPI_IFR_DATAEN; - - /* Special case for Continuous Read Mode */ - if (!cmd->tx_buf && !cmd->rx_buf) - ifr |= QSPI_IFR_CRM; - } - - /* Clear pending interrupts */ - (void)qspi_readl(aq, QSPI_SR); - - /* Set QSPI Instruction Frame registers */ - atmel_qspi_debug_command(aq, cmd, ifr); - qspi_writel(aq, QSPI_IAR, iar); - qspi_writel(aq, QSPI_ICR, icr); - qspi_writel(aq, QSPI_IFR, ifr); - - /* Skip to the final steps if there is no data */ - if (!cmd->enable.bits.data) - goto no_data; - - /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ - (void)qspi_readl(aq, QSPI_IFR); - - /* Stop here for continuous read */ - if (!cmd->tx_buf && !cmd->rx_buf) - return 0; - /* Send/Receive data */ - err = atmel_qspi_run_transfer(aq, cmd); - - /* Release the chip-select */ - qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); - - if (err) - return err; - -#if defined(DEBUG) && defined(VERBOSE_DEBUG) - /* - * If verbose debug is enabled, also dump the RX data in addition to - * the SPI command previously dumped by atmel_qspi_debug_command() - */ - if (cmd->rx_buf) - print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE, - 32, 1, cmd->rx_buf, cmd->buf_len, false); -#endif -no_data: - /* Poll INSTRuction End status */ - sr = qspi_readl(aq, QSPI_SR); - if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) - return err; - - /* Wait for INSTRuction End interrupt */ - reinit_completion(&aq->cmd_completion); - aq->pending = sr & QSPI_SR_CMD_COMPLETED; - qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED); - if (!wait_for_completion_timeout(&aq->cmd_completion, - msecs_to_jiffies(1000))) - err = -ETIMEDOUT; - qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED); - - return err; -} - -static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode, - u8 *buf, int len) -{ - struct atmel_qspi *aq = nor->priv; - struct atmel_qspi_command cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.enable.bits.instruction = 1; - cmd.enable.bits.data = 1; - cmd.instruction = opcode; - cmd.rx_buf = buf; - cmd.buf_len = len; - return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ, - nor->reg_proto); -} - -static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode, - u8 *buf, int len) -{ - struct atmel_qspi *aq = nor->priv; - struct atmel_qspi_command cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.enable.bits.instruction = 1; - cmd.enable.bits.data = (buf != NULL && len > 0); - cmd.instruction = opcode; - cmd.tx_buf = buf; - cmd.buf_len = len; - return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE, - nor->reg_proto); -} - -static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len, - const u_char *write_buf) -{ - struct atmel_qspi *aq = nor->priv; - struct atmel_qspi_command cmd; - ssize_t ret; - - memset(&cmd, 0, sizeof(cmd)); - cmd.enable.bits.instruction = 1; - cmd.enable.bits.address = nor->addr_width; - cmd.enable.bits.data = 1; - cmd.instruction = nor->program_opcode; - cmd.address = (u32)to; - cmd.tx_buf = write_buf; - cmd.buf_len = len; - ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM, - nor->write_proto); - return (ret < 0) ? ret : len; -} - -static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs) -{ - struct atmel_qspi *aq = nor->priv; - struct atmel_qspi_command cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.enable.bits.instruction = 1; - cmd.enable.bits.address = nor->addr_width; - cmd.instruction = nor->erase_opcode; - cmd.address = (u32)offs; - return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE, - nor->reg_proto); -} - -static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len, - u_char *read_buf) -{ - struct atmel_qspi *aq = nor->priv; - struct atmel_qspi_command cmd; - u8 num_mode_cycles, num_dummy_cycles; - ssize_t ret; - - if (nor->read_dummy >= 2) { - num_mode_cycles = 2; - num_dummy_cycles = nor->read_dummy - 2; - } else { - num_mode_cycles = nor->read_dummy; - num_dummy_cycles = 0; - } - - memset(&cmd, 0, sizeof(cmd)); - cmd.enable.bits.instruction = 1; - cmd.enable.bits.address = nor->addr_width; - cmd.enable.bits.mode = (num_mode_cycles > 0); - cmd.enable.bits.dummy = (num_dummy_cycles > 0); - cmd.enable.bits.data = 1; - cmd.instruction = nor->read_opcode; - cmd.address = (u32)from; - cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */ - cmd.num_mode_cycles = num_mode_cycles; - cmd.num_dummy_cycles = num_dummy_cycles; - cmd.rx_buf = read_buf; - cmd.buf_len = len; - ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM, - nor->read_proto); - return (ret < 0) ? ret : len; -} - static int atmel_qspi_init(struct atmel_qspi *aq) { /* Reset the QSPI controller */ From patchwork Mon Nov 5 10:36:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Bugalski X-Patchwork-Id: 10667719 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5992413A4 for ; Mon, 5 Nov 2018 10:37:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47ACB29167 for ; Mon, 5 Nov 2018 10:37:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BF922973A; Mon, 5 Nov 2018 10:37:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4FD629167 for ; Mon, 5 Nov 2018 10:37:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729248AbeKET4X (ORCPT ); Mon, 5 Nov 2018 14:56:23 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:44989 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729198AbeKET4W (ORCPT ); Mon, 5 Nov 2018 14:56:22 -0500 Received: by mail-lj1-f196.google.com with SMTP id k19-v6so7499397lji.11; Mon, 05 Nov 2018 02:37:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v5SrLqwaefxhcu13dG/N9X5a04K90k89Ih63e3RyAys=; b=TGWVK1YRmXP/aebB6wXKwVf0Hjug9Y++cvVhwPNSUqkM5EDwURH53ejCLsgB5bCrBP mH/X1fxQNqUsUztNWVrEoU53vSfMHSRNrkOJ7Ls2G4kRx3s0N4mVhDZE8qyOC9ZoIge3 tU5dcCJGV3a7shpPF9LRabHOq+pl5kGYaVbgF75dUJJkjm1S+Ntu1MBG11MAUNkkb5qG mWmmHCn6N8qaegqk7DXP78BSBXwIXJCCh0LO0YProJg3VGQEUwVJnsSO48ftQoChe1N1 mDa2jqHjY032YLnNvKKuJR3ElgTPxKEKC616J18dRZ3fnHNbCKX3Zp2TpBTysBJ823M3 BzKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v5SrLqwaefxhcu13dG/N9X5a04K90k89Ih63e3RyAys=; b=fi0uGa9dWkusdqUVkbqJNDQoz1+jrnQ2fr593r3Qr4irKl7pi7WvBLYi1FyF3U/xRy LDxQLJiJlWMfidHsSil1a5oZCG/f22LX3K9Ulbt+2gLj+kZeMg2CCEw1Pb37cPeNiItt 6u8eXL9dVBBXEguXAZHYm9FDX2ut31VP1NY4P8ju+ouwfyRYI6EMUYsc1+NRZHbixK2K PRW3RABHxZw4GDfmhNUFJ0jmBeiEtJIVmmMjoiJ0vIi9bycG1RTkg3NIroko1VTqXsin W21GEjWvhBvOhgRMKCf6QU7YVdYXznXIwyiVu+qCiZI4yEfTVJfdFDcsiNNx9qdnpwuN +cVA== X-Gm-Message-State: AGRZ1gI6qs8ux15nf4tgdaPIBMLgmNF3iy29+VM9Qc18oQWgqQ1SF6MD 59H/u+Wm5ncfosJTVxOD8w== X-Google-Smtp-Source: AJdET5eGxRiM0DxyBfEpFi98zsql3a3uCLwL1yTi8X8guYMX6Ale70TxJBKmyIvm3q2Fh8fn57x8lw== X-Received: by 2002:a2e:6594:: with SMTP id e20-v6mr15002634ljf.123.1541414237787; Mon, 05 Nov 2018 02:37:17 -0800 (PST) Received: from localhost.localdomain (89-64-7-227.dynamic.chello.pl. [89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:16 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 5/6] spi: Add QuadSPI driver for Atmel SAMA5D2 Date: Mon, 5 Nov 2018 11:36:24 +0100 Message-Id: <20181105103625.9644-6-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Kernel contains QSPI driver strongly tied to MTD and nor-flash memory. New spi-mem interface allows usage also other memory types, especially much larger NAND with SPI interface. This driver works as SPI controller and is not related to MTD, however can work with NAND-flash or other peripherals using spi-mem interface. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski --- drivers/mtd/spi-nor/Kconfig | 9 --------- drivers/mtd/spi-nor/Makefile | 1 - drivers/spi/Kconfig | 9 +++++++++ drivers/spi/Makefile | 1 + drivers/{mtd/spi-nor => spi}/atmel-quadspi.c | 0 5 files changed, 10 insertions(+), 10 deletions(-) rename drivers/{mtd/spi-nor => spi}/atmel-quadspi.c (100%) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 6cc9c929ff57..44fe8018733c 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -39,15 +39,6 @@ config SPI_ASPEED_SMC and support for the SPI flash memory controller (SPI) for the host firmware. The implementation only supports SPI NOR. -config SPI_ATMEL_QUADSPI - tristate "Atmel Quad SPI Controller" - depends on ARCH_AT91 || (ARM && COMPILE_TEST) - depends on OF && HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. - This driver does not support generic SPI. The implementation only - supports SPI NOR. - config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" depends on OF && (ARM || ARM64 || COMPILE_TEST) diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index f4c61d282abd..a552efd22958 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o -obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c94727e..ca68ac63c6c3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -91,6 +91,15 @@ config SPI_AT91_USART This selects a driver for the AT91 USART Controller as SPI Master, present on AT91 and SAMA5 SoC series. +config SPI_ATMEL_QUADSPI + tristate "Atmel Quad SPI Controller" + depends on ARCH_AT91 || (ARM && COMPILE_TEST) + depends on OF && HAS_IOMEM + help + This enables support for the Quad SPI controller in master mode. + This driver does not support generic SPI. The implementation only + supports spi-mem interface. + config SPI_AU1550 tristate "Au1550/Au1200/Au1300 SPI Controller" depends on MIPS_ALCHEMY diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3575205c5c27..258917db3f56 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o obj-$(CONFIG_SPI_ALTERA) += spi-altera.o obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o +obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o obj-$(CONFIG_SPI_ATH79) += spi-ath79.o obj-$(CONFIG_SPI_AU1550) += spi-au1550.o diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c similarity index 100% rename from drivers/mtd/spi-nor/atmel-quadspi.c rename to drivers/spi/atmel-quadspi.c From patchwork Mon Nov 5 10:36:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Bugalski X-Patchwork-Id: 10667717 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0493C14BD for ; Mon, 5 Nov 2018 10:37:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E7ACD29167 for ; Mon, 5 Nov 2018 10:37:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DBC432973A; Mon, 5 Nov 2018 10:37:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 943A929167 for ; Mon, 5 Nov 2018 10:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729299AbeKET4Y (ORCPT ); Mon, 5 Nov 2018 14:56:24 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:33155 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729197AbeKET4Y (ORCPT ); Mon, 5 Nov 2018 14:56:24 -0500 Received: by mail-lf1-f68.google.com with SMTP id i26so5768808lfc.0; Mon, 05 Nov 2018 02:37:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m6TZp0efiFkYinWCKC0lU0px1N/yD39RLk6D3EMpJfw=; b=D90p0HLTmIlg3qiBF2Ynl2RUXIhckvhVT1hOH8qjXWH9t+JGNgmhS9hKmg2y+sVUWR hJH34GDUnKkMeIMcWuXE+VbfcP6TvRJz6FfwqaRimhVv326BJL3GglAMckhAk4miwX/D 8AhAebqWy0O0s5VCj93FSh7nmUu+ZccfalQ3kH0JS3X8+Iq1UjjwhLWqMpu9o5AQv3gY JrrIHzowrRDHmHfn3qPvtX3QZezbYVkKwBKuZHW/L4quRx9cTHA207QWHajnKy/f1AOQ CIAKygk3Z94MCfrqA5fzYuO7J6OpQ2t8DAV1pRapIm5AhhRk5bu4xLU0eOvR68YVBHNf b9zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m6TZp0efiFkYinWCKC0lU0px1N/yD39RLk6D3EMpJfw=; b=tMSU6sI5C3rJnSmz2ngWvkds1ztRdM+3PCA+KZ73/l83S/2bxPmV2MIS9DtvleqkjT ri43VsG1blkcYfMwhfl5VQ8C1pdFNJkXwMnJwchdBJgM5PhrDtt4pbuMZc8YinJM07m5 jQKyyMVBA/bVqpfn5/PYSMnnqYS9KRS/J8m9cViBQ7oZP0K4UqGG6YdaCi97MWCaRM3K S0dxR8HYXk8LVoCwArqh0qOGhhGrmiWmF0ecg8athafc1nsrqIAEDp4yPHCZEggvkKc2 VItuZ+tndEqCKQ7V9g6pGzRvD7cLq0vfFFmqLOgIsTJmQsO6NpPu4mo1oI4OwaCGYm5y J8cg== X-Gm-Message-State: AGRZ1gJha6FCAZOM1XuijdlGL3Yehi4kgr4irEV1m2SwZu08lyKl6UsG vW/Osek8ZdDhkhzriCiTjQ== X-Google-Smtp-Source: AJdET5d4JryNbbQiRSXHFTXhw2rmAEY5ApN6Jt0SzXSElIDjMB+VNV3pTzoZieJsENKewY+lmlLQ0g== X-Received: by 2002:a19:ca51:: with SMTP id h17mr11616627lfj.126.1541414240357; Mon, 05 Nov 2018 02:37:20 -0800 (PST) Received: from localhost.localdomain (89-64-7-227.dynamic.chello.pl. [89.64.7.227]) by smtp.gmail.com with ESMTPSA id h140-v6sm5413605lfg.4.2018.11.05.02.37.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 02:37:19 -0800 (PST) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [PATCH v3 6/6] dt-bindings: spi: QuadSPI driver for Atmel SAMA5D2 Date: Mon, 5 Nov 2018 11:36:25 +0100 Message-Id: <20181105103625.9644-7-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181105103625.9644-1-bugalski.piotr@gmail.com> References: <20181105103625.9644-1-bugalski.piotr@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Atmel SAMA5D2 QuadSPI driver was moved from mtd to spi subsystem, this change is just moving DT-binding documentation. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/{mtd => spi}/atmel-quadspi.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{mtd => spi}/atmel-quadspi.txt (100%) diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt similarity index 100% rename from Documentation/devicetree/bindings/mtd/atmel-quadspi.txt rename to Documentation/devicetree/bindings/spi/atmel-quadspi.txt